On Thu, May 14, 2020 at 12:59:20PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the mlx5-next tree got a conflict in:
>
> drivers/infiniband/hw/mlx5/main.c
>
> between commit:
>
> 2be08c308f10 ("RDMA/mlx5: Delete create QP flags obfuscation")
>
> from the rdma tree
> + * 1. CPU vs. IOMMU
> + * 2. Guest vs. Host.
> + */
> + switch (addr_width) {
> +#ifdef CONFIG_X86
> + case ADDR_WIDTH_5LEVEL:
> + if (cpu_feature_enabled(X86_FEATURE_LA57) &&
> + cap_5lp_support(iommu->cap)) {
> +
On Wed, May 13, 2020 at 04:01:43PM -0700, Jacob Pan wrote:
> An Intel iommu domain uses 5-level page table by default. If the
> iommu that the domain tries to attach supports less page levels,
> the top level page tables should be skipped. Add a helper to do
> this so that it could be used in
On Wed, 13 May 2020 14:15:21 +0200 Ulf Hansson wrote:
>
>
> On Wed, 13 May 2020 at 11:47, Jisheng Zhang
> wrote:
> >
> > This reverts commit a027b2c5fed78851e69fab395b02d127a7759fc7.
> >
> > The HW supports auto clock gating, so it's useless to do runtime pm
> > in software.
>
> Runtime PM
Hi Jiri,
On 5/13/2020 11:31 PM, Jiri Olsa wrote:
On Fri, May 08, 2020 at 03:58:16PM +0800, Jin Yao wrote:
It would be useful to support the overall statistics for perf-stat
interval mode. For example, report the summary at the end of
"perf-stat -I" output.
But since perf-stat can support many
On Wed 13 May 22:03 PDT 2020, Rajendra Nayak wrote:
>
> []..
>
> > > spi->bus_num = -1;
> > > spi->dev.of_node = dev->of_node;
> > > @@ -596,6 +607,9 @@ static int spi_geni_probe(struct platform_device
> > > *pdev)
> > > spi_geni_probe_runtime_disable:
> > >
When we want to reset the evsel->prev_raw_counts, zeroing the aggr
is not enough, we need to reset the perf_counts too.
The perf_counts__reset zeros the perf_counts, and it should zero
the aggr too. This patch changes perf_counts__reset to non-static,
and calls it in evsel__reset_prev_raw_counts
root@kbl-ppc:~# perf stat --per-thread -e cycles,instructions -I1000
--interval-count 2
1.004171683 perf-3696 8,747,311 cycles
...
1.004171683 perf-3696691,730 instructions
#0.08 insn per cycle
It would be useful to support the overall statistics for perf-stat
interval mode. For example, report the summary at the end of
"perf-stat -I" output.
But since perf-stat can support many aggregation modes, such as
--per-thread, --per-socket, -M and etc, we need a solution which
doesn't bring
To collect the overall statistics for interval mode, we copy the
counts from evsel->prev_raw_counts to evsel->counts.
For AGGR_GLOBAL mode, because the perf_stat_process_counter creates
aggr values from per cpu values, but the per cpu values are 0,
so the calculated aggr values will be always 0.
Currently perf-stat supports to print counts at regular interval (-I),
but it's not very easy for user to get the overall statistics.
With this patchset, it supports to report the summary at the end of
interval output.
For example,
root@kbl-ppc:~# perf stat -e cycles -I1000 --interval-count 2
Hi Volodymyr,
On Thu, 14 May 2020 at 06:48, Volodymyr Babchuk wrote:
>
> Hi Sumit,
>
> On Wed, 13 May 2020 at 11:24, Sumit Garg wrote:
> >
> > Hi Volodymyr,
> >
> > On Wed, 13 May 2020 at 13:30, Jens Wiklander
> > wrote:
> > >
> > > Hi Volodymyr,
> > >
> > > On Wed, May 13, 2020 at 2:36 AM
Currently perf-stat supports to print counts at regular interval (-I),
but it's not very easy for user to get the overall statistics.
The patch uses 'evsel->prev_raw_counts' to get counts for summary.
Copy the counts to 'evsel->counts' after printing the interval results.
Next, we just follow the
On Thu, May 07, 2020 at 10:19:31AM -0600, Jeffrey Hugo wrote:
> The MHI device may be in the syserr state when we attempt to init it in
> power_up(). Since we have no local state, the handling is simple -
> reset the device and wait for it to transition out of the reset state.
>
> Signed-off-by:
On Wed, May 13, 2020 at 09:52:07PM -0700, Linus Torvalds wrote:
> On Wed, May 13, 2020, 20:50 Andy Lutomirski wrote:
>
> >
> > LTO isn’t a linker taking regular .o files full of regular machine
> > code and optimizing it. That’s nuts.
> >
>
> Yeah, you're right. I wear originally thinking just
On Fri 24 Apr 13:25 PDT 2020, Mathieu Poirier wrote:
> Introduce new elf find loaded resource table rproc_ops functions to be
> used when synchonising with an MCU.
>
> Mainly based on the work published by Arnaud Pouliquen [1].
>
> [1].
On Fri 24 Apr 13:25 PDT 2020, Mathieu Poirier wrote:
> Introduce new parse firmware rproc_ops functions to be used when
> synchonising with an MCU.
>
> Mainly based on the work published by Arnaud Pouliquen [1].
>
> [1]. https://patchwork.kernel.org/project/linux-remoteproc/list/?series=239877
On 5/14/20 12:27 PM, Christian Kujau wrote:
On Tue, 12 May 2020, kernel test robot wrote:
FYI, we noticed a -71.8% regression of netperf.Throughput_total_tps due to
commit:
As noted in this report, netperf is used to "measure various aspect of
networking performance". Are we sure the
Hi Yongbo,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on asoc/for-next]
[also build test WARNING on v5.7-rc5 next-20200511]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base'
On Fri 24 Apr 13:24 PDT 2020, Mathieu Poirier wrote:
> Get from the DT the syncon to probe the state of the remote processor
> and the location of the resource table.
>
> Mainly based on the work published by Arnaud Pouliquen [1].
>
> [1].
On Fri 24 Apr 13:24 PDT 2020, Mathieu Poirier wrote:
> Other than one has to be done after the other, there is no correlation
> between memory translation and DT parsing. As move function
> stm32_rproc_of_memory_translations() to stm32_rproc_probe() so that
> stm32_rproc_parse_dt() can be
From: Tudor Ambarus
Spare boards of duplicating the DMA bindings. Describe the flx1
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus
---
From: Tudor Ambarus
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
There is a single functional change in this patch. With the move of the
flx0 uart5
[]..
spi->bus_num = -1;
spi->dev.of_node = dev->of_node;
@@ -596,6 +607,9 @@ static int spi_geni_probe(struct platform_device *pdev)
spi_geni_probe_runtime_disable:
pm_runtime_disable(dev);
spi_master_put(spi);
+ if (mas->se.has_opp_table)
Why do you
From: Tudor Ambarus
Rework the sama5d2 SoC flexcom definitions. The Flexcom IPs are
in the SoC. Move all the flexcom nodes together with their function
definitions in the SoC dtsi. Boards will just fill the pins and enable
the desired functions. With this we remove the duplication of the
flexcom
From: Tudor Ambarus
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 7 -
From: Tudor Ambarus
Spare boards of duplicating the DMA bindings. Describe the flx4
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus
---
From: Tudor Ambarus
Device aliases are board-specific, if needed one should define them
in board dts rather than in the SoC dtsi. If an alias from the SoC
dtsi is addressed by a driver that does not use any of the of_alias*()
methods, we can drop it. This is the case for the i2s aliases, drop
From: Tudor Ambarus
Indicate which i2c alias is for which connector on the board.
Specify that serial0 is for DBGU. This eases tester's life.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Tudor Ambarus
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs.
Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/sama5d2.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Tudor Ambarus
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-sama5d2_icp.dts | 12
From: Tudor Ambarus
Spare boards of duplicating the DMA bindings. Describe the flx3
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus
---
From: Tudor Ambarus
The aliases should be defined in the board dts rather than in the
SoC dtsi. Don't rely on the aliases defined in the SoC dtsi and define
the alias for the Serial DBGU in the board dts file. sama5d2 boards use
the "serial0" alias for the Serial DBGU, do the same for
From: Tudor Ambarus
Describe all the flexcom functions for all the flexcom nodes.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/sama5d2.dtsi | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi
From: Tudor Ambarus
Users can choose which flexcom function to use. Describe the I2C
Flexcom0 function. Add alias for the i2c2 node in order to not rely
on probe order for the i2c device numbering. The sama5d2 SoC has
two dedicated i2c buses and five flexcoms that can function as i2c.
The i2c0
From: Tudor Ambarus
Spare boards of duplicating the DMA bindings. Describe the flx0
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus
---
On Tue, May 5, 2020 at 7:16 AM Thomas Gleixner wrote:
>
> For code simplicity split up the int3 handler into a kernel and user part
> which makes the code flow simpler to understand.
>
> Signed-off-by: Peter Zijlstra (Intel)
> Signed-off-by: Thomas Gleixner
> ---
> arch/x86/kernel/traps.c |
From: Tudor Ambarus
The sama5d2 SoC has the following IPs: [uart0, uart4], {spi0, spi1}, {i2c0,
i2c1}.
Label the flexcom functions in order:
flx0: uart5, spi2, i2c2
flx1: uart6, spi3, i2c3
flx2: uart7, spi4, i2c4
flx3: uart8, spi5, i2c5
flx4: uart9, spi6, i2c6
Some boards respected this
From: Tudor Ambarus
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-kizbox3_common.dtsi | 13
From: Tudor Ambarus
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus
---
arch/arm/boot/dts/at91-kizbox3_common.dtsi | 14
On Fri 24 Apr 13:24 PDT 2020, Mathieu Poirier wrote:
> Remove the remote processor from the process of parsing the device tree
> since (1) there is no correlation between them and (2) to use the
> information that was gathered to make a decision on whether to
> synchronise with the M4 or not.
>
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> Convert #BP to IDTENTRY_RAW:
> - Implement the C entry point with DEFINE_IDTENTRY_RAW
> - Invoke idtentry_enter/exit() from the function body
> - Emit the ASM stub with DECLARE_IDTENTRY_RAW
> - Remove the ASM idtentry in 64bit
>
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> Some exception handlers need to do extra work before any of the entry
> helpers are invoked. Provide IDTENTRY_RAW for this.
Acked-by: Andy Lutomirski
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Peter Zijlstra
>
> Avoid calling out to bsearch() by inlining it, for normal kernel configs
> this was the last external call and poke_int3_handler() is now fully self
> sufficient -- no calls to external code.
>
Acked-by: Andy
On Fri 24 Apr 13:24 PDT 2020, Mathieu Poirier wrote:
> Request IRQ with platform device rather than remote proc in order to
> call stm32_rproc_parse_dt() before rproc_alloc(). That way we can
> know whether we need to synchronise with the MCU or not.
>
> Signed-off-by: Mathieu Poirier
>
On Fri 24 Apr 13:24 PDT 2020, Mathieu Poirier wrote:
> Remove the remote processor from the process of parsing the memory
> ranges since there is no correlation between them.
>
> Signed-off-by: Mathieu Poirier
> Reviewed-by: Loic Pallardy
Reviewed-by: Bjorn Andersson
> ---
>
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Peter Zijlstra
>
> For code that needs the ultimate performance (it can inline the @cmp
> function too) or simply needs to avoid calling external functions for
> whatever reason, provide an __always_inline variant of bsearch().
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Peter Zijlstra
>
> Use arch_atomic_*() and READ_ONCE_NOCHECK() to ensure nothing untoward
> creeps in and ruins things.
>
> That is; this is the INT3 text poke handler, strictly limit the code
> that runs in it, lest it inadvertenly
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> In order to ensure poke_int3_handler() is completely self contained -- this
> is called while modifying other text, imagine the fun of hitting another
> INT3 -- ensure that everything it uses is not traced.
>
>
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #XF to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Handle INVD_BUG in C
> - Remove the ASM idtentry in 64bit
> -
13.05.2020 08:07, Wang, Jiada пишет:
> Hello Dmitry
>
> On 2020/05/12 8:13, Dmitry Osipenko wrote:
>> 11.05.2020 05:05, Wang, Jiada пишет:
>>> Hello Dmitry
>>>
>>> Thanks for your comment and test,
>>>
>>> can you let me know which platform (board) you are using for test,
>>> and DTS changes if
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert the IRET exception handler to IDTENTRY_SW. This is slightly
> different than the conversions of hardware exceptions as the IRET exception
> is invoked via an exception table when IRET faults. So it just
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #AC to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #GP to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #MF to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #SS to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #TS to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #SPURIOUS to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #NP to IDTENTRY_ERRORCODE:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Same as IDTENTRY but the C entry point has an error code argument.
>
Acked-by: Andy Lutomirski
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #OLD_MF to IDTENTRY:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry code
Hey Masahiro,
Your touch might be helpful here. CRYPTO_LIB_CHACHA20POLY1305 is a
tristate and depends on as well as selects other things that are
tristates.
Meanwhile BIG_KEYS is a bool, which needs to select
CRYPTO_LIB_CHACHA20POLY1305. However, it gets antsy if the the symbol
its selecting has
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #NM to IDTENTRY:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry code in
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #UD to IDTENTRY:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry code in
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #BR to IDTENTRY:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry code in
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #OF to IDTENTRY:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry code in
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Convert #DE to IDTENTRY:
> - Implement the C entry point with DEFINE_IDTENTRY
> - Emit the ASM stub with DECLARE_IDTENTRY
> - Remove the ASM idtentry in 64bit
> - Remove the open coded ASM entry code in
On Tue, May 5, 2020 at 7:15 AM Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Prepare for using IDTENTRY to define the C exception/trap entry points. It
> would be possible to glue this into the existing macro maze, but it's
> simpler and better to read at the end to just make them
On Tue, 12 May 2020, kernel test robot wrote:
> FYI, we noticed a -71.8% regression of netperf.Throughput_total_tps due to
> commit:
As noted in this report, netperf is used to "measure various aspect of
networking performance". Are we sure the bisect is correct? JFS is a
filesystem and is not
On Wed, May 13, 2020 at 6:44 PM Mathieu Desnoyers
wrote:
>
> - On May 5, 2020, at 9:44 AM, Thomas Gleixner t...@linutronix.de wrote:
>
> [...]
>
> > +.macro idtentry vector asmsym cfunc has_error_code:req sane=0
> > +SYM_CODE_START(\asmsym)
> > + ASM_CLAC
> > + cld
>
> Looking at the
Hi all,
After merging the keys tree, today's linux-next build (x86_64
allmodconfig) failed like this:
WARNING: unmet direct dependencies detected for CRYPTO_LIB_CHACHA20POLY1305
Depends on [m]: CRYPTO [=y] && (CRYPTO_ARCH_HAVE_LIB_CHACHA [=m] ||
!CRYPTO_ARCH_HAVE_LIB_CHACHA [=m]) &&
The NON_EXISTENT_LUN error can be written without an error condition
on the initiator responsible. Adding the initiatorname to this message
will reduce the effort required to fix this when many initiators are
supported by a target.
Signed-off-by: Lance Digby
---
When receiving reset interrupt, FADDR need to be reset to zero in
periphearl mode. Otherwise ep0 cannot do enumeration when re-pluging USB
cable.
Signed-off-by: Macpaul Lin
---
drivers/usb/musb/mediatek.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/usb/musb/mediatek.c
发件人： Dongyang Zhan
Date: 2020年5月3日周日 下午1:45
Subject: Possible null pointer dereference caused by vmstat_start()
To:
Cc:
In Linux 4.10.17, vmstat_start() stores the results of v =
kmalloc(stat_items_size, GFP_KERNEL) in m->private = v before security
check. If m->private is accessed, it may
Make a substitution of kzalloc with devm_kzalloc to simplify the
ipa_probe() process.
Signed-off-by: Wang Wenhu
Cc: Alex Elder
---
drivers/net/ipa/ipa_clock.c | 7 ++-
drivers/net/ipa/ipa_main.c | 7 ++-
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git
Emil Velikov writes:
> With earlier commits, the API no longer discards the const-ness of the
> sysrq_key_op. As such we can add the notation.
>
> Cc: Greg Kroah-Hartman
> Cc: Jiri Slaby
> Cc: linux-kernel@vger.kernel.org
> Cc: Michael Ellerman
> Cc: Benjamin Herrenschmidt
> Cc: Paul
> On May 13, 2020, at 7:20 PM, Linus Torvalds
> wrote:
>
> On Wed, May 13, 2020 at 5:51 PM Nick Desaulniers
> wrote:
>>
>> Are you sure LTO treats empty asm statements differently than full
>> memory barriers in regards to preventing tail calls?
>
> It had better.
>
> At link-time, there is
My Dear in the lord
My name is Mrs. Mina A. Brunel I am a Norway Citizen who is living in Burkina
Faso, I am married to Mr. Brunel Patrice, a politicians who owns a small gold
company in Burkina Faso; He died of Leprosy and Radesyge, in year February
2010, During his lifetime he deposited
WCN3991 supports transparent WBS (host encoded mSBC). Add a flag to the
device match data to show WBS is supported.
This requires the matching firmware for WCN3991 in linux-firmware:
1a8b0dc00f77 (qca: Enable transparent WBS for WCN3991)
Signed-off-by: Abhishek Pandit-Subedi
---
On Wed, May 13, 2020 at 4:33 AM Jiri Olsa wrote:
>
> On Wed, May 13, 2020 at 12:04:55AM -0700, Ian Rogers wrote:
>
> SNIP
>
> > > +METRICS FILE
> > > +
> > > +The file with metrics has following syntax:
> > > +
> > > + NAME = EXPRESSION ;
> > > + NAME = EXPRESSION ;
> > > + ...
> >
On Mon, 11 May 2020, Mickaël Salaün wrote:
> diff --git a/include/linux/fs.h b/include/linux/fs.h
> index 45cc10cdf6dd..2276642f8e05 100644
> --- a/include/linux/fs.h
> +++ b/include/linux/fs.h
> @@ -1517,6 +1517,11 @@ struct super_block {
> /* Pending fsnotify inode refs */
>
The mm-of-the-moment snapshot 2020-05-13-20-30 has been uploaded to
http://www.ozlabs.org/~akpm/mmotm/
mmotm-readme.txt says
README for mm-of-the-moment:
http://www.ozlabs.org/~akpm/mmotm/
This is a snapshot of my -mm patch queue. Uploaded at random hopefully
more than once a week.
You
allmodconfig
powerpc defconfig
powerpc allyesconfig
powerpc rhel-kconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a006-20200513
i386
We've seen kdump failures with recent kernels (5.5, 5.6, 5.7-rc1) on
amd systems when iommu is enabled in translation mode. In the cases so
far there has been mpt3sas involved, but I'm also seeing io page
faults for ahci right before mpt3sas has an io page fault:
[ 15.156620] ahci
Dear Tiwai san,
First of all, thank you very much all those years you contributed on ALSA.
Couple of days ago I emailed you over updating remark fields.
The purpose of edit was providing more error and meaning to application
engineers.
For example, when snd_pcm_writei returned -EIO,
On Mon, 11 May 2020, Mickaël Salaün wrote:
> + * .. warning::
> + *
> + * It is currently not possible to restrict some file-related actions
> + * accessible through these syscall families: :manpage:`chdir(2)`,
> + * :manpage:`truncate(2)`, :manpage:`stat(2)`, :manpage:`flock(2)`,
> + *
On Wed, May 13, 2020 at 04:27:39PM -0700, Kees Cook wrote:
> Like, couldn't just the entire thing just be:
>
> diff --git a/fs/namei.c b/fs/namei.c
> index a320371899cf..0ab18e19f5da 100644
> --- a/fs/namei.c
> +++ b/fs/namei.c
> @@ -2849,6 +2849,13 @@ static int may_open(const struct path *path,
On Thu, May 14, 2020 at 08:13:48AM +0800, kbuild test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: 24085f70a6e1b0cb647ec92623284641d8270637
> commit: 5990cdee689c6885b27c6d969a3d58b09002b0bc lib/mpi: Fix building for
> powerpc with
Hi all,
Today's linux-next merge of the mlx5-next tree got a conflict in:
drivers/infiniband/hw/mlx5/main.c
between commit:
2be08c308f10 ("RDMA/mlx5: Delete create QP flags obfuscation")
from the rdma tree and commit:
14c129e30152 ("{IB/net}/mlx5: Simplify don't trap code")
from the
- On May 13, 2020, at 8:12 PM, Thomas Gleixner t...@linutronix.de wrote:
[...]
>
>>> Mathieu Desnoyers wrote:
>
>>> Also, color me confused: is "do_signal()" actually running any user-space,
>>> or just setting up the user-space stack for eventual return to signal
>>> handler ?
>
> I'm
On 20-05-13 21:26:47, Tang Bin wrote:
> The function ehci_mxc_drv_probe() does not perform sufficient error
> checking after executing platform_get_irq(), thus fix it.
>
> Fixes: 7e8d5cd93fa ("USB: Add EHCI support for MX27 and MX31 based boards")
> Signed-off-by: Zhang Shengju
> Signed-off-by:
On Wed, May 13, 2020 at 10:41:16PM -0400, Joel Fernandes wrote:
> Hi Thomas,
>
> On Tue, May 05, 2020 at 03:44:05PM +0200, Thomas Gleixner wrote:
>
> Thank you for CC'ing me.
>
> > Interrupts and exceptions invoke rcu_irq_enter() on entry and need to
> > invoke rcu_irq_exit() before they either
On Mon, 11 May 2020, Jeremy Cline wrote:
> On Sat, Feb 22, 2020 at 03:51:24AM +1100, James Morris wrote:
> > On Thu, 20 Feb 2020, Jeremy Cline wrote:
> >
> > > A number of userspace tools, such as systemtap, need a way to see the
> > > current lockdown state so they can gracefully deal with the
On Wed, May 13, 2020 at 6:00 PM Masami Hiramatsu wrote:
>
> > But we should likely at least disallow it entirely on platforms where
> > we really can't - or pick one hardcoded choice. On sparc, you really
> > _have_ to specify one or the other.
>
> OK. BTW, is there any way to detect the
Hi Thomas,
On Tue, May 05, 2020 at 03:44:05PM +0200, Thomas Gleixner wrote:
Thank you for CC'ing me.
> Interrupts and exceptions invoke rcu_irq_enter() on entry and need to
> invoke rcu_irq_exit() before they either return to the interrupted code or
> invoke the scheduler due to preemption.
>
On Wed, May 13, 2020 at 2:09 PM Fabio Estevam wrote:
> The binding doc Documentation/devicetree/bindings/gpu/vivante,gc.yaml
> says that only the 'reg' clock could be optional, the others are
> required.
arch/arm/boot/dts/dove.dtsi only uses the 'core' clock.
arch/arm/boot/dts/stm32mp157.dtsi
allyesconfig
powerpc rhel-kconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a005-20200513
x86_64 randconfig-a003-20200513
x86_64 randconfig-a006-20200513
The patch looks good to me.
Maybe we could add the Fixes tag:
Fixes: fa8dda1edef9 (fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls
support)
Thanks,
Yilun
On Thu, May 14, 2020 at 12:52:05AM +0530, Souptick Joarder wrote:
> Corrected error handling goto sequnece. Level put_pages should
- On May 5, 2020, at 9:49 AM, Thomas Gleixner t...@linutronix.de wrote:
> From: Peter Zijlstra
>
> DR6/7 should be handled before nmi_enter() is invoked and restore after
> nmi_exit() to minimize the exposure.
>
> Split it out into helper inlines and bring it into the correct order.
>
Hi Asutosh,
On Wed, 2020-05-13 at 12:31 -0700, Asutosh Das (asd) wrote:
> On 5/12/2020 3:47 AM, Stanley Chu wrote:
> > Currently UFS host driver promises VCC supply if UFS device
> > needs to do WriteBooster flush during runtime suspend.
> >
> > However the UFS specification mentions,
> >
> >
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