On 06-05-20, 17:25, Samuel Zou wrote:
> Fixes coccicheck warnings:
>
> drivers/dma/ti/k3-udma.c:1294:1-3: WARNING: PTR_ERR_OR_ZERO can be used
> drivers/dma/ti/k3-udma.c:1311:1-3: WARNING: PTR_ERR_OR_ZERO can be used
> drivers/dma/ti/k3-udma.c:1376:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Do not generate SCTP_ADDR_{MADE_PRIM,ADDED} events for SCTP_FUTURE_ASSOC assocs.
These events are described in rfc6458#section-6.1
SCTP_PEER_ADDR_CHANGE:
This tag indicates that an address that is
part of an existing association has experienced a change of
state (e.g., a failure or return to
On Wed, May 13, 2020 at 7:31 AM Pratik Sampat wrote:
>
> Thanks for your comment.
>
>
> On 12/05/20 11:07 pm, Peter Zijlstra wrote:
> > Just a quick note..
> >
> > On Mon, May 11, 2020 at 07:40:55PM +0530, Pratik Rajesh Sampat wrote:
> >
> >> +/*
> >> + * Rearrange the weight distribution
Luis Chamberlain writes:
> On Wed, May 13, 2020 at 08:42:30AM -0500, Eric W. Biederman wrote:
>> Luis Chamberlain writes:
>>
>> > On Tue, May 12, 2020 at 12:40:55PM -0500, Eric W. Biederman wrote:
>> >> Luis Chamberlain writes:
>> >>
>> >> > On Tue, May 12, 2020 at 06:52:35AM -0500, Eric W.
On Tue 12-05-20 22:43:23, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Add a flag to preserve FS_XFLAG_DAX in the ext4 inode.
>
> Set the flag to be user visible and changeable. Set the flag to be
> inherited. Allow applications to change the flag at any time.
>
> Finally, on regular
On Wed, May 13, 2020 at 11:08:25AM -0300, Arnaldo Carvalho de Melo wrote:
> Em Wed, May 13, 2020 at 01:34:24PM +0200, Jiri Olsa escreveu:
> > On Wed, May 13, 2020 at 12:09:30AM -0700, Ian Rogers wrote:
> > > On Mon, May 11, 2020 at 1:54 PM Jiri Olsa wrote:
> > > >
> > > > Display line number on
On 13/05/2020 13:24, Thomas Gleixner wrote:
> Why would the SMP call function single interrupt go through the
> PLATFORM_IPI_VECTOR? It goes as the name says through the
> CALL_FUNCTION_SINGLE_VECTOR.
>
Wrong vector, my bad.
However 2) still stands in my opinion. We don't have "ipi raise"
On Wed, May 13, 2020 at 03:44:22PM +0300, Serge Semin wrote:
> On Fri, May 08, 2020 at 10:30:27PM +0300, Andy Shevchenko wrote:
> > On Fri, May 08, 2020 at 04:29:42PM +0300, Serge Semin wrote:
> > > DebugFS kernel interface provides a dedicated method to create the
> > > registers dump file. Use
The BD71837 had a HW "feature" where changing the regulator output
voltages of other regulators but bucks 1-4 might cause spikes if
regulators were enabled. Thus SW prohibit voltage changes for other
regulators except for bucks 1-4 when regulator is enabled.
The HW colleagues did inadvertly fix
The device tree binding declares the ti,mic-bias-source and the
ti,vref-source properties as u32. The code reads them as u8 which is
incorrect. Since the device tree binding indicates them as u32 the
conde needs to be updated to read u32.
In addition the bias source needs to be shifted 4 bits
On Thu 2020-04-30 19:14:34, Alper Nebi Yasak wrote:
> I recently experienced some trouble with setting up an encrypted-root
> system, my Chromebook Plus (rk3399-gru-kevin, ARM64) would appear to
> hang where it should have asked for an encryption passphrase; and I
> eventually figured out that the
On Tue 12-05-20 22:43:22, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> We add 'always', 'never', and 'inode' (default). '-o dax' continue to
> operate the same.
>
> Specifically we introduce a 2nd DAX mount flag EXT4_MOUNT2_DAX_NEVER and set
> it and EXT4_MOUNT_DAX_ALWAYS appropriately.
>
> > + reason: panic, oops, emergency, shutdown(ordered by severity)
> > + handling: restart, halt, poweroff
> >
> > Or we might just replace KMSG_DUMP_RESTART, KMSG_DUMP_HALT,
> > KMSG_DUMP_POWEROFF with a single KMSG_DUMP_SHUTDOWN.
> >
> > Then the max reason variable would make sense.
>
From: Oliver Graute
Set Gamma Values and Register Values for the HSD20_IPS Panel
Signed-off-by: Oliver Graute
---
need information howto set HSD20_IPS Panel at run time and not at compile time
Changes for v2:
- added define for HSD20_IPS_GAMMA values
- check for HSD20_IPS define
- enabled
On 28/04/2020 15:17, Bernard Zhao wrote:
> pm_resump api did not handle drm_mode_config_helper_resume error.
> This change add handle to return drm_mode_config_helper_resume`s
> error number. This code logic is aligned with api pm_suspend.
> After this change, the code maybe a bit readable.
>
>
On 3/20/20 3:16 AM, Michael Kelley wrote:
> From: Arnd Bergmann Sent: Wednesday, March 18, 2020 2:27 AM
>>
>> On Wed, Mar 18, 2020 at 1:18 AM Michael Kelley
>> wrote:
>>> From: Arnd Bergmann
On Sat, Mar 14, 2020 at 4:36 PM Michael Kelley
wrote:
>
> The Hyper-V frame buffer
Vivek Goyal writes:
> On Wed, May 13, 2020 at 11:03:48AM +0200, Vitaly Kuznetsov wrote:
>> Vivek Goyal writes:
>>
>> > On Tue, May 12, 2020 at 05:50:53PM +0200, Vitaly Kuznetsov wrote:
>> >> Vivek Goyal writes:
>> >>
>> >> >
>> >> > So if we are using a common structure
Hi Marek,
Thank you for the patch.
On Wed, May 13, 2020 at 03:32:36PM +0200, Marek Szyprowski wrote:
> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
> returns the number of the created entries in the DMA address space.
> However the subsequent calls to the
On Tue, May 12, 2020 at 09:42:30PM -0500, Rob Herring wrote:
> On Tue, May 05, 2020 at 11:45:10AM -0400, Pavel Tatashin wrote:
> > Currently, it is possible to dump kmsges for panic, or oops.
> > With max_reason it is possible to dump messages for other
> > kmesg_dump events, for example reboot,
On Fri, May 08, 2020 at 09:10:35PM +0200, Clément Péron wrote:
> Enable CPU opp tables for Tanix TX6.
>
> Also add the fixed regulator that provided vdd-cpu-gpu required for
> CPU opp tables.
>
> This voltage has been found using a voltmeter and could be wrong.
>
> Tested-by: Jernej Škrabec
>
On 20/04/2020 22:26, Martin Blumenstingl wrote:
> Add support for the Meson GX SoCs to the meson-ee-pwrc driver.
>
> The power domains on the GX SoCs are very similar to G12A. The only
> known differences so far are:
> - The GX SoCs do not have the HHI_VPU_MEM_PD_REG2 register (for the
> VPU
On Wed, May 13, 2020 at 7:13 AM Luis Chamberlain wrote:
>
> On Wed, May 13, 2020 at 06:49:50AM +0100, Al Viro wrote:
> > On Tue, May 12, 2020 at 01:43:05PM -0600, Shuah Khan wrote:
> > > diff --git a/fs/exec.c b/fs/exec.c
> > > index 06b4c550af5d..ea24bdce939d 100644
> > > --- a/fs/exec.c
> > >
On Wed, May 06, 2020 at 04:15:12PM +0800, Samuel Zou wrote:
> Fixes coccicheck warning:
>
> sound/soc/sunxi/sun4i-i2s.c:1177:1-3: WARNING: PTR_ERR_OR_ZERO can be used
>
> Reported-by: Hulk Robot
> Signed-off-by: Samuel Zou
Didn't we remove that coccicheck test?
Maxime
signature.asc
Delete the duplicate "to" possibly double-typed.
Signed-off-by: Wang Wenhu
Cc: Viresh Kumar
---
include/linux/cpufreq.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index f7240251a949..67d5950bd878 100644
---
On 20/04/2020 22:26, Martin Blumenstingl wrote:
> This adds support for the power domains on Meson8/Meson8b/Meson8m2.
> Meson8 doesn't use any reset lines while Meson8b and Meson8m2 use the
> same set of reset lines (which is different from the newer SoCs).
> Add dedicated compatible strings for
On Mon, May 11, 2020 at 06:47:44PM +0200, Vitaly Kuznetsov wrote:
> Concerns were expressed around (ab)using #PF for KVM's async_pf mechanism,
> it seems that re-using #PF exception for a PV mechanism wasn't a great
> idea after all. The Grand Plan is to switch to using e.g. #VE for 'page
> not
Arnaldo Carvalho de Melo wrote:
Em Mon, May 11, 2020 at 11:45:09PM +0530, Sandipan Das escreveu:
On 09/05/20 4:51 pm, Ravi Bangoria wrote:
> Commit 7eec00a74720 ("perf symbols: Consolidate symbol fixup issue")
> removed powerpc specific sym-handling.c file from Build. This wasn't
> caught by
Balbir Singh writes:
> @@ -550,8 +549,10 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct
> mm_struct *next,
>* Avoid user/user BTB poisoning by flushing the branch
>* predictor when switching between processes. This stops
>* one process
Russell,
Thanks for the feedback.
On 13/05/2020 at 15:05, Russell King - ARM Linux admin wrote:
On Wed, May 06, 2020 at 01:37:39PM +0200, nicolas.fe...@microchip.com wrote:
From: Nicolas Ferre
Keep previous function goals and integrate phylink actions to them.
phylink_ethtool_get_wol() is
On Wed, May 13, 2020 at 08:42:30AM -0500, Eric W. Biederman wrote:
> Luis Chamberlain writes:
>
> > On Tue, May 12, 2020 at 12:40:55PM -0500, Eric W. Biederman wrote:
> >> Luis Chamberlain writes:
> >>
> >> > On Tue, May 12, 2020 at 06:52:35AM -0500, Eric W. Biederman wrote:
> >> >> Luis
On Wed, 13 May 2020 at 10:11, Mika Westerberg
wrote:
> > I can fix up all those, but out of interest how did you "know" the
> > right three digit identifier to use?
> I work for Intel ;-)
Hah, okay, thanks :)
> > I'm really wondering if drivers/mfd/lpc_ich.c is the right place for
> > this kind
This is an add-on series to the main SoC Sparx5 series
(Message-ID: <20200513125532.24585-1-lars.povl...@microchip.com>).
The series add support for the serial GPIO controller used by Sparx5,
as well as (MSCC) ocelot/jaguar2.
The GPIO controller only supports output mode currently.
It is
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 52 +++
.../boot/dts/microchip/sparx5_pcb125.dts | 5 ++
This adds DT bindings for the Microsemi SGPIO controller, bindings
mscc,ocelot-sgpio and mscc,luton-sgpio.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/pinctrl/mscc,ocelot-sgpio.yaml | 66 +++
MAINTAINERS | 1 +
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
MAINTAINERS | 1 +
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile
Hi
Am 13.05.20 um 13:41 schrieb Wambui Karuga:
> Introduce the ability to track requests for the addition of drm debugfs
> files at any time and have them added all at once during
> drm_dev_register().
>
> Drivers can add drm debugfs file requests to a new list tied to drm_device.
> During
Em Wed, May 13, 2020 at 01:34:24PM +0200, Jiri Olsa escreveu:
> On Wed, May 13, 2020 at 12:09:30AM -0700, Ian Rogers wrote:
> > On Mon, May 11, 2020 at 1:54 PM Jiri Olsa wrote:
> > >
> > > Display line number on when parsing custom metrics file, like:
> > >
> > > $ cat metrics
> > > // IPC
>
Function isolate_migratepages_block() runs some checks out of lru_lock
when choose pages for migration. After checking PageLRU() it checks extra
page references by comparing page_count() and page_mapcount(). Between
these two checks page could be removed from lru, freed and taken by slab.
As a
Here is a final patch to solve that hugetlb_get_unmapped_area() can't
get unmapped area below mmap base for huge pages based on a few previous
discussions and patches from me.
I'm so sorry. When sending v2 and v3 patches, I forget to cc:
linux...@kvack.org and linux-kernel@vger.kernel.org. No
On Tue, May 12, 2020 at 12:19:30AM +0100, Bryan O'Donoghue wrote:
> This patch adds USB role switch support to the tps6598x.
>
> The setup to initiate or accept a data-role switch is both assumed and
> currently required to be baked-into the firmware as described in TI's
> document here.
>
>
On 13/05/20 14:43, john mathew wrote:
> +=
> +Capacity-Aware Scheduling
> +=
> +
Thanks for taking a jab at this. At a glance it looks okay, with one
comment below.
FWIW I still intend to write a more pamphlet-sized thing, I'll toss
something out
On 2020/05/13 22:46, Steven Rostedt wrote:
> On Wed, 13 May 2020 20:03:53 +0900
> Tetsuo Handa wrote:
>
>> I think that basically only oops (e.g. WARN()/BUG()/panic()) messages worth
>> printing to consoles and the rest messages do not worth printing to consoles.
>> Existing KERN_$LOGLEVEL is
Em Wed, May 13, 2020 at 01:39:41PM +0200, Jiri Olsa escreveu:
> On Wed, May 13, 2020 at 12:20:23PM +1000, Anand K Mistry wrote:
> > The setting and checking of 'done' contains a rare race where the signal
> > handler setting 'done' is run after checking to break the loop, but
> > before waiting in
On Wed, May 13, 2020 at 09:53:50AM -0400, Vivek Goyal wrote:
[..]
> > > And this notion of same structure being shared across multiple events
> > > at the same time is just going to create more confusion, IMHO. If we
> > > can decouple it by serializing it, that definitely feels simpler to
> > >
On Wed, May 13, 2020 at 08:02:14AM -0500, Rob Herring wrote:
> On Wed, May 13, 2020 at 7:10 AM Mark Brown wrote:
> > [1/1] spi: dt-bindings: sifive: Add missing 2nd register region
> > commit: b265b5a0ba15b6e00abce9bf162926e84b4323b4
> You missed my ask for an ack. This is a dependency
This add DT bindings for the Sparx5 SPI driver.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/spi/mscc,ocelot-spi.yaml | 49 +++
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git
With this change a SPI controller can be added without having a IRQ
associated, and causing all transfers to be polled. For SPI controllers
without DMA, this can significantly improve performance by less
interrupt handling overhead.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
This add spi-nor device nodes to the Sparx5 reference boards.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++--
arch/arm64/boot/dts/microchip/sparx5_pcb125.dts| 9 +
This adds a SPI controller to the Microchip Sparx5 SoC
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
This add support for the RX_SAMPLE_DLY register. If enabled in the
Designware IP, it allows tuning of the rx data signal by means of an
internal rx sample fifo.
The register is located at offset 0xf0, and if the option is not
enabled in the IP, changing the register will have no effect.
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 20
.../boot/dts/microchip/sparx5_pcb125.dts | 7 ++
This minor change allow dw-spi drivers to register
spi_controller_mem_ops memory operations if the platform supports it.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
drivers/spi/spi-dw.c | 3 +++
drivers/spi/spi-dw.h | 2 ++
2 files changed, 5 insertions(+)
diff --git
This adds support for the Sparx5 SoC in the spi-dw-mchp SPI controller.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
drivers/spi/spi-dw-mchp.c | 211 ++
1 file changed, 189 insertions(+), 22 deletions(-)
diff --git
This patch spins off the MSCC platforms into a separate driver, as
adding new platforms from the MSCC/Microchip product lines will
further complicate (clutter) the original driver.
The new 'spi-dw-mchp' driver still builds on the dw-spi foundation.
Reviewed-by: Alexandre Belloni
Signed-off-by:
This add DT bindings for the Microsemi/Microchip SPI controller used
in various SoC's. It describes the "mscc,ocelot-spi" and
"mscc,jaguar2-spi" bindings.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/spi/mscc,ocelot-spi.yaml | 60 +++
This is an add-on series to the main SoC Sparx5 series
(Message-ID: <20200513125532.24585-1-lars.povl...@microchip.com>).
The series add support for Sparx5 on top of the existing
ocelot/jaguar2 spi driver.
It spins off the existing support for the MSCC platforms into a
separate driver, as adding
On Wed, 13 May 2020 at 15:24, Peter Zijlstra wrote:
>
> On Wed, May 13, 2020 at 03:15:55PM +0200, Marco Elver wrote:
> > So far so good, except: both __no_sanitize_or_inline and
> > __no_kcsan_or_inline *do* avoid KCSAN instrumenting plain accesses, it
> > just doesn't avoid explicit kcsan_check
HiFive unleashed A00 board has VSC8541-01 ethernet phy, this device is
identified as a Revision B device as described in device identification
registers. In order to use this phy in the unmanaged mode, it requires
a specific reset sequence of logical 0-1-0-1 transition on the NRESET pin
as
The GEMGXL_RST line on HiFive Unleashed is pulled low and is
using GPIO number 12. Add these reset-gpio details to dt-node
using which the linux phylib can reset the phy.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 1 +
1 file changed, 1
HiFive Unleashed is having VSC8541-01 ethernet phy device and requires a
specific reset sequence of 0-1-0-1 in order to use it in unmanaged mode.
This series addresses a corner case where phy reset is not handled by boot
stages prior to linux.
Somewhat similar unreliable phy probe failure was
Ethernet phy VSC8541-01 on HiFive Unleashed has its reset line
connected to a gpio, so enable GPIO driver's required to reset
the phy.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/configs/defconfig
Although not exactly identical, unthrottle_cfs_rq() and enqueue_task_fair()
are quite close and follow the same sequence for enqueuing an entity in the
cfs hierarchy. Modify unthrottle_cfs_rq() to use the same pattern as
enqueue_task_fair(). This fixes a problem already faced with the latter and
enqueue_task_fair jumps to enqueue_throttle label when cfs_rq_of(se) is
throttled which means that se can't be NULL in such case and we can move
the label after the if (!se) statement. Futhermore, the latter can be
removed because se is always NULL when reaching this point.
Reviewed-by: Phil Auld
On Wed, May 13, 2020 at 02:46:31PM +0100, Jon Hunter wrote:
>
> On 13/05/2020 10:43, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 5.6.13 release.
> > There are 118 patches in this series, all will be posted as a response
> > to this one. If anyone has any
On Wed, 13 May 2020 20:03:53 +0900
Tetsuo Handa wrote:
> I think that basically only oops (e.g. WARN()/BUG()/panic()) messages worth
> printing to consoles and the rest messages do not worth printing to consoles.
> Existing KERN_$LOGLEVEL is too rough-grained.
Why don't you look into having a
Balbir Singh writes:
> +++ b/arch/x86/kernel/l1d_flush.c
> @@ -0,0 +1,36 @@
Lacks
+// SPDX-License-Identifier: GPL-2.0-only
On Wed, May 13, 2020 at 11:03:48AM +0200, Vitaly Kuznetsov wrote:
> Vivek Goyal writes:
>
> > On Tue, May 12, 2020 at 05:50:53PM +0200, Vitaly Kuznetsov wrote:
> >> Vivek Goyal writes:
> >>
> >> >
> >> > So if we are using a common structure "kvm_vcpu_pv_apf_data" to deliver
> >> > type1 and
On Wed, May 13, 2020 at 03:32:09PM +0200, Andrew Lunn wrote:
> On Wed, May 13, 2020 at 02:06:48PM +0200, Oleksij Rempel wrote:
> > The cable test seems to be support by all of currently support Atherso
> > PHYs, so add support for all of them. This patch was tested only on
> > AR9331 PHY with
> So, I think consistency of implementation is more important than fixing
> this; the current behaviour has been established for many years now.
Hi Russell, Doug
With netlink ethtool we have the possibility of adding a new API to
control this. And we can leave the IOCTL API alone, and the
On Wed, May 13, 2020 at 12:22 PM Christoph Hellwig wrote:
>
> On Wed, May 13, 2020 at 09:07:43AM +0200, Martijn Coenen wrote:
> > On Wed, May 13, 2020 at 4:30 AM Jens Axboe wrote:
> > > > Looks acceptable to me, but I'm getting a failure applying it to
> > > > for-5.8/drivers on this patch:
> >
On 5/13/20 3:54 PM, ansuels...@gmail.com wrote:
>> Hi Ansuel,
>>
>> On 5/1/20 1:06 AM, Ansuel Smith wrote:
>>> From: Sham Muthayyan
>>>
>>> Add tx term offset support to pcie qcom driver need in some revision of
>>> the ipq806x SoC.
>>> Ipq8064 have tx term offset set to 7.
>>> Ipq8064-v2
Hi Daniel
On Thu, 2020-05-07 at 13:06 +0200, Daniel Kiper wrote:
> > There is a function that verifies if platform is TXT capable
> > -grub_txt_verify_platform(), it only checks SMX and GETSEC features.
> > Although BIOS should enforce both VMX and VT-d enabled when enabling
> > TXT, I think that
I've pushed out a branch with the first three patches here:
git://git.infradead.org/users/hch/dma-mapping.git dma-sg_table-helper
Gitweb:
http://git.infradead.org/users/hch/dma-mapping.git/shortlog/refs/heads/dma-sg_table-helper
and merged it into the dma-mapping for-next tree. Unless
On 13/05/2020 10:43, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.4.41 release.
> There are 90 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On 13/05/2020 10:43, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.6.13 release.
> There are 118 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
On Wed, 13 May 2020 20:03:53 +0900
Tetsuo Handa wrote:
> I think that basically only oops (e.g. WARN()/BUG()/panic()) messages worth
> printing to consoles and the rest messages do not worth printing to consoles.
> Existing KERN_$LOGLEVEL is too rough-grained.
And this statement is exactly why
On 13/05/2020 10:44, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.19.123 release.
> There are 48 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses
CC dt
On Wed, May 13, 2020 at 1:52 PM Rodrigo Rolim Mendes de Alencar
<455.rodrigo.alen...@gmail.com> wrote:
> This patch provides support for displays like VGM128064B0W10,
> which requires a column offset of 2, i.e., its segments starts
> in SEG2 and ends in SEG129.
>
> Signed-off-by: Rodrigo
Luis Chamberlain writes:
> On Tue, May 12, 2020 at 12:40:55PM -0500, Eric W. Biederman wrote:
>> Luis Chamberlain writes:
>>
>> > On Tue, May 12, 2020 at 06:52:35AM -0500, Eric W. Biederman wrote:
>> >> Luis Chamberlain writes:
>> >>
>> >> > +static struct ctl_table fs_base_table[] = {
>> >>
On Wed, May 13, 2020 at 03:38:36PM +0200, Martijn Coenen wrote:
> sector_t is now always u64, so we don't need to check for truncation.
>
> Signed-off-by: Martijn Coenen
Looks good:
Reviewed-by: Christoph Hellwig
On Wed, May 13, 2020 at 2:57 PM Kalle Valo wrote:
>
> Arnd Bergmann writes:
>
> > On Wed, May 13, 2020 at 8:50 AM Kalle Valo wrote:
> >>
> >> Kalle Valo writes:
> >
> > At least if it fails reproducibly, it's probably not too hard to drill
> > down further. Some ideas:
> >
> > * I'd first try
On 2020/5/12 下午11:49, Qi Zheng wrote:
For version 1 to 3 of the device tree, this is the node full
path as a zero terminated string, starting with "/". The
following equation will not hold, since the node name has
been processed in the fdt_get_name().
*pathp == '/'
For version 16 and
From: John Mathew
Add new sections to enable addition of new documentation on
the scheduler. Existing documentation is moved under the related
new sections. The sections are
- overview
- sched-features
- arch-specific.rst
- sched-debugging.rst
Suggested-by: Lukas Bulwahn
Signed-off-by:
version 4:
-Added section on Capacity-Aware Scheduling
-Reworded CFS recently added features.
-Removed vruntime description from scheduler structs
-Added description of idle and stopper sched classses
version 3:
-Fix spelling, spacing and typo errors.
version 2:
- Remove :c:func: directive
From: John Mathew
Add documentation for introduction to
-context-switch
-x86 context-switch
-MIPS context switch
Suggested-by: Lukas Bulwahn
Co-developed-by: Mostafa Chamanara
Signed-off-by: Mostafa Chamanara
Co-developed-by: Oleg Tsymbal
Signed-off-by: Oleg Tsymbal
Signed-off-by: John
---
Documentation/scheduler/cfs-overview.rst | 113 ++--
Documentation/scheduler/sched-cas.rst | 74
.../scheduler/sched-data-structs.rst | 163 +-
Documentation/scheduler/sched-design-CFS.rst | 20 +++
From: John Mathew
Add documentation for
-scheduler overview
-scheduler state transtion
-CFS overview
-scheduler data structs
Add rst for scheduler APIs and modify sched/core.c
to add kernel-doc comments.
Suggested-by: Lukas Bulwahn
Co-developed-by: Mostafa Chamanara
Signed-off-by:
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
On Thu, May 7, 2020 at 9:55 AM Geert Uytterhoeven
wrote:
> From: Yoshihiro Kaneko
>
> Convert the Renesas Interrupt Controller (INTC) for external pins Device
> Tree binding documentation to json-schema.
>
> Signed-off-by: Yoshihiro Kaneko
> Co-developed-by: Geert Uytterhoeven
> Signed-off-by:
This patch adds a temperature sensor driver to the Sparx5 SoC.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
drivers/hwmon/Kconfig | 10 +++
drivers/hwmon/Makefile | 2 +-
drivers/hwmon/sparx5-temp.c | 154
3 files changed,
This add the DT binding specification for the Sparx5 temperature
sensor.
Reviewed-by: Alexandre Belloni
Signed-off-by: Lars Povlsen
---
.../bindings/hwmon/microchip,sparx5-temp.yaml | 39 +++
1 file changed, 39 insertions(+)
create mode 100644
This is an add-on series to the main SoC Sparx5 series
(Message-ID: <20200513125532.24585-1-lars.povl...@microchip.com>).
It is expected that the DT patches are to be taken directly by the arm-soc
maintainers.
Lars Povlsen (3):
dt-bindings: hwmon: Add Sparx5 temperature sensor
arm64: dts:
opal_xive_donate_page() will reference the newly allocated memory using
__pa(). Since kmemleak is unable to track the physical memory resulting
in false positives, silence those by using kmemleak_ignore().
unreferenced object 0xc000201b53e9 (size 65536):
comm "qemu-kvm", pid 124557, jiffies
kvmppc_pmd_alloc() and kvmppc_pte_alloc() allocate some memory but then
pud_populate() and pmd_populate() will use __pa() to reference the newly
allocated memory.
Since kmemleak is unable to track the physical memory resulting in false
positives, silence those by using kmemleak_ignore().
On Wed, May 13, 2020 at 02:34:40PM +0200, Oleksij Rempel wrote:
> Add initial cable testing support.
> This PHY needs only 100usec for this test and it is recommended to run it
> before the link is up. For now, provide at least ethtool support, so it
> can be tested by more developers.
>
> This
loop_set_status() calls loop_config_discard() to configure discard for
the loop device; however, the discard configuration depends on whether
the loop device uses encryption, and when we call it the encryption
configuration has not been updated yet. Move the call down so we apply
the correct
sector_t is now always u64, so we don't need to check for truncation.
Signed-off-by: Martijn Coenen
---
drivers/block/loop.c | 21 +++--
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index f1754262fc94..00de7fec0ed5
This allows userspace to completely setup a loop device with a single
ioctl, removing the in-between state where the device can be partially
configured - eg the loop device has a backing file associated with it,
but is reading from the wrong offset.
Besides removing the intermediate state,
LOOP_SET_STATUS(64) will actually allow some lo_flags to be modified; in
particular, LO_FLAGS_AUTOCLEAR can be set and cleared, whereas
LO_FLAGS_PARTSCAN can be set to request a partition scan. Make this
explicit by updating the UAPI to include the flags that can be
set/cleared using this ioctl.
This function was now only used by loop_set_capacity(). Just open code
the remaining code in the caller instead.
Reviewed-by: Christoph Hellwig
Signed-off-by: Martijn Coenen
---
drivers/block/loop.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git
801 - 900 of 1758 matches
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