Signed-off-by: Andra Paraschiv
---
Changelog
v2 -> v3
* Remove the GPL additional wording as SPDX-License-Identifier is already in
place.
v1 -> v2
* Update path to Makefile to match the drivers/virt/nitro_enclaves directory.
---
drivers/virt/Makefile| 2 ++
drivers/virt/nitro
Another resource that is being set for an enclave is memory. User space
memory regions, that need to be backed by contiguous memory regions,
are associated with the enclave.
One solution for allocating / reserving contiguous memory regions, that
is used for integration, is hugetlbfs. The user spac
flush_icache_user_range definition for xtensa is placed under
preprocessor condition that is not processed in noMMU configurations,
resulting in the following build errors:
fs/exec.c:1065:3: error: implicit declaration of function
‘flush_icache_user_range’
fs/binfmt_flat.c:857:2: error: impl
An enclave is associated with an fd that is returned after the enclave
creation logic is completed. This enclave fd is further used to setup
enclave resources. Once the enclave needs to be terminated, the enclave
fd is closed.
Add logic for enclave termination, that is mapped to the enclave fd
rel
Signed-off-by: Andra Paraschiv
---
Changelog
v2 -> v3
* Remove the GPL additional wording as SPDX-License-Identifier is already in
place.
v1 -> v2
* Update path to Kconfig to match the drivers/virt/nitro_enclaves directory.
* Update help in Kconfig.
---
drivers/virt/Kconfig|
Before setting the memory regions for the enclave, the enclave image
needs to be placed in memory. After the memory regions are set, this
memory cannot be used anymore by the VM, being carved out.
Add ioctl command logic to get the offset in enclave memory where to
place the enclave image. Then th
An enclave, before being started, has its resources set. One of its
resources is CPU.
Add ioctl command logic for enclave vCPU creation. Return as result a
file descriptor that is associated with the enclave vCPU.
Signed-off-by: Alexandru Vasile
Signed-off-by: Andra Paraschiv
---
Changelog
v2
Add ioctl command logic for enclave VM creation. It triggers a slot
allocation. The enclave resources will be associated with this slot and
it will be used as an identifier for triggering enclave run.
Return a file descriptor, namely enclave fd. This is further used by the
associated user space en
The Nitro Enclaves PCI device exposes a MMIO space that this driver
uses to submit command requests and to receive command replies e.g. for
enclave creation / termination or setting enclave resources.
Add logic for handling PCI device command requests based on the given
command type.
Register an
The Nitro Enclaves driver provides an ioctl interface to the user space
for enclave lifetime management e.g. enclave creation / termination and
setting enclave resources such as memory and CPU.
This ioctl interface is mapped to a Nitro Enclaves misc device.
Signed-off-by: Andra Paraschiv
---
Cha
In addition to the replies sent by the Nitro Enclaves PCI device in
response to command requests, out-of-band enclave events can happen e.g.
an enclave crashes. In this case, the Nitro Enclaves driver needs to be
aware of the event and notify the corresponding user space process that
abstracts the
The Nitro Enclaves (NE) driver communicates with a new PCI device, that
is exposed to a virtual machine (VM) and handles commands meant for
handling enclaves lifetime e.g. creation, termination, setting memory
regions. The communication with the PCI device is handled using a MMIO
space and MSI-X in
The Nitro Enclaves PCI device is used by the kernel driver as a means of
communication with the hypervisor on the host where the primary VM and
the enclaves run. It handles requests with regard to enclave lifetime.
Setup the PCI device driver and add support for MSI-X interrupts.
Signed-off-by: A
Nitro Enclaves (NE) is a new Amazon Elastic Compute Cloud (EC2) capability
that allows customers to carve out isolated compute environments within EC2
instances [1].
For example, an application that processes sensitive data and runs in a VM,
can be separated from other applications running in the
The Nitro Enclaves driver handles the enclave lifetime management. This
includes enclave creation, termination and setting up its resources such
as memory and CPU.
An enclave runs alongside the VM that spawned it. It is abstracted as a
process running in the VM that launched it. The process intera
The Nitro Enclaves driver keeps an internal info per each enclave.
This is needed to be able to manage enclave resources state, enclave
notifications and have a reference of the PCI device that handles
command requests for enclave lifetime management.
Signed-off-by: Alexandru-Catalin Vasile
Sign
Hi,
On 5/25/20 3:25 AM, Russell King - ARM Linux admin wrote:
On Sun, May 24, 2020 at 11:28:52PM -0500, Jeremy Linton wrote:
Hi,
On 5/24/20 9:44 AM, Andrew Lunn wrote:
+++ b/include/linux/phy.h
@@ -275,6 +275,11 @@ struct mii_bus {
int reset_delay_us;
/* RESET GPIO descriptor
> Yes, we know even for the NXP reference hardware, one of the phy's doesn't
> probe out correctly because it doesn't respond to the ieee defined
> registers. I think at this point, there really isn't anything we can do
> about that unless we involve the (ACPI) firmware in currently nonstandard
> b
On Mon, May 25, 2020 at 04:51:16PM -0500, Jeremy Linton wrote:
> Hi,
>
> On 5/25/20 5:06 AM, Russell King - ARM Linux admin wrote:
> > On Sun, May 24, 2020 at 10:34:13PM -0500, Jeremy Linton wrote:
> > > Hi,
> > >
> > > On 5/23/20 1:37 PM, Russell King - ARM Linux admin wrote:
> > > > On Fri, May
On Mon, 25 May 2020 11:31:27 -0700, Andrii Nakryiko wrote:
> On Sun, May 24, 2020 at 5:09 AM Akira Yokosawa wrote:
>>
>> On Fri, 22 May 2020 12:38:21 -0700, Andrii Nakryiko wrote:
>>> On 5/22/20 10:43 AM, Paul E. McKenney wrote:
On Fri, May 22, 2020 at 10:32:01AM -0400, Alan Stern wrote:
Hi all,
Commit
1fe411077207 ("Replace HTTP links with HTTPS ones: documentation")
is missing a Signed-off-by from its author.
--
Cheers,
Stephen Rothwell
pgpJrDTI9Knpg.pgp
Description: OpenPGP digital signature
These two functions share the same logic.
Signed-off-by: Wei Yang
---
include/linux/bitops.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 5b5609e81a84..80703ef27aee 100644
--- a/include/linux/bitops.h
+++ b/incl
Hi!
> >This is the multi color LED framework. This framework presents clustered
> >colored LEDs into an array and allows the user space to adjust the brightness
> >of the cluster using a single file write. The individual colored LEDs
> >intensities are controlled via a single file that is an ar
Hi,
On 5/25/20 4:07 PM, Russell King - ARM Linux admin wrote:
On Mon, May 25, 2020 at 04:02:13PM -0500, Jeremy Linton wrote:
So, I think you're going to have to add a work-around to ignore bit 0,
which brings up the question whether this is worth it or not.
It does ignore bit 0, it gets turne
On Mon, May 25, 2020 at 01:41:10PM -0700, Andrew Morton wrote:
>On Mon, 25 May 2020 18:32:16 +0300 Andy Shevchenko
> wrote:
>
>> On Mon, May 25, 2020 at 02:43:12PM +, Wei Yang wrote:
>> > On Mon, May 25, 2020 at 12:14:58PM +0300, Andy Shevchenko wrote:
>> > >On Sun, May 24, 2020 at 12:35:51PM
pr_warn("** If you see this message and you are not debugging**\n");
>pr_warn("** the kernel, report this immediately to your vendor!
> **\n");
>pr_warn("**
> **\n");
>pr_warn("** NOTICE NOTICE NOTICE NOTICE
On Fri, May 22, 2020 at 7:55 AM Adrian Reber wrote:
> This enables CRIU to checkpoint and restore a process as non-root.
>
> Over the last years CRIU upstream has been asked a couple of time if it
> is possible to checkpoint and restore a process as non-root. The answer
> usually was: 'almost'.
>
Hi,
On 5/25/20 5:06 AM, Russell King - ARM Linux admin wrote:
On Sun, May 24, 2020 at 10:34:13PM -0500, Jeremy Linton wrote:
Hi,
On 5/23/20 1:37 PM, Russell King - ARM Linux admin wrote:
On Fri, May 22, 2020 at 04:30:52PM -0500, Jeremy Linton wrote:
Until this point, we have been sanitizing
The struct hyperv_ir_domain_ops is not modified and can be made const to
allow the compiler to put it in read-only memory.
Before:
textdata bss dec hex filename
29161180112052161460 drivers/iommu/hyperv-iommu.o
After:
textdata bss dec hex f
Constify some structs with function pointers to allow the compiler to
put them in read-only memory. There is not dependency between the
patches.
Rikard Falkeborn (2):
iommu/hyper-v: Constify hyperv_ir_domain_ops
iommu/sun50i: Constify sun50i_iommu_ops
drivers/iommu/hyperv-iommu.c | 2 +-
dri
The struct sun50i_iommu_ops is not modified and can be made const to
allow the compiler to put it in read-only memory.
Before:
textdata bss dec hex filename
143582501 64 16923421b drivers/iommu/sun50i-iommu.o
After:
textdata bss dec hex filen
From: "Joel Fernandes (Google)"
kfree_rcu()'s debug_objects logic uses the address of the object's
embedded rcu_head to queue/unqueue. Instead of this, make use of the
object's address itself as preparation for future headless kfree_rcu()
support.
Reviewed-by: Uladzislau Rezki
Signed-off-by: Ul
From: Sebastian Andrzej Siewior
The per-CPU variable is initialized at runtime in
kfree_rcu_batch_init(). This function is invoked before
'rcu_scheduler_active' is set to 'RCU_SCHEDULER_RUNNING'.
After the initialisation, '->initialized' is to true.
The raw_spin_lock is only acquired if '->initi
It is possible that one of the channels cannot be detached
because its free channel is busy and previously queued data
has not been processed yet. On the other hand, another
channel can be successfully detached causing the monitor
work to stop.
Prevent that by rescheduling the monitor work if ther
Rename kvfree_rcu() function to the kvfree_rcu_local() one.
The purpose is to prevent a conflict of two same function
declarations. The kvfree_rcu() will be globally visible
what would lead to a build error. No functional change.
Cc: linux...@kvack.org
Cc: r...@vger.kernel.org
Cc: Andrew Morton
S
In order to reduce the dynamic need for pages in kfree_rcu(),
pre-allocate a configurable number of pages per CPU and link
them in a list. When kfree_rcu() reclaims objects, the object's
container page is cached into a list instead of being released
to the low-level page allocator.
Such an approac
To do so, we use an array of kvfree_rcu_bulk_data structures.
It consists of two elements:
- index number 0 corresponds to slab pointers.
- index number 1 corresponds to vmalloc pointers.
Keeping vmalloc pointers separated from slab pointers makes
it possible to invoke the right freeing API for
Update the kvfree_call_rcu() function with head-less support.
This allows RCU to reclaim objects without an embedded rcu_head.
tree-RCU:
We introduce two chains of arrays to store SLAB-backed and vmalloc
pointers, each. Storage in either of these arrays does not require
embedding an rcu_head with
We can simplify KFREE_BULK_MAX_ENTR macro and get rid of
magic numbers which were used to make the structure to be
exactly one page.
Suggested-by: Boqun Feng
Reviewed-by: Joel Fernandes (Google)
Signed-off-by: Uladzislau Rezki (Sony)
Signed-off-by: Joel Fernandes (Google)
---
kernel/rcu/tree.
The following changes are introduced:
1. Rename rcu_invoke_kfree_callback() to rcu_invoke_kvfree_callback(),
as well as the associated trace events, so the rcu_kfree_callback(),
becomes rcu_kvfree_callback(). The reason is to be aligned with kvfree()
notation.
2. Rename __is_kfree_rcu_offset to _
Introduce helpers to lock and unlock per-cpu "kfree_rcu_cpu"
structures. That will make kfree_call_rcu() more readable
and prevent programming errors.
Reviewed-by: Joel Fernandes (Google)
Signed-off-by: Uladzislau Rezki (Sony)
---
kernel/rcu/tree.c | 31 +++
1 file c
This is a v2 of the https://lkml.org/lkml/2020/4/28/1626 series.
Please have look at v1 to find out more about motivation and details.
It is based on the latest dev.2020.05.17a Paul's branch.
Short changelog (v1 -> v2):
- Combine some patches, thus reduce the overall number;
- Switch one l
Replace kfree() with kvfree() in rcu_reclaim_tiny().
This makes it possible to release either SLAB or vmalloc
objects after a GP.
Reviewed-by: Joel Fernandes (Google)
Signed-off-by: Uladzislau Rezki (Sony)
---
kernel/rcu/tiny.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Introduce four new test cases for testing the kvfree_rcu()
interface. Two of them belong to single argument functionality
and another two for 2-argument functionality.
The aim is to stress and check how kvfree_rcu() behaves under
different load and memory conditions and analyze its performance
thr
Make kvfree_rcu() capable of freeing objects that will not
embed an rcu_head within it. This saves storage overhead in
such objects. Reclaiming headless objects this way requires
only a single argument (pointer to the object).
After this patch, there are two ways to use kvfree_rcu():
a) kvfree_rc
kvmalloc() can allocate two types of objects: SLAB backed
and vmalloc backed. How it behaves depends on requested
object's size and memory pressure.
Add a kvfree_rcu() interface that can free memory allocated
via kvmalloc(). It is a simple alias to kfree_rcu() which
can now handle either type of o
The assembly and disassembly of data to be sent to or received from a
device invoke functions (regmap_format_XXX() and regmap_parse_XXX())
that extract or insert data items into a buffer. In some cases these
functions are invoked with buffer pointers with odd addresses but try
to directly assign fr
From: "Joel Fernandes (Google)"
To keep the kfree_rcu() code working in purely atomic sections on RT,
such as non-threaded IRQ handlers and raw spinlock sections, avoid
calling into the page allocator which uses sleeping locks on RT.
In fact, even if the caller is preemptible, the kfree_rcu() c
From: "Joel Fernandes (Google)"
On PREEMPT_RT kernels, the krcp spinlock gets converted to an rt-mutex
and causes kfree_rcu() callers to sleep. This makes it unusable for
callers in purely atomic sections such as non-threaded IRQ handlers and
raw spinlock sections. Fix it by converting the spinlo
On Mon, 25 May 2020 10:52:39 +0800 Bibo Mao wrote:
> Here add pte_sw_mkyoung function to make page readable on MIPS
> platform during page fault handling. This patch improves page
> fault latency about 10% on my MIPS machine with lmbench
> lat_pagefault case.
>
> It is noop function on other arc
On Mon, 25 May 2020 10:52:38 +0800 Bibo Mao wrote:
> If two threads concurrently fault at the same page, the thread that
> won the race updates the PTE and its local TLB. For now, the other
> thread gives up, simply does nothing, and continues.
>
> It could happen that this second thread trigger
On Mon, 25 May 2020 10:52:37 +0800 Bibo Mao wrote:
> It is not necessary to flush tlb page on all CPUs if suitable PTE
> entry exists already during page fault handling, just updating
> TLB is fine.
>
> Here redefine flush_tlb_fix_spurious_fault as empty on MIPS system.
>
> ...
>
> --- a/arch/m
ITE_ONCE(link->status, DL_STATE_ACTIVE);
> }
>
> My goal is to figure out the order in which the device links between
> the supplier and consumers devices are created and how that's changing
> the flag and status. Then I can come up with a fix.
Here we go (ho
Hi Vinicius,
On Thu, 21 May 2020 at 20:33, Vinicius Costa Gomes
wrote:
>
> Murali Karicheri writes:
>
> > This RFC series add support for Parallel Redundancy Protocol (PRP)
> > as defined in IEC-62439-3 in the kernel networking subsystem. PRP
> > Uses a Redundancy Control Trailer (RCT) the forma
On Mon, May 25, 2020 at 12:41:32PM +0100, Mark Brown wrote:
> On Sat, May 23, 2020 at 11:34:10AM +0300, Serge Semin wrote:
> > On Fri, May 22, 2020 at 04:22:41PM +0100, Mark Brown wrote:
>
> > > Right, that definitely needs to be fixed then - 8MHz is indeed a totally
> > > normal clock rate for SP
On Fri, May 22, 2020 at 07:19:55AM -0700, Guenter Roeck wrote:
> On Sun, May 10, 2020 at 01:32:11PM +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides an embedded process, voltage and temperature
> > sensor to monitor an internal SoC environment (chip temperature, supply
> > voltage and process m
On Mon, May 25, 2020 at 12:05 PM Michael Walle wrote:
>
> Am 2020-05-25 20:39, schrieb Saravana Kannan:
> > On Mon, May 25, 2020 at 4:31 AM Michael Walle wrote:
> >>
> >> Am 2020-05-23 00:47, schrieb Michael Walle:
> >> > Am 2020-05-23 00:21, schrieb Saravana Kannan:
> >> >> On Fri, May 22, 2020
On 25/05/20 10:43 pm, Peter Rosin wrote:
> It is not valid to cache/short out selection of the mux.
>
> mux_control_select() only locks the mux until mux_control_deselect()
> is called. mux_control_deselect() may put the mux in some low power
> state or some other user of the mux might select it f
Add Telit LE910C1-EUX compositions:
0x1031: tty, tty, tty, rmnet
0x1033: tty, tty, tty, ecm
Signed-off-by: Daniele Palmas
---
Hi Johan,
following the lsusb output:
Bus 003 Device 007: ID 1bc7:1031 Telit Wireless Solutions
Device Descriptor:
bLength18
bDescriptorType
Hi all,
The INTEL_CPUFREQ_TRANSITION_DELAY_HWP = 2
test results from this e-mail were incorrect.
The test and graphs are being re-done.
On 2020.05.25 08:30 Doug smythies wrote:
>
> Legend - intel_pstate - powersave graph [2].
>
> What? Why is there such a graph, unrelated to this patch?
>
On 22/05/2020 10:11, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:44AM +0300, Andra Paraschiv wrote:
Signed-off-by: Alexandru Vasile
Signed-off-by: Andra Paraschiv
No changelog?
I included the changelog in v3.
---
samples/nitro_enclaves/.gitignore | 2 +
samples/nitro
On Mon, May 25, 2020 at 04:02:13PM -0500, Jeremy Linton wrote:
> > So, I think you're going to have to add a work-around to ignore bit 0,
> > which brings up the question whether this is worth it or not.
>
> It does ignore bit 0, it gets turned into the C22 regs flag, and
> cleared/ignored in the
On 22/05/2020 10:09, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:45AM +0300, Andra Paraschiv wrote:
Signed-off-by: Andra Paraschiv
No changelog?
I included the changelog in v3.
Thanks,
Andra
Amazon Development Center (Romania) S.R.L. registered office: 27A Sf. Lazar
Street, UBC5, flo
On 22/05/2020 10:09, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:43AM +0300, Andra Paraschiv wrote:
Signed-off-by: Andra Paraschiv
Changelog is needed
I included it in v3.
Thanks,
Andra
Amazon Development Center (Romania) S.R.L. registered office: 27A Sf. Lazar
Street, UBC5, floor 2
Hi,
On 5/25/20 4:45 AM, Russell King - ARM Linux admin wrote:
On Sun, May 24, 2020 at 09:46:55PM -0500, Jeremy Linton wrote:
Hi,
Thanks for taking a look at this.
On 5/23/20 1:20 PM, Russell King - ARM Linux admin wrote:
On Fri, May 22, 2020 at 04:30:49PM -0500, Jeremy Linton wrote:
C45 dev
On 22/05/2020 10:09, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:42AM +0300, Andra Paraschiv wrote:
Signed-off-by: Andra Paraschiv
changelog is needed.
I included it in v3.
Thanks,
Andra
Amazon Development Center (Romania) S.R.L. registered office: 27A Sf. Lazar
Street, UBC5, floor
On 22/05/2020 10:08, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:44AM +0300, Andra Paraschiv wrote:
Signed-off-by: Alexandru Vasile
Signed-off-by: Andra Paraschiv
I know I don't take commits with no changelog text :(
Included in v3 the changelog for each patch in the series, in addition
"Rafael J. Wysocki" writes:
> On Mon, May 25, 2020 at 3:39 AM Francisco Jerez
> wrote:
>>
>> "Rafael J. Wysocki" writes:
>>
>> > From: Rafael J. Wysocki
>> >
>> > Allow intel_pstate to work in the passive mode with HWP enabled and
>> > make it translate the target frequency supplied by the cpu
On Fri, 22 May 2020 22:46:07 +0200 Johannes Berg wrote:
> > The irony is you have a problem with a networking device and all the
> > devices your initial set touched are networking. Two of the drivers
> > you touched either have or will soon have devlink health reporters
> > implemented.
>
> Li
On 2020-05-25 09:56, Jason Gunthorpe wrote:
On Mon, May 25, 2020 at 11:11:42AM -0400, Peter Xu wrote:
On Mon, May 25, 2020 at 11:46:51AM -0300, Jason Gunthorpe wrote:
On Mon, May 25, 2020 at 10:28:06AM -0400, Peter Xu wrote:
On Mon, May 25, 2020 at 09:26:07AM -0300, Jason Gunthorpe wrote:
On
On 22/05/2020 10:08, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:36AM +0300, Andra Paraschiv wrote:
Add ioctl command logic for enclave VM creation. It triggers a slot
allocation. The enclave resources will be associated with this slot and
it will be used as an identifier for triggering encla
On Mon, May 25, 2020 at 10:49:06PM +0200, Jonas Falkevik wrote:
> On Mon, May 25, 2020 at 6:10 PM Xin Long wrote:
> >
> > On Mon, May 25, 2020 at 9:10 PM Marcelo Ricardo Leitner
> > wrote:
> > >
> > > On Mon, May 25, 2020 at 04:42:16PM +0800, Xin Long wrote:
> > > > On Sat, May 23, 2020 at 8:04 P
On 22/05/2020 10:07, Greg KH wrote:
On Fri, May 22, 2020 at 09:29:35AM +0300, Andra Paraschiv wrote:
+static char *ne_cpus;
+module_param(ne_cpus, charp, 0644);
+MODULE_PARM_DESC(ne_cpus, " - CPU pool used for Nitro Enclaves");
This is not the 1990's, don't use module parameters if you can he
On Mon, May 25, 2020 at 09:52:54PM +0300, Vladimir Oltean wrote:
> Hi Josh,
>
> On Mon, 25 May 2020 at 20:28, Josh Triplett wrote:
> >
> > On Mon, May 25, 2020 at 04:02:38PM +0300, Vladimir Oltean wrote:
> > > On NXP T1040, the UART is typically detected as 16550A_FSL64. After said
> > > patch, i
On Mon, May 25, 2020 at 6:10 PM Xin Long wrote:
>
> On Mon, May 25, 2020 at 9:10 PM Marcelo Ricardo Leitner
> wrote:
> >
> > On Mon, May 25, 2020 at 04:42:16PM +0800, Xin Long wrote:
> > > On Sat, May 23, 2020 at 8:04 PM Jonas Falkevik
> > > wrote:
> > > >
> > > > On Tue, May 19, 2020 at 10:42
ufs_qcom_dump_dbg_regs() uses usleep_range, a sleeping function, but can
be called from atomic context in the following flow:
ufshcd_intr -> ufshcd_sl_intr -> ufshcd_check_errors ->
ufshcd_print_host_regs -> ufshcd_vops_dbg_register_dump ->
ufs_qcom_dump_dbg_regs
This causes a boot crash on the L
On Mon, 25 May 2020 18:32:16 +0300 Andy Shevchenko
wrote:
> On Mon, May 25, 2020 at 02:43:12PM +, Wei Yang wrote:
> > On Mon, May 25, 2020 at 12:14:58PM +0300, Andy Shevchenko wrote:
> > >On Sun, May 24, 2020 at 12:35:51PM +, Wei Yang wrote:
> > >> These two cases could be unified into o
On Mon, May 25, 2020 at 11:00:03AM -, tip-bot2 for Tony Luck wrote:
> The following commit has been merged into the ras/core branch of tip:
>
> Commit-ID: 3cb1ada80fe29e2fa022b5f20370b65718e0a744
> Gitweb:
> https://git.kernel.org/tip/3cb1ada80fe29e2fa022b5f20370b65718e0a744
> Auth
Change it to inline function to make callers use the proper argument.
And no need for it to be macro per Andrew's comment [1].
[1]
https://lore.kernel.org/lkml/20200518221235.1fa32c38e5766113f78e3...@linux-foundation.org/
Signed-off-by: Guoqing Jiang
---
include/linux/mm_types.h | 6 +-
1
On Mon, May 25, 2020 at 10:07 PM Olivier Sobrie
wrote:
>
> Silex insight BA431 is an IP designed to generate random numbers that
> can be integrated in various FPGA.
> This driver adds support for it through the hwrng interface.
>
> This driver is used in Silex Insight Viper OEM boards.
>
> Signed
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If both the HTTP and
On Mon 2020-05-25 15:57:28, Andrew Lunn wrote:
> > > standardizing on rx-delay-ps and tx-delay-ps would make sense since that
> > > is the lowest resolution and the property would be correctly named with
> > > an unit in the name.
> >
> > Seems like similar patch is already being reviewed from Dan
Silex insight BA431 is an IP designed to generate random numbers that
can be integrated in various FPGA.
This driver adds support for it through the hwrng interface.
This driver is used in Silex Insight Viper OEM boards.
Signed-off-by: Olivier Sobrie
Signed-off-by: Waleed Ziad
---
drivers/char
Silex Insight is a microelectronic company whose headquarter is located
in Belgium.
Web site of the company: https://www.silexinsight.com/
Signed-off-by: Olivier Sobrie
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
This patch documents the device tree bindings of the BA431 hardware
random number generator.
This IP is for instance present in the Viper OEM boards sold by Silex
Insight.
Signed-off-by: Olivier Sobrie
---
.../bindings/rng/silex-insight,ba431-rng.yaml | 36 +++
1 file changed, 3
Hello all,
This set of patches aims at introducing a linux hwrng driver for the
Silex Insight BA431 IP which is available for various FPGA.
This hardware is for instance present in Silex Insight Viper OEM boards.
The two first patches are documenting the device tree bindings.
The last one contain
On 5/25/20 1:29 AM, Pavel Begunkov wrote:
> On 23/05/2020 21:57, Jens Axboe wrote:
>> If the file is flagged with FMODE_BUF_RASYNC, then we don't have to punt
>> the buffered read to an io-wq worker. Instead we can rely on page
>> unlocking callbacks to support retry based async IO. This is a lot m
The mapping operations of the Tegra SMMU driver are subjected to a race
condition issues because SMMU Address Space isn't allocated and freed
atomically, while it should be. This patch makes the mapping operations
atomic, it fixes an accidentally released Host1x Address Space problem
which happens
On 5/22/20 7:06 AM, Dan Carpenter wrote:
> On Mon, May 18, 2020 at 08:45:31PM -0400, Mitchell Tasman wrote:
>> In several cases where a pointer marked as __user is
>> (intentionally) assigned or passed to a non-marked target,
>> cast to the target pointer type with a __force directive
>> to quiet w
On Mon, 25 May 2020 20:01:45 +0200
"Alexander A. Klimov" wrote:
> > But this does not seem to do harm at this point, so I have gone ahead and
> > applied it.
> What does this mean? Is there a kernel.org repo/branch with my patch?
That means it's in the docs-next tree.
jon
On Fri, 22 May 2020 08:37:41 -0400
Steven Rostedt wrote:
> On Mon, 18 May 2020 13:29:24 -0500
> Tom Zanussi wrote:
>
> > The in-kernel trace event API should have its own section, and the
> > duplicate section numbers need fixing as well.
> >
> > Signed-off-by: Tom Zanussi
>
> Acked-by: St
The Hurd gained[0] support for moving the translator and author
fields out of the inode and into the "gnu.*" xattr namespace.
In anticipation of that, an xattr INDEX was reserved[1]. The Hurd has
now been brought into compliance[2] with that.
This patch adds support for reading and writing such
On Mon, Apr 20, 2020 at 04:11:38PM +0800, Xu Yilun wrote:
> Some DFL FPGA PCIe cards (e.g. Intel FPGA Programmable Acceleration
> Card) support MSI-X based interrupts. This patch allows PCIe driver
> to prepare and pass interrupt resources to DFL via enumeration API.
> These interrupt resources cou
On Mon, Apr 20, 2020 at 04:11:40PM +0800, Xu Yilun wrote:
> Error reporting interrupt is very useful to notify users that some
> errors are detected by the hardware. Once users are notified, they
> could query hardware logged error states, no need to continuously
> poll on these states.
>
> This p
On Mon, Apr 20, 2020 at 04:11:42PM +0800, Xu Yilun wrote:
> AFU (Accelerated Function Unit) is dynamic region of the DFL based FPGA,
> and always defined by users. Some DFL based FPGA cards allow users to
> implement their own interrupts in AFU. In order to support this,
> hardware implements a new
On Mon, Apr 20, 2020 at 04:11:43PM +0800, Xu Yilun wrote:
> This patch adds introductions of interrupt related interfaces for FME
> error reporting, port error reporting and AFU user interrupts features.
>
> Signed-off-by: Luwei Kang
> Signed-off-by: Wu Hao
> Signed-off-by: Xu Yilun
> Acked-by:
On Mon, Apr 20, 2020 at 04:11:37PM +0800, Xu Yilun wrote:
> DFL based FPGA devices could support interrupts for different purposes,
> but current DFL framework only supports feature device enumeration with
> given MMIO resources information via common DFL headers. This patch
> introduces one new AP
On Mon, Apr 20, 2020 at 04:11:39PM +0800, Xu Yilun wrote:
> FPGA user applications may be interested in interrupts generated by
> DFL features. For example, users can implement their own FPGA
> logics with interrupts enabled in AFU (Accelerated Function Unit,
> dynamic region of DFL based FPGA). So
On Mon, Apr 20, 2020 at 04:11:41PM +0800, Xu Yilun wrote:
> Error reporting interrupt is very useful to notify users that some
> errors are detected by the hardware. Once users are notified, they
> could query hardware logged error states, no need to continuously
> poll on these states.
>
> This p
25.05.2020 15:20, Thierry Reding пишет:
...
> Do we have a good way to find out how bad exactly the contention would
> be when using a mutex?
I'm now having a second thought about it. We don't need to care about
that scenario at all because it's a software-design defect of the
upstream Host1x driv
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