Min compiler version has been raised, so that's ok now.
Signed-off-by: Michael S. Tsirkin
---
include/linux/virtio_config.h | 163 --
1 file changed, 77 insertions(+), 86 deletions(-)
diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h
We normally expect vdpa to use the modern interface.
However for consistency, let's use same APIs as vhost
for legacy guests.
Signed-off-by: Michael S. Tsirkin
---
drivers/virtio/virtio_vdpa.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git
Some legacy guests just assume features are 0 after reset.
We detect that config space is accessed before features are
set and set features to 0 automatically.
Note: some legacy guests might not even access config space, if this is
reported in the field we might need to catch a kick to handle
For new helpers handling legacy features to be effective,
vhost needs to invoke them. Tie them in.
Signed-off-by: Michael S. Tsirkin
---
drivers/vhost/vdpa.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/vhost/vdpa.c b/drivers/vhost/vdpa.c
index
mlxbf-tmfifo accesses config space using native types -
which works for it since the legacy virtio native types.
This will break if it ever needs to support modern virtio,
so with new tags previously introduced for virtio net config,
sparse now warns for this in drivers.
Since this is a legacy
Tag config space fields as having virtio endian-ness.
Signed-off-by: Michael S. Tsirkin
---
drivers/scsi/virtio_scsi.c | 4 ++--
include/uapi/linux/virtio_scsi.h | 20 ++--
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/scsi/virtio_scsi.c
Transitional devices should all use __virtioXX types.
Modern ones should use __leXX.
_uXX type would be a bug.
Let's prevent that.
Signed-off-by: Michael S. Tsirkin
---
include/linux/virtio_config.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
Since gpu is a modern-only device,
tag config space fields as having little endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_gpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/uapi/linux/virtio_gpu.h
Since crypto is a modern-only device,
tag config space fields as having little endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_crypto.h | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git
Since fs is a modern-only device,
tag config space fields as having little endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_fs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/uapi/linux/virtio_fs.h b/include/uapi/linux/virtio_fs.h
index
Since this is a modern-only device,
tag config space fields as having little endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_iommu.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/uapi/linux/virtio_iommu.h
Since this is a modern-only device,
tag config space fields as having little endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_input.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/uapi/linux/virtio_input.h
Since this is a modern-only device,
tag config space fields as having little endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_pmem.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/virtio_pmem.h
Currently all config space fields are of the type __uXX.
This confuses people and some drivers (notably vdpa)
access them using CPU endian-ness - which only
works well for legacy or LE platforms.
Update virtio_cread/virtio_cwrite macros to allow __virtioXX
and __leXX field types. Follow-up
Since this is a modern-only device,
tag config space fields as having little endian-ness.
TODO: check other uses of __virtioXX types in this header,
should probably be __leXX.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_mem.h | 14 +++---
1 file changed, 7
Tag config space fields as having virtio endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_net.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/uapi/linux/virtio_net.h b/include/uapi/linux/virtio_net.h
index
virtio_store_mb was built with split ring in mind so it accepts
__virtio16 arguments. Packed ring uses __le16 values, so sparse
complains. It's just a store with some barriers so let's convert it to
a macro, we don't loose too much type safety by doing that.
Signed-off-by: Michael S. Tsirkin
Tag config space fields as having little endian-ness.
Note that balloon is special: LE even when using
the legacy interface.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_balloon.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
balloon uses virtio32_to_cpu instead of cpu_to_virtio32
to convert a native endian number to virtio.
No practical difference but makes sparse warn.
Fix it up.
Signed-off-by: Michael S. Tsirkin
---
drivers/virtio/virtio_balloon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Tag config space fields as having virtio endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_blk.h | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/uapi/linux/virtio_blk.h b/include/uapi/linux/virtio_blk.h
index
Tag config space fields as having virtio endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_console.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/uapi/linux/virtio_console.h
b/include/uapi/linux/virtio_console.h
index
Tag config space fields as having virtio endian-ness.
Signed-off-by: Michael S. Tsirkin
---
include/uapi/linux/virtio_9p.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/uapi/linux/virtio_9p.h b/include/uapi/linux/virtio_9p.h
index 277c4ad44e84..441047432258
Config space endian-ness is currently a mess: fields are
not tagged with the correct endian-ness so it's easy
to make mistakes like instanciating config space in
native endian-ness.
The following patches adding sparse tagging are currently in my tree.
Lightly tested.
As a follow-up, I plan to
On Mon, 3 Aug 2020 16:14:42 +0200 Jiri Pirko wrote:
> >devlink dev reload [ net-ns-respawn { PID | NAME | ID } ] [ driver-param-init
> >] [ fw-activate [ --live] ]
>
> Jakub, why do you prefer to have another extra level-specific option
> "live"? I think it is clear to have it as a separate
On Mon, Aug 3, 2020 at 1:48 PM Linus Torvalds
wrote:
>
> I've pushed out my merge of this thing [..]
It seems I'm not the only one unhappy with the pull request.
For some reason I also don't see pr-tracker-bot being all happy and
excited about it. I wonder why.
Linus
Quoting Julia Lawall (2020-08-01 01:53:42)
> The function __clk_get_flags has not been used since the April 2019
> commit a348f05361c9 ("ARM: omap2+: hwmod: drop CLK_IS_BASIC
> flag usage"). Other uses were removed in June 2015, eg by
> commit 98d8a60eccee ("clk: Convert __clk_get_flags() to
>
Quoting Geert Uytterhoeven (2020-08-03 01:48:35)
> CONFIG_IOMEM does not exist. The correct symbol to depend on is
> CONFIG_HAS_IOMEM.
>
> Fixes: 1e7468bd9d30a21e ("clk: Specify IOMEM dependency for HSDK pll driver")
> Signed-off-by: Geert Uytterhoeven
> ---
Applied to clk-next
On Mon 2020-08-03 19:42:17, Andy Shevchenko wrote:
> On Mon, Aug 3, 2020 at 5:51 PM Eddie James wrote:
> >
> > IBM created an implementation of the PCA9552 on a PIC16F
> > microcontroller. The I2C device addresses are different from the
> > hardware PCA9552, so add a new compatible string and
On 03.08.20 13:37, Vitaly Kuznetsov wrote:
Alexander Graf writes:
It's not desireable to have all MSRs always handled by KVM kernel space. Some
MSRs would be useful to handle in user space to either emulate behavior (like
uCode updates) or differentiate whether they are valid based on the
On Tue, Jul 28, 2020 at 09:05:29AM +0300, Eli Cohen wrote:
> Hi Michael,
> please note that this series depends on mlx5 core device driver patches
> in mlx5-next branch in
> git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git.
> git pull
On Sun, Aug 2, 2020 at 2:41 PM Jens Axboe wrote:
>
> Lots of cleanups in here, hardening the code and/or making it easier to
> read and fixing buts, but a core feature/change too adding support for
> real async buffered reads. With the latter in place, we just need
> buffered write async support
On 02/08/2020 16:39, Jia-Ju Bai wrote:
> To fix this problem, "req->op" is assigned to a local variable, and then
> the driver accesses this variable instead of "req->op".
>
> Signed-off-by: Jia-Ju Bai
Not sure how necessary this is (or even if anyone's still usingSiena
SR-IOV, since it needed a
On 7/24/2020 9:09 AM, Jane Chu wrote:
commit 7d988097c546 ("acpi/nfit, libnvdimm/security: Add security DSM overwrite
support")
adds a sysfs_notify_dirent() to wake up userspace poll thread when the
"overwrite"
operation has completed. But the notification is issued before the internal
dimm
On 7/24/2020 9:09 AM, Jane Chu wrote:
Since
commit d78c620a2e82 ("libnvdimm/security: Introduce a 'frozen' attribute"),
when issue
# ndctl sanitize-dimm nmem0 --overwrite
then immediately check the 'security' attribute,
# cat
On 8/3/20 1:29 PM, Stephen Smalley wrote:
On 8/3/20 4:00 PM, Stephen Smalley wrote:
On Mon, Aug 3, 2020 at 12:14 PM Lakshmi Ramasubramanian
wrote:
On 8/3/20 8:11 AM, Stephen Smalley wrote:
Possibly I'm missing something but with these patches applied on top of
next-integrity, and the
Quoting Sai Prakash Ranjan (2020-07-28 22:13:10)
> etm4_count keeps track of number of ETMv4 registered and on some systems,
> a race is observed on etm4_count variable which can lead to multiple calls
> to cpuhp_setup_state_nocalls_cpuslocked(). This function internally calls
>
The pull request you sent on Sun, 2 Aug 2020 21:17:21 +0200 (CEST):
> git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/fixes
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/99f6cf61f175c1239ed8e86d4a1757c380da52d1
Thank you!
--
Deet-doot-dot, I am a
On Wed, Jul 29, 2020 at 08:54:52AM +0300, Eli Cohen wrote:
> On Tue, Jul 28, 2020 at 02:53:34PM +0800, Jason Wang wrote:
> >
> > Just notice Michael's vhost branch can not compile due to this commit:
> >
> > commit fee8fe6bd8ccacd27e963b71b4f943be3721779e
> > Author: Michael S. Tsirkin
> >
Hi Greg,
On Mon, Aug 3, 2020 at 7:35 PM Greg Kroah-Hartman
wrote:
> On Mon, Aug 03, 2020 at 08:58:20AM -0700, Guenter Roeck wrote:
> > On Mon, Aug 03, 2020 at 02:17:38PM +0200, Greg Kroah-Hartman wrote:
> > > This is the start of the stable review cycle for the 5.7.13 release.
> > > There
> >
On 8/3/20 4:00 PM, Stephen Smalley wrote:
On Mon, Aug 3, 2020 at 12:14 PM Lakshmi Ramasubramanian
wrote:
On 8/3/20 8:11 AM, Stephen Smalley wrote:
Possibly I'm missing something but with these patches applied on top of
next-integrity, and the following lines added to /etc/ima/ima-policy:
On Mon, 3 Aug 2020 20:34:48 +0200 p...@cmp.felk.cvut.cz wrote:
> From: Pavel Pisa
>
> This driver adds support for the CTU CAN FD open-source IP core.
> More documentation and core sources at project page
> (https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core).
> The core integration to Xilinx
On Mon, 3 Aug 2020, Nick Desaulniers wrote:
> On Sat, Aug 1, 2020 at 12:23 PM Lukas Bulwahn wrote:
> >
> > Hi Nathan, Hi Nick,
> >
> > I have been busy with other topics around the kernel and static analysis;
> > but then, I read clang and static analysis in my mailbox in this patch.
> >
> >
Atomic transfers are required to properly power off a machine through
an I2C controlled PMIC, such as the Actions Semi ATC260x series.
System shutdown may happen with interrupts being disabled and, as a
consequence, the kernel may hang if the driver does not support atomic
transfers.
This
Linus,
Please pull the latest ras/core git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git ras-core-2020-08-03
# HEAD: bb2de0adca217a114ce023489426e24152e4bfcf x86/mce, EDAC/mce_amd:
Print PPIN in machine check records
Boris is on vacation and he asked us to send
Please pull the exec-linus branch from the git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace.git
exec-linus
HEAD: 7fce69dff8db30cb93aace0bbebda09972027af7 Implement kernel_execve
During the development of v5.7 I ran into bugs and quality of
implementation
On Thu, 9 Jul 2020, Miquel Raynal wrote:
> Add support for Silvaco I3C dual-role IP. The master role is supported
> in SDR mode only. I2C transfers have not been tested but are shared
> because they are so close to the I3C transfers in terms of registers
> configuration.
>
> Signed-off-by:
On Mon, Aug 03, 2020 at 12:05:06PM -0700, Andi Kleen wrote:
> > However, the history of their being together comes from
> >
> > 9bebe9e5b0f3 ("kbuild: Fix .text.unlikely placement")
> >
> > which seems to indicate there was some problem with having them separated
> > out,
> > although I don't
On Mon, Aug 03, 2020 at 09:27:36PM +0200, Thomas Gleixner wrote:
> Heiko Carstens writes:
>
> > On Mon, Aug 03, 2020 at 06:05:24PM +0200, Thomas Gleixner wrote:
> >> +/**
> >> + * vdso_update_begin - Start of a VDSO update section
> >> + *
> >> + * Allows architecture code to safely update the
On Mon, Aug 03, 2020 at 12:52:40PM -0700, Joe Perches wrote:
> On Mon, 2020-08-03 at 21:41 +0200, Sam Ravnborg wrote:
> > On Tue, Jul 07, 2020 at 04:05:39PM -0500, Gustavo A. R. Silva wrote:
> > > Replace the existing /* fall through */ comments and its variants with
> > > the new pseudo-keyword
From: Jiafei Pan
The driver calls napi_schedule_irqoff() from a context where, in RT,
hardirqs are not disabled, since the IRQ handler is force-threaded.
In the call path of this function, __raise_softirq_irqoff() is modifying
its per-CPU mask of pending softirqs that must be processed, using
From: Jiafei Pan
The driver calls napi_schedule_irqoff() from a context where, in RT,
hardirqs are not disabled, since the IRQ handler is force-threaded.
In the call path of this function, __raise_softirq_irqoff() is modifying
its per-CPU mask of pending softirqs that must be processed, using
On Mon, Aug 03, 2020 at 03:38:37PM -0400, Frank Ch. Eigler wrote:
> Hi -
>
> > > While this does seem to be the right solution for the extant problem, I
> > > do want to take a moment and ask if the function sections need to be
> > > exposed at all? What tools use this information, and do they
Documentation for sysfs backlight level interface requires that
values in both 'brightness' and 'actual_brightness' files are
interpreted to be in range from 0 to the value given in the
'max_brightness' file.
With amdgpu, max_brightness gives 255, and values written by the user
into 'brightness'
On 8/3/2020 11:42 AM, James Bottomley wrote:
> On Mon, 2020-08-03 at 10:28 -0500, Eric W. Biederman wrote:
> [...]
>> What is wrong with live migration between one qemu process and
>> another qemu process on the same machine not work for this use case?
>>
>> Just reusing live migration would seem
On Sun, Aug 2, 2020 at 5:32 AM Kent Gibson wrote:
>
> On Fri, Jul 31, 2020 at 06:05:10PM +0200, Bartosz Golaszewski wrote:
> > On Sun, Jul 26, 2020 at 3:12 AM Kent Gibson wrote:
[snip!]
> > > >
> > > > > +static u64 gpioline_config_flags(struct gpioline_config *lc, int
> > > > > line_idx)
> >
On Mon, Aug 3, 2020 at 12:14 PM Lakshmi Ramasubramanian
wrote:
>
> On 8/3/20 8:11 AM, Stephen Smalley wrote:
> >
> > Possibly I'm missing something but with these patches applied on top of
> > next-integrity, and the following lines added to /etc/ima/ima-policy:
> >
> > measure func=LSM_STATE
On Mon, Aug 3, 2020 at 8:46 AM Pali Rohár wrote:
>
> On Wednesday 29 July 2020 12:48:09 Rob Herring wrote:
> > On Wed, Jul 15, 2020 at 04:25:56PM +0200, Marek Behún wrote:
> > > From: Pali Rohár
> > >
> > > Providing driver's 'remove' function allows kernel to bind and unbind
> > > devices
> >
On 8/2/20 4:04 PM, William Breathitt Gray wrote:
On Tue, Jul 28, 2020 at 05:45:53PM -0500, David Lechner wrote:
On 7/21/20 2:35 PM, William Breathitt Gray wrote:
This is a reimplementation of the Generic Counter driver interface.
...
-F: include/linux/counter_enum.h
+F:
On Sun, Aug 2, 2020 at 11:32 AM Kent Gibson wrote:
>
> On Sun, Aug 02, 2020 at 11:31:58AM +0800, Kent Gibson wrote:
> > On Fri, Jul 31, 2020 at 06:05:10PM +0200, Bartosz Golaszewski wrote:
> > > On Sun, Jul 26, 2020 at 3:12 AM Kent Gibson wrote:
> > > >
> > >
> > > > >
> > > > > > +
On Mon, 3 Aug 2020 23:50:42 +0900
Masami Hiramatsu wrote:
> Nice catch!
>
> Acked-by: Masami Hiramatsu
>
> Fixes: ae6aa16fdc16 ("kprobes: introduce ftrace based optimization")
> Cc: sta...@vger.kernel.org
Thanks Masami,
I'll add this to my queue for the merge window.
-- Steve
On Mon, 2020-08-03 at 21:41 +0200, Sam Ravnborg wrote:
> On Tue, Jul 07, 2020 at 04:05:39PM -0500, Gustavo A. R. Silva wrote:
> > Replace the existing /* fall through */ comments and its variants with
> > the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
> > fall-through
On 8/3/20 14:41, Sam Ravnborg wrote:
> On Tue, Jul 07, 2020 at 04:05:39PM -0500, Gustavo A. R. Silva wrote:
>> Replace the existing /* fall through */ comments and its variants with
>> the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
>> fall-through markings when it is the
On Mon, Aug 3, 2020 at 5:11 PM Stafford Horne wrote:
>
> On big-endian architectures like OpenRISC, sparse outputs below warnings on
> asm-generic/io.h. This is due to io statements like:
>
> __raw_writel(cpu_to_le32(value), PCI_IOBASE + addr);
>
> The __raw_writel() function expects native
Le 03/08/2020 à 21:35, Joe Perches a écrit :
On Mon, 2020-08-03 at 21:19 +0200, Christophe JAILLET wrote:
Le 03/08/2020 à 17:41, Jakub Kicinski a écrit :
On Sun, 2 Aug 2020 16:15:23 +0200 Christophe JAILLET wrote:
Update the size used in 'dma_free_coherent()' in order to match the one
used
f9d95999bc9c
> commit: 397dc00e249ec64e106374565575dd0eb7e25998 mips: sgi-ip27: switch from
> DISCONTIGMEM to SPARSEMEM
> date: 10 months ago
> config: mips-randconfig-r032-20200803 (attached as .config)
> compiler: mips64-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget
>
On Mon, 3 Aug 2020 18:14:17 + Ahmed Abdelsalam wrote:
> This patch allows copying the DSCP from inner IPv4 header to the
> outer IPv6 header, when doing SRv6 Encapsulation.
>
> This allows forwarding packet across the SRv6 fabric based on their
> original traffic class.
>
> Signed-off-by:
Now that the support is in place with previous commits, we add several
chips that use the BrcmSTB driver.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 4
1 file changed, 4 insertions(+)
diff --git
The Raspberry Pi (RPI) is currently the only chip using this driver
(pcie-brcmstb.c). There, only one memory controller is used, without an
extension region, and the SCB0 viewport size is set to the size of the
first and only dma-range region. Other BrcmSTB SOCs have more complicated
memory
From: Jim Quinlan
Older BrcmSTB chips do not have a separate register for MSI interrupts; the
MSIs are in a register that also contains unrelated interrupts. In
addition, the interrupts lie in bits [31..24] for these legacy chips. This
commit provides common code for both legacy and non-legacy
From: Jim Quinlan
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The
2711 family requires 128B whereas other devices can employ 512. The
assignment is complicated by the fact that the values for this two-bit
field have different meanings;
Value Type_Generic
From: Jim Quinlan
Add in compatibility strings and code for three Broadcom STB chips. Some
of the register locations, shifts, and masks are different for certain
chips, requiring the use of different constants based on of_id.
We would like to add the following at this time to the match list
From: Jim Quinlan
Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
and resume. Now the PCIe driver may do so as well.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
---
drivers/pci/controller/pcie-brcmstb.c | 47 +++
1 file changed,
From: Jim Quinlan
Some STB chips have a special purpose reset controller named RESCAL (reset
calibration). The PCIe HW can now control RESCAL to start and stop its
operation. On probe(), the RESCAL is deasserted and the driver goes
through the sequence of setting registers and reading status
From: Jim Quinlan
The PERST# bit was moved to a different register in 7278-type STB chips.
In addition, the polarity of the bit was also changed; for other chips
writing a 1 specified assert; for 7278-type chips, writing a 0 specifies
assert.
Of course, PERST# is a PCIe asserted-low signal.
From: Jim Quinlan
Have PCIE_BRCMSTB depend on ARCH_BRCMSTB. Also set the default value to
ARCH_BRCMSTB.
Signed-off-by: Jim Quinlan
Acked-by: Florian Fainelli
Reviewed-by: Rob Herring
---
drivers/pci/controller/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Jim Quinlan
- Add compatible strings for three more Broadcom STB chips: 7278, 7216,
7211 (STB version of RPi4).
- Add new property 'brcm,scb-sizes'.
- Add new property 'resets'.
- Add new property 'reset-names' for 7216 only.
- Allow 'ranges' and 'dma-ranges' to have more than one item
Patchset Summary:
Enhance a PCIe host controller driver. Because of its unusual design
we are foced to change dev->dma_pfn_offset into a more general role
allowing multiple offsets. See the 'v1' notes below for more info.
v10:
Commit: "device-mapping: Introduce DMA range map,
Hi Tom,
On Mon, Jul 20, 2020 at 12:18:45PM -0700, t...@redhat.com wrote:
> From: Tom Rix
>
> clang static analysis reports this repesentative error
>
> pvr2fb.c:1049:2: warning: 1st function call argument
> is an uninitialized value [core.CallAndMessage]
> if (*cable_arg)
>
commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")
Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register and uses it by
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
Tegra210 and later has a separate sdmmc_legacy_tm (TMCLK) used by Tegra
SDMMC hawdware for data timeout to achive better timeout than using
SDCLK and using TMCLK is recommended.
USE_TMCLK_FOR_DATA_TIMEOUT bit in Tegra SDMMC register
commit 4346b7c7941d ("mmc: tegra: Add Tegra186 support")
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra186 from the
beginning of its support in driver.
Tegra186 SDMMC hardware by default uses timeout clock (TMCLK) instead
of SDCLK and this quirk should not be set.
So, this patch remove
commit 5425fb15d8ee ("arm64: tegra: Add Tegra194 chip device tree")
Tegra194 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra194 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.
So, this
Tegra210/Tegra186/Tegra194 has incorrectly enabled
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK from the beginning of their support.
Tegra210 and later SDMMC hardware default uses sdmmc_legacy_tm (TMCLK)
all the time for hardware data timeout instead of SDCLK and this TMCLK
need to be kept enabled by
commit 742af7e7a0a1 ("arm64: tegra: Add Tegra210 support")
Tegra210 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.
Tegra SDMMC advertises 12Mhz as timeout clock frequency in host
capability register.
So, this clock should
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support")
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra210 from the
beginning of Tegra210 support in the driver.
Tegra210 SDMMC hardware by default uses timeout clock (TMCLK)
instead of SDCLK and this quirk should not be set.
So, this patch
From: Nick Terrell
This patch replaces all memcpy() calls with LZ4_memcpy() which calls
__builtin_memcpy() so the compiler can inline it.
LZ4 relies heavily on memcpy() with a constant size being inlined. In
x86 and i386 pre-boot environments memcpy() cannot be inlined because
memcpy() doesn't
Quoting Anson Huang (2020-07-29 18:22:49)
> Use readl_relaxed() instead of __raw_readl(), and use BIT(x)
> instead of (1 << X) to fix below build warning reported by kernel
> test robot:
>
> drivers/clk/imx/clk-imx6sl.c:149:49: warning: Shifting signed 32-bit
> value by 31 bits is undefined
On Tue, Jul 07, 2020 at 04:05:39PM -0500, Gustavo A. R. Silva wrote:
> Replace the existing /* fall through */ comments and its variants with
> the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
> fall-through markings when it is the case.
>
> [1]
>
Hi -
> > While this does seem to be the right solution for the extant problem, I
> > do want to take a moment and ask if the function sections need to be
> > exposed at all? What tools use this information, and do they just want
> > to see the bounds of the code region? (i.e. the start/end of all
Hi Linus,
Please pull these seccomp updates for v5.9-rc1. There are a bunch of
clean ups and selftest improvements along with two major updates to the
SECCOMP_RET_USER_NOTIF filter return: EPOLLHUP support to more easily
detect the death of a monitored process, and being able to inject fds when
Quoting Taniya Das (2020-08-01 11:13:35)
> Update the clock controller nodes for Low power audio subsystem
> functionality.
>
> Signed-off-by: Taniya Das
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
3 files
Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable
split pagetables and per-instance pagetables for drm/msm.
Signed-off-by: Jordan Crouse
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
---
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
---
Each submitqueue is attached to a context. Add a pointer to the
context to the submitqueue at create time and refcount it so
that it stays around through the life of the queue.
GPU submissions can access the active context via the submitqueue
instead of requiring it to be passed around from
This series adds an Adreno SMMU implementation to arm-smmu to allow GPU hardware
pagetable switching.
The Adreno GPU has built in capabilities to switch the TTBR0 pagetable during
runtime to allow each individual instance or application to have its own
pagetable. In order to take advantage of
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in the
arm-smmu implementation specific code.
Do a bit of prep work to add the upcoming adreno-smmu implementation.
Add an hook to allow the implementation to choose which context banks
to allocate. Then, add domain_attr_get / domain_attr_set hooks to allow
for implementation specific domain attributes.
Move some of the common structs to
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