Hi Sam,
On 07/09/2020 12:54, Sam Ravnborg wrote:
> On Mon, Sep 07, 2020 at 12:33:41PM +0200, Neil Armstrong wrote:
>> Hi,
>>
>> Please ignore this serie, the vendors patch is missing and the panel driver
>> still has the vrefresh...
>>
>> Will repost.
>
> Please fix so DRM_DEV_* is replaced by de
On Fri, Sep 4, 2020 at 6:48 PM Andy Shevchenko
wrote:
>
> On Fri, Sep 04, 2020 at 05:45:37PM +0200, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > While we do check the "chip-name" property in probe(), we never actually
> > use it. Let's pass the chip label to the driver using d
This commit adds the pinctrl driver for the MediaTek's MT8167 SoC.
Signed-off-by: Fabien Parent
---
drivers/pinctrl/mediatek/Kconfig |7 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt8167.c | 362 +
drivers/pinctrl/mediatek
Add binding documentation of pinctrl-mt65xx for MT8167 SoC.
Signed-off-by: Fabien Parent
---
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
b/Documentation/devicetree/b
On Mon, Sep 07, 2020 at 01:15:14PM +0200, Jason A. Donenfeld wrote:
> Gotcha. So your perspective is that the goal is actually to have no
> list at all in the end, because all MSR writes should go through sysfs
> interfaces and such, always? I certainly like that goal -- it'd make a
> whole lot of
On 07.09.2020 05:54, Muchun Song wrote:
> Hi all,
>
> Any comments or suggestions? Thanks.
>
> On Fri, Aug 28, 2020 at 11:19 AM Muchun Song wrote:
>>
>> There is a race between the assignment of `table->data` and write value
>> to the pointer of `table->data` in the __do_proc_doulongvec_minmax()
On 09/07/2020 12:02 PM, Will Deacon wrote:
[+ Suzuki as I'd like his Ack on this]
Thanks Will !
On Fri, Aug 14, 2020 at 05:39:40PM -0700, Tuan Phan wrote:
Add support for probing device from ACPI node.
Each DSU ACPI node and its associated cpus are inside a cluster node.
Signed-off-by: Tua
On Mon, Sep 7, 2020 at 1:50 PM Andy Shevchenko
wrote:
>
> On Mon, Sep 07, 2020 at 01:04:29PM +0200, Bartosz Golaszewski wrote:
> > On Fri, Sep 4, 2020 at 6:49 PM Andy Shevchenko
> > wrote:
> > > On Fri, Sep 04, 2020 at 05:45:39PM +0200, Bartosz Golaszewski wrote:
> > > > From: Bartosz Golaszewski
The function is now only a helper that searches the
connection from device graph and then by checking if the
supplied connection identifier matches a property that
contains reference.
Signed-off-by: Heikki Krogerus
---
drivers/base/Makefile| 2 +-
drivers/base/devcon.c| 101 ---
This is second version of this series. I forgot to remove the file
from Documentation/driver-api/index.rst. Hopefully these are now OK.
The original cover letter:
Hi,
This was the last patch in my series that removed struct
device_connection [1]. It's now split into two separate patches.
[1]
h
On Mon, Sep 07, 2020 at 09:37:12PM +0800, Tzung-Bi Shih wrote:
> On Thu, Aug 20, 2020 at 3:40 AM Mark Brown wrote:
> > That's for binding the MFD subdevice to an OF node, you don't need to do
> > that for a device like this - you can just use the of_node of the parent
> > to get at the properties
On 07/09/2020 19:47, Pali Rohár wrote:
On Monday 07 September 2020 19:43:08 Andre Heider wrote:
On 07/09/2020 19:35, Pali Rohár wrote:
On Monday 07 September 2020 19:23:03 Andrew Lunn wrote:
My dts-foo is a little rusty, but now that you labeled the ports in the
.dtsi, can this whole "switch0"
These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.
Jianjun Wang (3):
dt-bindings: Add YAML schemas for Gen3 PCIe controller
PCI: mediatek: Add new generation controller support
MAINTAINERS: update entry for MediaTek PCIe controller
a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Cheng-Yi-Chiang/Add-documentation-and-machine-driver-for-SC7180-sound-card/20200907-180250
base: https://git.kern
From: Leon Romanovsky
Changelog:
v2:
* Rebased on top of the 524d8ffd07f0
* Removed "udata" check in destroy flows
* Changed ib_free_cq to return early
* Used Jason's suggestion to implement "RDMA/mlx5: Issue FW command to destroy
SRQ on reentry" patch.
v1
* Changed returned value in efa_
Hi Catalin, sorry for the late reply, I was on vacation.
On Fri, 2020-08-28 at 18:43 +0100, Catalin Marinas wrote:
> Hi Nicolas,
>
> On Wed, Aug 19, 2020 at 08:24:33PM +0200, Nicolas Saenz Julienne wrote:
> > There is no benefit in splitting the 32-bit address space into two
> > distinct DMA zone
On 01/09/2020 01:32, Jonathan Marek wrote:
-#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
-#define FASTRPC_IOCTL_MUNMAP_IOWR('R', 7, struct
fastrpc_req_munmap)
+#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
+#define
On Mon, Aug 17, 2020 at 05:34:23PM +0530, Anshuman Khandual wrote:
> HWCAP name arrays (hwcap_str, compat_hwcap_str, compat_hwcap2_str) that are
> scanned for /proc/cpuinfo are detached from their bit definitions making it
> vulnerable and difficult to correlate. It is also bit problematic because
On Mon, Sep 07, 2020 at 12:00:10PM +, Song Bao Hua (Barry Song) wrote:
> Hi All,
> In case we have a numa system with 4 nodes and in each node we have 24 cpus,
> and all of the 96 cores are idle.
> Then we start a process with 4 threads in this totally idle system.
> Actually any one of the f
On Mon, Sep 07, 2020 at 02:06:15PM +0200, Bartosz Golaszewski wrote:
> On Mon, Sep 7, 2020 at 1:53 PM Andy Shevchenko
> wrote:
> > On Mon, Sep 07, 2020 at 12:26:34PM +0200, Bartosz Golaszewski wrote:
> > > On Mon, Sep 7, 2020 at 11:59 AM Andy Shevchenko
> > > wrote:
> > > > On Fri, Sep 04, 2020 a
On 07/09/20 12:41, pet...@infradead.org wrote:
> So cenceptually there's the problem that idle must always be runnable,
> and the moment you boost it, it becomes subject to a different
> scheduling class.
>
> Imagine for example what happens when we boost it to RT and then have it
> be subject to
Below is the list of build error/warning regressions/improvements in
v5.9-rc4[1] compared to v5.8[2].
Summarized:
- build errors: +4/-3
- build warnings: +64/-24
JFYI, when comparing v5.9-rc4[1] to v5.9-rc3[3], the summaries are:
- build errors: +0/-0
- build warnings: +2/-2
Happy fixing
Use function callbacks for SCU related functions in pinctrl-imx.c
in order to support the scenario of PINCTRL_IMX is built in while
PINCTRL_IMX_SCU is built as module, all drivers using SCU pinctrl
driver need to initialize the SCU related function callback.
Signed-off-by: Anson Huang
---
Changes
Add bare protocol support for SCMI SystemPower as needed by an OSPM agent:
basic initialization and SYSTEM_POWER_STATE_NOTIFIER core notification
support.
No event-handling logic is attached to such notification by this commit.
Signed-off-by: Cristian Marussi
---
v4 --> v5
- system notifications
Hi all,
this series wants to add the core SCMI System Power support and related
events' handling logic: the protocol support itself is trivial and boils
down to some bare initializations and supporting one SCMI System Power
notification event meant to carry platform-originated System transition
re
It was <2020-08-26 śro 09:13>, when Geert Uytterhoeven wrote:
> On Tue, Aug 25, 2020 at 8:02 PM Andrew Lunn wrote:
>> On Tue, Aug 25, 2020 at 07:03:09PM +0200, Łukasz Stelmach wrote:
>> > + if (netif_msg_pktdata(ax_local)) {
>> > + int loop;
>> > + netdev_info(ndev, "TX
On Monday 07 September 2020 19:43:08 Andre Heider wrote:
> On 07/09/2020 19:35, Pali Rohár wrote:
> > On Monday 07 September 2020 19:23:03 Andrew Lunn wrote:
> > > > My dts-foo is a little rusty, but now that you labeled the ports in the
> > > > .dtsi, can this whole "switch0" block reduced to some
Add SCMI System Power device name to the core list of supported protocol
devices.
Signed-off-by: Cristian Marussi
---
drivers/firmware/arm_scmi/driver.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/arm_scmi/driver.c
b/drivers/firmware/arm_scmi/driver.c
index f749af6e79fc
Add an SCMI System Power control driver to handle platform's requests
carried by SYSTEM_POWER_STATE_NOTIFIER notifications: such platform
requested system power state transitions are handled accordingly,
gracefully or forcefully, depending on the notifications' message flags.
Graceful requests are
Hi Eric,
On 9/3/2020 11:15 PM, Auger Eric wrote:
Hi Diana,
On 8/26/20 11:33 AM, Diana Craciun wrote:
This patch adds the skeleton for interrupt support
for fsl-mc devices. The interrupts are not yet functional,
the functionality will be added by subsequent patches.
Signed-off-by: Bharat Bhush
From: Zhang Changzhong Sent: Monday, September 7,
2020 8:50 PM
> Because clk_prepare_enable() and clk_disable_unprepare() already checked
> NULL clock parameter, so the additional checks are unnecessary, just remove
> them.
>
> Reported-by: Hulk Robot
> Signed-off-by: Zhang Changzhong
Acked-b
On Fri, Jul 24, 2020 at 05:16:04PM +0800, Wei Li wrote:
> Armv8.3 extends the SPE by adding:
> - Alignment field in the Events packet, and filtering on this event
> using PMSEVFR_EL1.
> - Support for the Scalable Vector Extension (SVE).
>
> The main additions for SVE are:
> - Recording the vecto
On Tue, Sep 01, 2020 at 02:15:30PM -0500, Gage Eads wrote:
> --- /dev/null
> +++ b/drivers/misc/dlb2/dlb2_main.c
> @@ -0,0 +1,208 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/* Copyright(c) 2018-2020 Intel Corporation */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
On Mon, Sep 7, 2020 at 5:16 AM Lorenzo Pieralisi
wrote:
>
> On Thu, Aug 27, 2020 at 09:29:59AM -0400, Jim Quinlan wrote:
> > On Thu, Aug 27, 2020 at 2:35 AM Christoph Hellwig wrote:
> > >
> > > On Tue, Aug 25, 2020 at 10:40:27AM -0700, Florian Fainelli wrote:
> > > > Hi,
> > > >
> > > > On 8/24/2
From: Joerg Roedel
The inat-tables.c file has some arrays in it that contain pointers to
other arrays. These pointers need to be relocated when the kernel
image is moved to a different location.
The pre-decompression boot-code has no support for applying ELF
relocations, so initialize these arra
From: Joerg Roedel
Move the definition of the x86 page-fault error code bits to the new
header file asm/trap_pf.h. This makes it easier to include them into
pre-decompression boot code. No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/trap_pf.h | 24 +
On 07/09/2020 19:42, Pali Rohár wrote:
On Monday 07 September 2020 19:13:41 Andre Heider wrote:
@@ -120,7 +124,7 @@
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ switch0port0: port@0 {
This labe
From: Joerg Roedel
Hi,
here is a new version of the SEV-ES Guest Support patches for x86. The
previous versions can be found as a linked list starting here:
https://lore.kernel.org/lkml/20200824085511.7553-1-j...@8bytes.org/
I updated the patch-set based on ther review comments I got a
From: Tom Lendacky
Extend the vmcb_safe_area with SEV-ES fields and add a new
'struct ghcb' which will be used for guest-hypervisor communication.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/svm.h | 51 --
arch/x86/kvm/s
On Mon, Sep 07, 2020 at 11:52:20AM +0200, John Paul Adrian Glaubitz wrote:
> Hi Rich!
>
> On 9/3/20 6:16 PM, Rich Felker wrote:
> >> I can confirm that this patch fixes both strace for me and does not break
> >> libseccomp,
> >> I have run the libseccomp testsuite with my patch for SuperH support
Masami Hiramatsu writes:
> Sorry, for noticing this point, I Cc'd to systemtap. Is systemtap taking
> care of spinlock too?
On PRREMPT_RT configurations, systemtap uses the raw_spinlock_t
types/functions, to keep its probe handlers as atomic as we can make them.
- FChE
From: Joerg Roedel
Building a correct GHCB for the hypervisor requires setting valid bits
in the GHCB. Simplify that process by providing accessor functions to
set values and to update the valid bitmap and to check the valid bitmap
in KVM.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/s
From: Joerg Roedel
Do not allocate a vmcb_control_area and a vmcb_save_area on the stack,
as these structures will become larger with future extenstions of
SVM and thus the svm_set_nested_state() function will become a too large
stack frame.
Signed-off-by: Joerg Roedel
---
arch/x86/kvm/svm/nes
On 07/09/2020 19:35, Pali Rohár wrote:
On Monday 07 September 2020 19:23:03 Andrew Lunn wrote:
My dts-foo is a little rusty, but now that you labeled the ports in the
.dtsi, can this whole "switch0" block reduced to something like:
&switch0port1 {
label = "lan1";
};
&switch0port3 {
From: Joerg Roedel
Add code needed to setup an IDT in the early pre-decompression
boot-code. The IDT is loaded first in startup_64, which is after
EfiExitBootServices() has been called, and later reloaded when the
kernel image has been relocated to the end of the decompression area.
This allows
The command "make coccicheck C=1 CHECK=scripts/coccicheck" results in the
error:
./scripts/coccicheck: line 65: -1: shift count out of range
This happens because every time the C variable is specified,
the shell arguments need to be "shifted" in order to take only
the last argument, which
On Monday 07 September 2020 19:13:41 Andre Heider wrote:
> > @@ -120,7 +124,7 @@
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - port@0 {
> > + switch0port0: port@0 {
>
> This label is unused it seems.
Yes, it is u
On Fri, 4 Sep 2020 17:57:38 +0800, Qi Liu wrote:
> event_idx is obtained from armv8pmu_get_event_idx(), and this idx must be
> between ARMV8_IDX_CYCLE_COUNTER and cpu_pmu->num_events. So it's unnecessary
> to do this check. Let's remove it.
Applied to will (for-next/perf), thanks!
[1/1] arm64: pe
From: Tom Lendacky
Add code to handle #VC exceptions on DR7 register reads and writes.
This is needed early because show_regs() reads DR7 to print it out.
Under SEV-ES there is currently no support for saving/restoring the
DRx registers, but software expects to be able to write to the DR7
regist
From: Joerg Roedel
Add handling for emulation the MOVS instruction on MMIO regions, as done
by the memcpy_toio() and memcpy_fromio() functions.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 77
1 file changed, 77 insertions(+)
diff --git a
From: Tom Lendacky
Implement a handler for #VC exceptions caused by WBINVD instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling framework ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 9 +
1 file changed, 9 in
From: Tom Lendacky
Implement a handler for #VC exceptions caused by RDMSR/WRMSR
instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 28
From: Tom Lendacky
Add the handlers for #VC exceptions invoked at runtime.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/idtentry.h | 6 +
arch/x86/kernel/idt.c | 11 +-
arch/x86/kernel/sev-es.c| 246 +++-
3 f
From: Joerg Roedel
When a #VC exception is triggered by user-space the instruction decoder
needs to read the instruction bytes from user addresses. Enhance
vc_decode_insn() to safely fetch kernel and user instructions.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 31
From: Tom Lendacky
Add handler for VC exceptions caused by MMIO intercepts. These
intercepts come along as nested page faults on pages with reserved
bits set.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to VC handling framework ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roed
From: Joerg Roedel
Re-use the handlers for CPUID and IOIO caused #VC exceptions in the
early boot handler.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es-shared.c | 7 +++
arch/x86/kernel/sev-es.c| 6 ++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arc
It was <2020-08-25 wto 20:01>, when Andrew Lunn wrote:
> Hi Łukasz
>
> It is pretty clear this is a "vendor crap driver".
I can't deny.
> It needs quite a bit more work on it.
I'll be more than happy to take your suggestions.
> On Tue, Aug 25, 2020 at 07:03:09PM +0200, Łukasz Stelmach wrote:
>
From: Joerg Roedel
When an NMI hits in the #VC handler entry code before it switched to
another stack, any subsequent #VC exception in the NMI code-path will
overwrite the interrupted #VC handlers stack.
Make sure this doesn't happen by explicitly adjusting the #VC IST entry
in the NMI handler
From: Joerg Roedel
The #VC handler needs special entry code because:
1. It runs on an IST stack
2. It needs to be able to handle nested #VC exceptions
To make this work the entry code is implemented to pretend it doesn't
use an IST stack. When entered from user-mode or early SY
From: Joerg Roedel
The get_stack_info functionality is needed in the entry code for the #VC
exception handler. Provide a version of it in the .text.noinstr
section which can be called safely from there.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/stacktrace.h | 2 ++
arch/x86/kernel/
From: Tom Lendacky
The runtime handler needs a GHCB per CPU. Set them up and map them
unencrypted.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/mem_encrypt.h | 2 ++
arch/x86/kernel/sev-es.c | 56 +-
arch/x86/kernel/tr
From: Joerg Roedel
Load the GDT right after switching to virtual addresses to make sure
there is a defined GDT for exception handling.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/kernel/head_64.S | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
From: Joerg Roedel
Allocate and map an IST stack and an additional fall-back stack for
the #VC handler. The memory for the stacks is allocated only when
SEV-ES is active.
The #VC handler needs to use an IST stack because it could be raised
from kernel space with unsafe stack, e.g. in the SYSCAL
From: Joerg Roedel
Force a page-fault on any further accesses to the GHCB page when they
shouldn't happen anymore. This will catch the bugs where a #VC exception
is raised when no one is expected anymore.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/ident_map_64.c | 17
From: Joerg Roedel
Setup sev-es.c and include the code from the
pre-decompression stage to also build it into the image of the running
kernel. Temporarily add __maybe_unused annotations to avoid build
warnings until the functions get used.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/Makefi
From: Joerg Roedel
Setup an early handler for #VC exceptions. There is no GHCB mapped
yet, so just re-use the vc_no_ghcb_handler. It can only handle CPUID
exit-codes, but that should be enough to get the kernel through
verify_cpu() and __startup_64() until it runs on virtual addresses.
Signed-of
From: Joerg Roedel
The xgetbv() function is needed in pre-decompression boot code, but
asm/fpu/internal.h can't be included there directly. Doing so opens
the door to include-hell due to various include-magic in
boot/compressed/misc.h.
Avoid that by moving xgetbv()/xsetbv() to a separate header
From: Joerg Roedel
Make sure segments are properly set up before setting up an IDT and
doing anything that might cause a #VC exception. This is later needed
for early exception handling.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/kernel/head_64.S | 52 +++-
From: Joerg Roedel
Add the first handler for #VC exceptions. At stage 1 there is no GHCB
yet becaue the kernel might still be running on the EFI page table.
The stage 1 handler is limited to the MSR based protocol to talk to
the hypervisor and can only support CPUID exit-codes, but that is
enoug
From: Joerg Roedel
The code to setup idt_data is needed for early exception handling, but
set_intr_gate() can't be used that early because it has pv-ops in its
code path, which don't work that early.
Split out the idt_data initialization part from set_intr_gate() so
that it can be used separatel
From: Joerg Roedel
Changing the function to take start and end as parameters instead of
start and size simplifies the callers, which don't need to calculate
the size if they already have start and end.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/boot/compressed/ident_map_6
From: Tom Lendacky
Handle #VC exceptions caused by CPUID instructions. These happen in
early boot code when the KASLR code checks for RDTSC.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling framework ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86
From: Joerg Roedel
Move the assembly coded dispatch between page-faults and all other
exceptions to C code to make it easier to maintain and extend.
Also change the return-type of early_make_pgtable() to bool and make it
static.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable.h |
On Monday 07 September 2020 19:23:03 Andrew Lunn wrote:
> > My dts-foo is a little rusty, but now that you labeled the ports in the
> > .dtsi, can this whole "switch0" block reduced to something like:
> >
> > &switch0port1 {
> > label = "lan1";
> > };
> >
> > &switch0port3 {
> > label = "
From: Joerg Roedel
The function can fail to create an identity mapping, check for that
and bail out if it happens.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/ident_map_64.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/boot/compressed/ident_m
From: Joerg Roedel
The file contains only code related to identity mapped page-tables.
Rename the file and compile it always in.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/boot/compressed/Makefile | 2 +-
arch/x86/boot/compressed/{kaslr_64.c => ident
From: Joerg Roedel
Handling exceptions during boot requires a working GDT. The kernel GDT
can't be used on the direct mapping, so load a startup GDT and setup
segments.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/setup.h | 1 +
arch/x86/kernel/head64.c | 33 ++
From: Joerg Roedel
Add the sev_es_active function for checking whether SEV-ES is enabled.
Also cache the value of MSR_AMD64_SEV at boot to speed up the feature
checking in the running code.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/include/asm/mem_encrypt.h | 3 +++
arch
From: Joerg Roedel
Install a page-fault handler to add an identity mapping to addresses
not yet mapped. Also do some checking whether the error code is sane.
This makes non SEV-ES machines use the exception handling
infrastructure in the pre-decompressions boot code too, making it less
likely to
From: Joerg Roedel
Make sure there is a stack once the kernel runs from virual addresses.
At this stage any secondary CPU which boots will have lost its stack
because the kernel switched to a new page-table which does not map the
real-mode stack anymore.
This is needed for handling early #VC exc
From: Tom Lendacky
Add support for decoding and handling #VC exceptions for IOIO events.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapted code to #VC handling framework ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/sev-es.c | 32 +
arch/x
From: Joerg Roedel
The functions are needed to map the GHCB for SEV-ES guests. The GHCB is
used for communication with the hypervisor, so its content must not be
encrypted. After the GHCB is not needed anymore it must be mapped
encrypted again so that the running kernel image can safely re-use th
From: Joerg Roedel
Move these two functions from kernel/idt.c to include/asm/desc.h:
* init_idt_data()
* idt_init_desc()
These functions are needed to setup IDT entries very early and need to
be called from head64.c. To be usable this early these functions need to
be compiled wi
From: Joerg Roedel
Install an exception handler for #VC exception that uses a GHCB. Also
add the infrastructure for handling different exit-codes by decoding
the instruction that caused the exception and error handling.
Signed-off-by: Joerg Roedel
---
arch/x86/Kconfig
From: Joerg Roedel
When booted through startup_64 the kernel keeps running on the EFI
page-table until the KASLR code sets up its own page-table. Without
KASLR the pre-decompression boot code never switches off the EFI
page-table. Change that by unconditionally switching to a kernel
controlled pa
From: Joerg Roedel
Factor out the code to fetch the instruction from user-space to a helper
function.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/insn-eval.h | 2 ++
arch/x86/kernel/umip.c | 26 +-
arch/x86/lib/insn-eval.c
From: Joerg Roedel
Factor out the code used to decode an instruction with the correct
address and operand sizes to a helper function.
No functional changes.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/insn-eval.h | 2 ++
arch/x86/kernel/umip.c | 23 +---
arch/x
From: Tom Lendacky
Add CPU feature detection for Secure Encrypted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include
From: Joerg Roedel
Add a function to the instruction decoder which returns the pt_regs
offset of the register specified in the reg field of the modrm byte.
Signed-off-by: Joerg Roedel
Acked-by: Masami Hiramatsu
---
arch/x86/include/asm/insn-eval.h | 1 +
arch/x86/lib/insn-eval.c | 23
From: Joerg Roedel
Call set_sev_encryption_mask() while still on the stage 1 #VC-handler,
because the stage 2 handler needs the kernel's own page-tables to be
set up, to which calling set_sev_encryption_mask() is a prerequisite.
Signed-off-by: Joerg Roedel
---
arch/x86/boot/compressed/head_64.
From: Joerg Roedel
Add a function to check whether an instruction has a REP prefix.
Signed-off-by: Joerg Roedel
Reviewed-by: Masami Hiramatsu
---
arch/x86/include/asm/insn-eval.h | 1 +
arch/x86/lib/insn-eval.c | 24
2 files changed, 25 insertions(+)
diff --
From: Joerg Roedel
With the page-fault handler in place the identity mapping can be built
on-demand. So remove the code which manually creates the mappings and
unexport/remove the functions used for it.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/boot/compressed/ident_map_
From: Tom Lendacky
Implement a handler for #VC exceptions caused by RDPMC instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 22 ++
1
From: Tom Lendacky
Implement a handler for #VC exceptions caused by RDTSC and RDTSCP
instructions. Also make it available in the pre-decompression stage
because the KASLR code used RDTSC/RDTSCP to gather entropy and some
hypervisors intercept these instructions.
Signed-off-by: Tom Lendacky
[ jr
On Mon, 7 Sep 2020, Markus Elfring wrote:
> >> +++
> >> b/scripts/coccinelle/api/use_devm_platform_get_and_ioremap_resource.cocci
> >> @@ -0,0 +1,48 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/// Simplify a function call combination by using a known wrapper
> >> function.
> >> +//
> >
On Mon, Sep 07, 2020 at 06:29:13PM +0200, Ahmed S. Darwish wrote:
> I've been unsuccessful in reproducing this huge, 200+ bytes, difference.
> Can I please get the defconfig and GCC version?
I think I lost the config and it's either gcc-9.3 or gcc-10, I can't
remember.
I just tried with:
make
From: Joerg Roedel
When running under SEV-ES the kernel has to tell the hypervisor when to
open the NMI window again after an NMI was injected. This is done with
an NMI-complete message to the hypervisor.
Add code to the kernels NMI handler to send this message right at the
beginning of do_nmi()
From: Joerg Roedel
The code at the trampoline entry point is executed in real-mode. In
real-mode #VC exceptions can't be handled, so anything that might cause
such an exception must be avoided.
In the standard trampoline entry code this is the WBINVD instruction and
the call to verify_cpu(), whi
From: Doug Covelli
Add VMware specific handling for #VC faults caused by VMMCALL
instructions.
Signed-off-by: Doug Covelli
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: - Adapt to different paravirt interface ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/c
From: Joerg Roedel
The APs are not ready to handle exceptions when verify_cpu() is called
in secondary_startup_64.
Signed-off-by: Joerg Roedel
Reviewed-by: Kees Cook
---
arch/x86/include/asm/realmode.h | 1 +
arch/x86/kernel/head_64.S | 12
arch/x86/realmode/init.c
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