On Thu, Nov 19, 2020 at 8:26 AM wrote:
>
> From: Patrice Chotard
>
> Add dev_wakeup_path() helper to avoid to spread
> dev->power.wakeup_path test in drivers.
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Ulf Hansson
> ---
>
> Changes from v1:
> - Fold the 4 v1 patches into one
> - Add
Add a new vxattr that allows userspace to list the caps for a specific
directory or file.
Signed-off-by: Luis Henriques
---
Hi!
Here's a version that also shows the caps in hexadecimal format, as
suggested by Jeff. IMO the parenthesis and the '0x' prefix help the
readability, but they may make
On Mon, 16 Nov 2020 20:43:17 +,
David Brazdil wrote:
>
> While protected nVHE KVM is installed, start trapping all host SMCs.
> By default, these are simply forwarded to EL3, but PSCI SMCs are
> validated first.
>
> Create new constant HCR_HOST_NVHE_PROTECTED_FLAGS with the new set of HCR
>
On Mon, 2020-11-23 at 22:54 +0530, Aditya Srivastava wrote:
> Currently, checkpatch.pl warns for BAD_SIGN_OFF on non-standard signature
> styles.
I think this proposed change is unnecessary.
> This warning occurs because of incorrect use of signature tags,
> e.g. an evaluation on v4.13..v5.8
On Mon, Nov 23, 2020 at 06:06:31PM +0100, Rafael J. Wysocki wrote:
> On Mon, Nov 23, 2020 at 4:32 PM Heikki Krogerus
> wrote:
> >
> > Hi,
> >
> > I originally introduced these as part of my series where I was
> > proposing PM ops for software nodes [1], but since that still needs
> > work, I'm
On Tue, Nov 17, 2020 at 7:50 PM Ionela Voinescu wrote:
>
> While the current domain and cpu lists are appropriate for ALL and ANY
> coordination types where single structures are kept for the domain and
> CPU data, they can be inefficient for NONE and HW coordination types,
> where domain
syzbot has found a reproducer for the following issue on:
HEAD commit:418baf2c Linux 5.10-rc5
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=161c84ed50
kernel config: https://syzkaller.appspot.com/x/.config?x=5524c10373633a9c
dashboard link:
On Mon, 16 Nov 2020 20:43:15 +,
David Brazdil wrote:
>
> Add an early parameter that allows users to opt into protected KVM mode
> when using the nVHE hypervisor. In this mode, guest state will be kept
> private from the host. This will primarily involve enabling stage-2
> address
On Thu, Nov 19, 2020 at 07:10:50PM +, Cristian Marussi wrote:
> +This binding uses the common regulator binding[6] but, due to SCMI
> abstractions,
> +supports only a subset of its properties as specified below amongst Optional
> +properties.
> +Required properties:
> + - reg : shall
On Mon, Nov 23, 2020 at 04:03:00PM +, Stefan Chulski wrote:
> > -Original Message-
> > From: Russell King - ARM Linux admin
> > Sent: Monday, November 23, 2020 5:52 PM
> > To: Stefan Chulski
> > Cc: net...@vger.kernel.org; thomas.petazz...@bootlin.com;
> > da...@davemloft.net; Nadav
On Tue, Nov 17, 2020 at 2:48 PM Lukasz Luba wrote:
>
> The constrain name has limit of size 30, which sometimes might be hit.
> When this happens the new line might get lost. Prevent this and set the
> max limit for name string length equal 29. This would result is proper
> string clamping (when
* Arnd Bergmann [201123 16:55]:
> On Mon, Nov 16, 2020 at 10:04 AM Tony Lindgren wrote:
> >
> > * Grygorii Strashko [201030 14:47]:
> > > Enable networking options required for NFS boot on TI platforms, which is
> > > widely for automated test systems.
> > > - enable new TI CPSW switch driver
On Fri, Nov 13, 2020 at 9:58 AM Alex Shi wrote:
>
> Add parameter explanation to fix kernel-doc marks:
>
> kernel/power/suspend.c:233: warning: Function parameter or member
> 'state' not described in 'suspend_valid_only_mem'
> kernel/power/suspend.c:344: warning: Function parameter or member
>
Hi,
On Mon, Nov 9, 2020 at 5:01 PM Douglas Anderson wrote:
>
> When I run:
> scripts/kernel-doc -rst drivers/gpu/drm/panel/panel-simple.c
>
> I see that several of the kernel-doc entries aren't showing up because
> they don't specify the full path down the hierarchy. Let's fix that
> and also
Currently, checkpatch.pl warns for BAD_SIGN_OFF on non-standard signature
styles.
This warning occurs because of incorrect use of signature tags,
e.g. an evaluation on v4.13..v5.8 showed the use of following incorrect
signature tags, which may seem correct, but are not standard:
1) Requested-by
On Sat, 21 Nov 2020, Moritz Fischer wrote:
Hi Matthew,
On Wed, Nov 18, 2020 at 11:01:51AM -0800, matthew.gerl...@linux.intel.com wrote:
From: Matthew Gerlach
A DFL may not begin at offset 0 of BAR 0. A PCIe vendor
specific capability can be used to specify the start of a
number of DFLs.
Adding Lorenzo and Sudeep to this one in particular, as there is a bit
of a corner case below.
On Mon, 16 Nov 2020 20:43:14 +,
David Brazdil wrote:
>
> Add a handler of CPU_SUSPEND host PSCI SMCs. The SMC can either enter
> a sleep state indistinguishable from a WFI or a deeper sleep state
On Thu, 2020-11-12 at 23:26 -0800, Dmitry Torokhov wrote:
> On Thu, Nov 12, 2020 at 07:52:14PM +0200, Andy Shevchenko wrote:
> > On Thu, Nov 12, 2020 at 6:40 PM Nicolas Saenz Julienne
> > wrote:
> > >
> > > When unbinding the firmware device we need to make sure it has no
> > > consumers left.
On Mon, Nov 23, 2020 at 05:06:31PM +, Paoloni, Gabriele wrote:
> From my understanding no_way_out and kill_it are different in principles:
> no_way_out is telling that an error occurred 'somewhere' in some CPU bank
> that requires the system to panic (e.g. PCC=1); kill_it is saying that the
>
On 11/23, Daeho Jeong wrote:
> From: Daeho Jeong
>
> Added two ioctl to decompress/compress explicitly the compression
> enabled file in "compress_mode=user-based" mount option.
>
> Using these two ioctls, the users can make a control of compression
> and decompression of their files.
>
>
On 11/23, Daeho Jeong wrote:
> From: Daeho Jeong
>
> We will add a new "compress_mode" mount option to control file
> compression mode. This supports "fs-based" and "user-based".
> In "fs-based" mode (default), f2fs does automatic compression on
> the compression enabled files. In "user-based"
Hi!
> > > >How is it supposed to be useful?
> > > >
> > > >I'm pretty sure there are critical data that are not measured by
> > > >proposed module... and that are written under normal circumstances.
> > > >
> > > The goal of this series is to introduce the IMA hook
> > > measure_critical_data()
On Mon, Nov 23, 2020 at 11:06:21AM -0500, Pavel Tatashin wrote:
> What I mean here is allowing users to guarantee that the page's PA is
> going to stay the same. Sort of a stronger mlock. Mlock only
> guarantees that the page is not swapped, but something like
You've just described
On 21-11-20, 19:41, Bjorn Andersson wrote:
> From: Stephen Boyd
>
> The SMMU that sits in front of the QUP needs to be programmed properly
> so that the i2c geni driver can allocate DMA descriptors. Failure to do
> this leads to faults when using devices such as an i2c touchscreen where
> the
defer_compaction() and compaction_deferred() and
compaction_restarting() in mm/compaction.c won't
be used in other files, so make them static, and
remove the declaration in the header file.
Take the chance to fix a typo.
Signed-off-by: Hui Su
---
include/linux/compaction.h | 12
From: Jordan Crouse
GPU targets with an MMU-500 attached have a slightly different process for
enabling system cache. Use the compatible string on the IOMMU phandle
to see if an MMU-500 is attached and modify the programming sequence
accordingly.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 9 +
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
Acked-by: Will Deacon
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
Now that we have a struct io_pgtable_domain_attr with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 8 +++-
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire
From: Sharat Masetty
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
Signed-off-by: Sai
On Thu, Nov 19, 2020 at 09:42:05PM +, Ashish Kalra wrote:
> From: Ashish Kalra
>
> For SEV, all DMA to and from guest has to use shared (un-encrypted) pages.
> SEV uses SWIOTLB to make this happen without requiring changes to device
> drivers. However, depending on workload being run, the
On 11/20/20 3:14 PM, Eric W. Biederman wrote:
When discussing[1] exec and posix file locks it was realized that none
of the callers of get_files_struct fundamentally needed to call
get_files_struct, and that by switching them to helper functions
instead it will both simplify their code and
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the outer-cacheability attributes set in the TCR for a
non-coherent page table walker when using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 10 --
include/linux/io-pgtable.h | 4
Add iommu domain attribute for pagetable configuration which
initially will be used to set quirks like for system cache aka
last level cache to be used by client drivers like GPU to set
right attributes for caching the hardware pagetables into the
system cache and later can be extended to include
On Mon, Nov 23, 2020 at 4:32 PM Heikki Krogerus
wrote:
>
> Hi,
>
> I originally introduced these as part of my series where I was
> proposing PM ops for software nodes [1], but since that still needs
> work, I'm sending these two separately.
>
> So basically I'm only modifying dwc3-pci.c so it
Hi Boris
> -Original Message-
> From: Borislav Petkov
> Sent: Monday, November 23, 2020 3:28 PM
> To: Paoloni, Gabriele
> Cc: Luck, Tony ; t...@linutronix.de;
> mi...@redhat.com; x...@kernel.org; h...@zytor.com; linux-
> e...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache to cache
both the GPU data buffers(like textures) as well the SMMU pagetables.
This helps with improved render
On 11/22/20 10:22 AM, Joe Perches wrote:
> On Sun, 2020-11-22 at 08:33 -0800, Tom Rix wrote:
>> On 11/21/20 9:10 AM, Joe Perches wrote:
>>> On Sat, 2020-11-21 at 08:50 -0800, t...@redhat.com wrote:
A difficult part of automating commits is composing the subsystem
preamble in the commit
From: Sahitya Tummala
> Sent: 23 November 2020 05:29
>
> Use rwsem to ensure serialization of the callers and to avoid
> starvation of high priority tasks, when the system is under
> heavy IO workload.
I can't see any read lock requests.
So why the change?
David
-
Registered Address
On Sat, 14 Nov 2020 00:47:22 +0100
Halil Pasic wrote:
> On Fri, 13 Nov 2020 12:14:22 -0500
> Tony Krowiak wrote:
> [..]
> > >> }
> > >>
> > >> +#define MDEV_SHARING_ERR "Userspace may not re-assign queue %02lx.%04lx
> > >> " \
> > >> + "already assigned to %s"
> >
On Mon, 16 Nov 2020 20:43:13 +,
David Brazdil wrote:
>
> Add a handler of the CPU_ON PSCI call from host. When invoked, it looks
> up the logical CPU ID corresponding to the provided MPIDR and populates
> the state struct of the target CPU with the provided x0, pc. It then
> calls CPU_ON
On Fri, Nov 20, 2020 at 12:12 PM Flavio Suligoi wrote:
>
> For "fixed" PCI devices, such as chips directly soldered
> on the main board (ethernet, Wi-Fi, serial ports, etc.),
> it is possible to find an ACPI enumeration.
>
> This allows to add useful properties to these devices.
> Just for an
USBPHYC has a register per phy to control and monitor the debug interface
of the HS PHY through a digital debug access.
With this register, it is possible to know if PLL Lock input to phy is
high. That means the PLL is ready for HS operation.
Instead of using an hard-coded delay after PLL enable
On 2020-11-23 20:51, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:39PM +0530, Sai Prakash Ranjan wrote:
Some hardware variants contain a system cache or the last level
cache(llc). This cache is typically a large block which is shared
by multiple clients on the SOC. GPU uses the system cache
PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE
signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers
To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.
Signed-off-by: Amelie Delaunay
---
To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 6 ++
1 file changed, 6 insertions(+)
diff
PLL block requires to be powered with 1v1 and 1v8 supplies to catch
ENABLE signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers
Due to async_schedule_domain call in regulator_bulk_enable,
scheduling while atomic bug can raise if regulator_bulk_enable is called
under atomic context.
To avoid this issue, this patch replaces all regulator_bulk* by regulator_
per regulators.
Signed-off-by: Amelie Delaunay
---
STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8
supplies. To ensure a good behavior of the PLL, during boot, runtime and
suspend/resume sequences, this series reworks its management to fix regulators
issues and improve PLL status reliability.
Amelie Delaunay (6):
On Mon, Nov 23, 2020 at 4:37 AM Masahiro Yamada wrote:
>
> I can move it to compiler_attribute.h
>
> This attribute is supported by gcc, clang, and icc.
> https://godbolt.org/z/ehd6so
>
> I can send v2.
>
> I do not mind renaming, but it should be done in a separate patch.
Of course -- sorry, I
On Mon, Nov 23, 2020 at 05:51:08PM +0800, Alice Guo wrote:
> Directly reading ocotp register depends on that bootloader enables ocotp
> clk, which is not always effective, so change to use nvmem API. Using
> nvmem API requires to support driver defer probe and thus change
> soc-imx8m.c to use
On Mon, Nov 23, 2020 at 05:51:05PM +0800, Alice Guo wrote:
> Add DT Binding doc for the Unique ID of i.MX 8M series.
>
> Signed-off-by: Alice Guo
> ---
>
> v2: remove the subject prefix "LF-2571-1"
> v3: put it into Documentation/devicetree/bindings/arm/fsl.yaml
> modify the description of
On Mon, Nov 23, 2020 at 05:51:07PM +0800, Alice Guo wrote:
> In order to be able to use NVMEM APIs to read soc unique ID, add the
> nvmem data cell and name for nvmem-cells to the "soc" node, and add a
> nvmem node which provides soc unique ID to efuse@3035.
>
> Signed-off-by: Alice Guo
>
Hi John,
Thanks for the patch.
On 11/21/2020 12:03 PM, John Stultz wrote:
The kernel test robot reported the following build error:
All errors (new ones prefixed by >>):
xtensa-linux-ld: drivers/regulator/qcom-rpmh-regulator.o: in function
`rpmh_regulator_vrm_get_voltage_sel':
On Mon, Nov 23, 2020 at 05:51:06PM +0800, Alice Guo wrote:
> Add compatible string to .dtsi files for binding of imx8_soc_info and
> device.
>
> v2: remove the subject prefix "LF-2571-2"
> v3: none
> v4: change subject and commit message, add Reviewed-by
You have here duplicated changelog. Leave
On 11/17/20 11:07 AM, Tom Lendacky wrote:
From: Tom Lendacky
This patch series provides support for running SEV-ES guests under KVM.
Any comments on this series?
Thanks,
Tom
Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the
SEV support to protect the guest
On Mon, 2020-11-23 at 16:10 +, David Howells wrote:
> Joe Perches wrote:
>
> > > call->unmarshall++;
> > > +
> > > + fallthrough;
> >
> > My preference would be to change these to break and not fallthrough;
> >
> > > case 5:
> > > break;
> > > }
>
> My
On Mon, Nov 23, 2020 at 09:47:53PM +0530, Srinivasa Rao Mandadapu wrote:
> Fix enabling BCLK and LRCLK only when LPAIF is invalid state and
> bit clock in enable state.
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify
On Fri, Nov 20, 2020 at 09:20:43AM -0800, Linus Torvalds wrote:
> On Fri, Nov 20, 2020 at 6:36 AM Will Deacon wrote:
> >
> > tlb_finish_mmu() takes two confusing and unused 'start'/'end' address
> > arguments. Remove them.
>
> Ack, but please add the history to it.
>
> Those arguments were
On Fri, Nov 20, 2020 at 09:31:09AM -0800, Linus Torvalds wrote:
> Oh - wait.
>
> Not ack.
>
> Not because this is wrong, but because I think you should remove the
> start/end arguments here too.
>
> The _only_ thing they were used for was that "fullmm" flag, afaik. So
> now they no longer make
From: Ioana Ciornei
Because the minimum supported DPRC version is 6.0, there is no need to
check for incompatible 6.x versions lower to the minimum one. Just
remove the second half of the check to simplify the logic.
Signed-off-by: Ioana Ciornei
---
drivers/bus/fsl-mc/dprc-driver.c | 4 +---
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: d001e41e1b15716e9b759df5ef00510699f85282
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/d001e41e1b15716e9b759df5ef00510699f85282
Author:Chen Baozi
On Tue 03-11-20 22:17:47, Paweł Jasiak wrote:
> I have written small patch that fixes problem for me and doesn't break
> x86_64.
OK, with a help of Boris Petkov I think I have a fix that looks correct
(attach). Can you please try whether it works for you? Thanks!
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: 74cde1a53368aed4f2b4b54bf7030437f64a534b
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/74cde1a53368aed4f2b4b54bf7030437f64a534b
Author:Xu Qiang
On Mon, Nov 23, 2020 at 04:43:30PM +, Mark Brown wrote:
> On Mon, Nov 23, 2020 at 03:58:31PM +0100, Krzysztof Kozlowski wrote:
>
> > Having these of_match_ptr() for OF-only drivers is not the correct way
> > but rather something which is copied from existing drivers into new
> > ones. This is
On Mon, Nov 23, 2020 at 03:58:31PM +0100, Krzysztof Kozlowski wrote:
> Having these of_match_ptr() for OF-only drivers is not the correct way
> but rather something which is copied from existing drivers into new
> ones. This is another reason for removing them - people will stop
> copying this
On 2020-11-23 20:49, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:42PM +0530, Sai Prakash Ranjan wrote:
Now that we have a struct domain_attr_io_pgtbl_cfg with quirks,
use that for non_strict mode as well thereby removing the need
for more members of arm_smmu_domain in the future.
On Mon, 2020-11-23 at 14:53 +, Luis Henriques wrote:
> Add a new vxattr that allows userspace to list the caps for a specific
> directory or file.
>
> Signed-off-by: Luis Henriques
> ---
> fs/ceph/xattr.c | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git
On Mon, 23 Nov 2020 16:20:08 +, Cristian Marussi wrote:
> For sake of consistency, remove any residual naming based on _le suffixes
> in SCMI Sensors Protocol, since little endianity is already assumed across
> all of SCMI implementation and, as such, all currently existent names do
> not
On 2020-11-23 20:48, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:41PM +0530, Sai Prakash Ranjan wrote:
Add iommu domain attribute for pagetable configuration which
initially will be used to set quirks like for system cache aka
last level cache to be used by client drivers like GPU to set
On 2020-11-23 20:36, Will Deacon wrote:
On Tue, Nov 17, 2020 at 08:00:40PM +0530, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override
the attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
The pca9685 driver supports a new staggered-outputs property for reduced
current surges and EMI. This adds documentation for the new DT property.
Signed-off-by: Clemens Gruber
---
Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi Philippe,
Some additional feedback:
The patch title could be changed to:
"tracing: Remove duplicate `type` field from regmap `regcache_sync` trace event"
to clarify that this belongs to tracing.
- On Nov 23, 2020, at 11:15 AM, Philippe Duplessis-Guindon
pduples...@efficios.com wrote:
This adds the MIPI DSI Host Pixel Clock bindings.
Signed-off-by: Neil Armstrong
---
include/dt-bindings/clock/g12a-clkc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/g12a-clkc.h
b/include/dt-bindings/clock/g12a-clkc.h
index 40d49940d8a8..a93b58c5e18e 100644
This serie adss the MIPI DSI Host Pixel Clock used to feed the DSI pixel
clock to the DSI Host controller.
Unlike the AXG SoC, the DSI Pixel Clock has a supplementary mux, divider and
gate
stage before feeding the pixel clock to the MIPI DSI Host controller.
Neil Armstrong (2):
dt-bindings:
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be
different
from the VPU ENCL output clock to feed the DSI Host controller with a different
clock rate.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.c | 72
On Mon, Nov 23, 2020 at 05:41:30PM +0200, Georgi Djakov wrote:
> Hello Greg,
>
> Here is a pull request with a few interconnect fixes for 5.10-rc.
> Please take them into char-misc-linus when possible. All patches
> have been reviewed and tested. They have been also in linux-next
> since last
On 11/23/20 2:55 AM, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:27bba9c5 Merge tag 'scsi-fixes' of git://git.kernel.org/pu..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=11041f1e50
> kernel config:
The PCA9685 supports staggered LED output ON times to minimize current
surges and reduce EMI.
When this new option is enabled, the ON times of each channel are
delayed by channel number x counter range / 16, which avoids asserting
all enabled outputs at the same counter value while still
On Mon, 23 Nov 2020 11:28:12 -0500
Steven Rostedt wrote:
> I noticed:
>
>
> [ 237.650900] enabling event benchmark_event
>
> In both traces. Could you disable CONFIG_TRACEPOINT_BENCHMARK and see if
> the issue goes away. That event kicks off a thread that spins in a tight
> loop for some
This switch to the atomic API goes hand in hand with a few fixes to
previously experienced issues:
- The duty cycle is no longer lost after disable/enable (previously the
OFF registers were cleared in disable and the user was required to
call config to restore the duty cycle settings)
- The
The full OFF bits are set by default in the PCA9685 LEDn_OFF_H
registers at POR. LEDn_ON_L/H and LEDn_OFF_L default to 0.
The datasheet states that LEDn_OFF and LEDn_ON should never be both set
to the same values.
This patch removes the clearing of the full OFF bit in the probe
function. We
> I fixed the first sentence:
>
> Follow-up to a73619a845d5 ("kbuild: use -fmacro-prefix-map to make
> __FILE__ a relative path") commit.
>
> to
>
> Follow-up to commit a73619a845d5 ("kbuild: use -fmacro-prefix-map to
> make __FILE__ a relative path").
ok, i see
> > Assembler sources also use
On Mon, 2020-11-23 at 07:58 -0800, James Bottomley wrote:
> We're also complaining about the inability to recruit maintainers:
>
> https://www.theregister.com/2020/06/30/hard_to_find_linux_maintainers_says_torvalds/
>
> And burn out:
>
> http://antirez.com/news/129
On Mon, 2020-11-23 at 07:03 -0600, Gustavo A. R. Silva wrote:
> On Sun, Nov 22, 2020 at 11:53:55AM -0800, James Bottomley wrote:
> > On Sun, 2020-11-22 at 11:22 -0800, Joe Perches wrote:
> > > On Sun, 2020-11-22 at 11:12 -0800, James Bottomley wrote:
> > > > On Sun, 2020-11-22 at 10:25 -0800, Joe
> Makes sense, as this means no userspace change.
>
> > 2. Add an internal move_pages_zone() similar to move_pages() syscall
> > but instead of migrating to a different NUMA node, migrate pages from
> > ZONE_MOVABLE to another zone.
> > Call move_pages_zone() on demand prior to pinning pages from
> [...]
> >> >> +static int get_gpio_pin_state(struct irq_desc *irq_desc)
> >> >> +{
> >> >> + struct gpio_chip *gc =
> >> >> irq_data_get_irq_chip_data(_desc->irq_data);
> >> >> +
> >> >> + return gc->get(gc, irq_desc->irq_data.hwirq);
> >> >> +}
> >> [...]
> >> >> + ssize_t
Hi Vinod,
Thanks for your valuable review. My comments inline.
On 11/21/2020 8:19 PM, Vinod Koul wrote:
On 20-11-20, 19:30, Reddy, MallikarjunaX wrote:
Hi Vinod,
Thanks for the review. My comments inline.
On 11/18/2020 11:55 PM, Vinod Koul wrote:
On 12-11-20, 13:38, Amireddy Mallikarjuna
On Thu, Nov 19, 2020 at 12:52:44PM -0700, Nathan Chancellor wrote:
> Clang warns:
>
> drivers/memory/tegra/tegra30-emc.c:1275:15: warning: variable 'np' is
> uninitialized when used here [-Wuninitialized]
> of_node_put(np);
> ^~
>
Hi Vinod,
Thanks for your valuable review comments. Please see my comments inline.
On 11/21/2020 8:17 PM, Vinod Koul wrote:
On 20-11-20, 19:30, Reddy, MallikarjunaX wrote:
Hi Vinod,
Thanks for the review. My comments inline.
On 11/19/2020 1:38 AM, Vinod Koul wrote:
On 12-11-20, 13:38,
On Mon, 23 Nov 2020 16:27:20 +0100
Marco Elver wrote:
> On Fri, Nov 20, 2020 at 02:27PM -0500, Steven Rostedt wrote:
> > On Thu, 19 Nov 2020 13:53:57 +0100
> > Marco Elver wrote:
> >
> > > Running tests again, along with the function tracer
> > > Running tests on all trace events:
> > >
On Mon, Nov 23, 2020 at 4:58 PM James Bottomley
wrote:
>
> On Mon, 2020-11-23 at 15:19 +0100, Miguel Ojeda wrote:
> > On Sun, Nov 22, 2020 at 11:36 PM James Bottomley
> > wrote:
[cut]
> >
> > Maintainers routinely review 1-line trivial patches, not to mention
> > internal API changes, etc.
>
>
GPIOs - as returned by of_get_named_gpio() and used by the gpiolib - are
signed integers, where negative number indicates error. The return
value of of_get_named_gpio() should not be assigned to an unsigned int
because in case of !CONFIG_GPIOLIB such number would be a valid GPIO.
Fixes:
I had an error saying that `regcache_sync` had 2 fields named `type` while using
libtraceevent. This was the format of this event:
$ sudo cat /sys/kernel/debug/tracing/events/regmap/regcache_sync/format
name: regcache_sync
ID: 1216
format:
Dear RT Folks,
I'm pleased to announce the 5.4.78-rt44 stable release.
This release is just an update to the new stable 5.4.78 version
and no RT specific changes have been made.
You can get this release via the git tree at:
For sake of consistency, remove any residual naming based on _le suffixes
in SCMI Sensors Protocol, since little endianity is already assumed across
all of SCMI implementation and, as such, all currently existent names do
not explicitly state their endianness.
No functional change.
Fix enabling BCLK and LRCLK only when LPAIF is invalid state and
bit clock in enable state.
In device suspend/resume scenario LPAIF is going to reset state.
which is causing LRCLK disable and BCLK enable.
Avoid such inconsitency by removing unnecessary cpu dai prepare API,
which is doing LRCLK
On Mon, Nov 23, 2020 at 4:52 PM Jani Nikula wrote:
>
> On Sat, 21 Nov 2020, James Bottomley
> wrote:
> > On Sat, 2020-11-21 at 08:50 -0800, t...@redhat.com wrote:
> >> A difficult part of automating commits is composing the subsystem
> >> preamble in the commit log. For the ongoing effort of a
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