On Fri, Jan 08, 2021 at 07:17:10PM +0800, zhenwei pi wrote:
> According to pvpanic spec:
> https://git.qemu.org/?p=qemu.git;a=blob_plain;f=docs/specs/pvpanic.txt
>
> The guest should determine pvpanic capability by RDPT, so initialize
> capability during device probing. There is no need to
The code that acquires the version strings for libc and libcpp is
identical, as is the printversion call. The only difference being the
name of the library being printed.
Refactor the code by unifying the bits that are common to both libraries.
Signed-off-by: Alexander Kapshuk
---
On Fri, Jan 08, 2021 at 07:17:10PM +0800, zhenwei pi wrote:
> According to pvpanic spec:
> https://git.qemu.org/?p=qemu.git;a=blob_plain;f=docs/specs/pvpanic.txt
>
> The guest should determine pvpanic capability by RDPT, so initialize
> capability during device probing. There is no need to
Standard DRM panel driver for DSI command mode panel used by omapfb2 is also
available now. Just like the other panels its module name clashes with the
module from drivers/video/fbdev/omap2/omapfb/displays, part of the deprecated
omapfb2 fbdev driver. As omapfb2 can only be compiled when the
Drop semicolons after function definitions that have managed to sneak in
and get reproduced.
Signed-off-by: Johan Hovold
---
drivers/gnss/mtk.c| 2 +-
drivers/gnss/serial.c | 2 +-
drivers/gnss/sirf.c | 2 +-
drivers/gnss/ubx.c| 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
On 2021-01-08 10:32:36 [+0100], Peter Zijlstra wrote:
> It's a single task wakeup (the caller), doing that from hardirq context
> really should not be a problem, we do lots of that in RT already.
I'm not worry about that single wakeup but about an artificial case
where you manage to accumulate
Every time I have stumbled upon this routine, I get confused with the
way 'have_policy' is used and I have to dig in to understand why is it
so. Here is an attempt to make it easier to understand, and hopefully it
is an improvement.
The 'have_policy' check was just an optimization to avoid
According to pvpanic spec:
https://git.qemu.org/?p=qemu.git;a=blob_plain;f=docs/specs/pvpanic.txt
The guest should determine pvpanic capability by RDPT, so initialize
capability during device probing. There is no need to register panic
notifier callback function if no events supported.
Before
The AMU counters won't get used today if the cpufreq driver is built as
a module as the amu core requires everything to be ready by late init.
Fix that properly by registering for cpufreq policy notifier. Note that
the amu core don't have any cpufreq dependency after the first time
This patch does a couple of optimizations in init_amu_fie(), like early
exits from paths where we don't need to continue any further, avoid the
enable/disable dance, moving the calls to
topology_scale_freq_invariant() just when we need them, instead of at
the top of the routine, and avoiding
Hi,
Here is the V4 with the general improvements for topology stuff. This
cleans up the code and makes it work with cpufreq modules.
V4:
- Added Rby from Ionela.
- In 3/3, Print cpus instead of amu_fie_cpus and make it pr_debug
instead.
Viresh Kumar (3):
arm64: topology: Avoid the
On Mon, Jan 04, 2021 at 04:30:11PM +0100, Konrad Dybcio wrote:
> Hi,
>
> could you explicitly state in the probe function (or just in the driver in
> general, as there's not much more?) and the config structs that the target
> SoC is X55?
>
The compatible says it...
> A few more SoCs
From: Christoph Hellwig
> Sent: 21 September 2020 15:22
>
> So looking at the various callers I'm not sure this API is the
> best. If we want to do something fancy I'd hide the struct iovec
> instances entirely with something like:
>
> struct iov_storage {
> struct iovec
There appears to be a regression with the filesystem NLS modules. I cannot load
any of them. They all produce:
modprobe: ERROR: could not insert 'nls_cp437': Invalid argument
The system journal reports:
Jan 08 02:04:56 mrgency kernel: BPF:No data
Jan 08 02:04:56 mrgency kernel: failed to
The following commit has been merged into the x86/asm branch of tip:
Commit-ID: 5c99720b28381bb400d4f546734c34ddaf608761
Gitweb:
https://git.kernel.org/tip/5c99720b28381bb400d4f546734c34ddaf608761
Author:Dave Jiang
AuthorDate:Thu, 07 Jan 2021 09:45:21 -07:00
Committer:
The following commit has been merged into the x86/asm branch of tip:
Commit-ID: 6ae58d871319dc22ef780baaacd393f8543a1e74
Gitweb:
https://git.kernel.org/tip/6ae58d871319dc22ef780baaacd393f8543a1e74
Author:Dave Jiang
AuthorDate:Thu, 07 Jan 2021 09:44:51 -07:00
Committer:
On Fri, 2021-01-08 at 10:53 +, Lee Jones wrote:
> On Fri, 08 Jan 2021, Zheng Yongjun wrote:
>
> You're still not using the correct subject format.
>
> It should be:
>
> "mfd: : Description starting with an uppercase char"
IMO: overly pedantic
I would like to help with slab allocators maintenance, from the perspective of
being responsible for SLAB and more recently also SLUB in an enterprise distro
kernel and supporting its users. Recently I've been focusing on improving
SLUB's debugging features, and patch review in the area, including
Hi Peter,
On 08/01/21 4:16 pm, Peter Rosin wrote:
> Hi!
>
> On 2020-12-24 12:42, Kishon Vijay Abraham I wrote:
>> AM64 has a single lane SERDES which can be configured to be used
>> with either PCIe or USB. Define the possilbe values for the SERDES
>> function in AM64 SoC here.
>>
>>
On 08-01-21, 09:44, Ionela Voinescu wrote:
> Now that I think of it again (after spending 30 minutes trying to come
> up with a more clear solution) I realised this is not actually a
> problem :).
>
> The only location that checks the invariance status is schedutil, but
> what a cpufreq governor
Hi Rob,
On 08/01/21 8:33 am, Rob Herring wrote:
> On Thu, Dec 24, 2020 at 05:12:47PM +0530, Kishon Vijay Abraham I wrote:
>> AM64 has a single lane SERDES which can be configured to be used
>> with either PCIe or USB. Define the possilbe values for the SERDES
>> function in AM64 SoC here.
>
>
Hello, Greg.
On 07/01/21 13:39, Greg KH wrote:
My point is, do NOT have different file names. Userspace should not
care about the backing transport layer of a device.
Regarding sound cards and such -- we agree perfectly. For a driver like
XillyUSB, it's not necessarily clear what is
As per specs, e.g, JESD220E chapter 7.2, while powering
off/on the ufs device, REF_CLK signal should be between
VSS(Ground) and VCCQ/VCCQ2.
Reviewed-by: Can Guo
Signed-off-by: Ziqi Chen
---
drivers/scsi/ufs/ufshcd.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
As per specs, e.g, JESD220E chapter 7.2, while powering
off/on the ufs device, RST_n signal should be between
VSS(Ground) and VCCQ/VCCQ2.
Signed-off-by: Ziqi Chen
---
drivers/scsi/ufs/ufs-qcom.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/x86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 0287840b93e0..a480804ae27a 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -7976,7 +7976,7 @@ void kvm_arch_exit(void)
On 08/01/2021 08:00, Sameer Pujar wrote:
...
Signed-off-by: Peter Geis
Tested-by: Ion Agorria
---
sound/pci/hda/hda_tegra.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c
Unlike most other architectures, MIPS defines ffz() below ffs().
Signed-off-by: Geert Uytterhoeven
---
arch/mips/include/asm/bitops.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index
The generic definition of ffz() is not defined in the same header files
as the generic definitions of ffs().
Signed-off-by: Geert Uytterhoeven
---
include/asm-generic/bitops/builtin-ffs.h | 2 +-
include/asm-generic/bitops/ffs.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Fix a misspelling of "synonym".
Signed-off-by: Geert Uytterhoeven
---
include/linux/bitops.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index a61f192c096b3ac6..a5a48303b0f111ee 100644
--- a/include/linux/bitops.h
+++
On Fri, 08 Jan 2021, Zheng Yongjun wrote:
You're still not using the correct subject format.
It should be:
"mfd: : Description starting with an uppercase char"
Code looks fine.
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
> ---
>
On Fri, Jan 8, 2021 at 2:34 PM Chunfeng Yun wrote:
>
> On Tue, 2020-12-29 at 14:24 +0800, Ikjoon Jang wrote:
> > xhci-mtk has hooks on add_endpoint() and drop_endpoint() from xhci
> > to handle its own sw bandwidth managements and stores bandwidth data
> > into internal table every time
Am Freitag, 8. Januar 2021, 11:48:26 CET schrieb Heiko Stübner:
> Am Freitag, 8. Januar 2021, 10:05:16 CET schrieb Paul Kocialkowski:
> > Hi Ezequiel,
> >
> > On Thu 07 Jan 21, 16:08, Ezequiel Garcia wrote:
> > > Happy to see this patch. It was on my TODO list,
> > > but I hadn't had time to
Am Freitag, 8. Januar 2021, 10:05:16 CET schrieb Paul Kocialkowski:
> Hi Ezequiel,
>
> On Thu 07 Jan 21, 16:08, Ezequiel Garcia wrote:
> > Happy to see this patch. It was on my TODO list,
> > but I hadn't had time to bringup my rk3326 device.
>
> Same here, I just had an occasion to use it again
From: Peter Zijlstra
> Sent: 08 January 2021 09:52
>
> On Fri, Jan 08, 2021 at 09:37:45AM +, David Laight wrote:
> > The lack of spinlocks in userspace really kills you.
>
> Glibc has them, but please don't complain about lock holder preemption
> issues if you do actually use them ;-)
Hi Robert and Tomasz,
On 08.01.2021 12:49, Tomasz Figa wrote:
Hi Robert,
On Thu, Jan 7, 2021 at 11:21 PM Robert Foss wrote:
The Bayer GRBG10 mode used for earlier modes 3280x2460 and
1640x1232 isn't the mode output by the sensor for the
3264x2448 and 1632x1224 modes.
Switch from
Hi!
On 2020-12-24 12:42, Kishon Vijay Abraham I wrote:
> AM64 has a single lane SERDES which can be configured to be used
> with either PCIe or USB. Define the possilbe values for the SERDES
> function in AM64 SoC here.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
>
Hi Andrey,
On 1/7/21 7:18 PM, Andrey Konovalov wrote:
>> Boolean arguments are generally bad for legibility, hence I tend to avoid
>> them.
>> In this case exposing the constants does not seem a big issue especially
>> because
>> the only user of this code is "KASAN_HW_TAGS" and definitely
On Friday 08 Jan 2021 at 09:44:16 (+), Ionela Voinescu wrote:
> On Thursday 17 Dec 2020 at 16:20:49 (+0530), Viresh Kumar wrote:
> > On 16-12-20, 19:37, Ionela Voinescu wrote:
> > > I did not yet test this, but reading this comment made me wonder..
> > >
> > > arch_scale_freq_invariant() (or
Based on the drm_connector_mode_valid, if the hibmc implementation
of mode_valid only returns MODE_OK, then we can not implement the
mode_valid function.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 7 ---
1 file changed, 7 deletions(-)
diff --git
The A10s/A13 mali gpu was not defined in device tree
Add A10 mali gpu as a fallback for A10s/A13
Tested with Olimex-A13-SOM / Olimex-A13-OlinuXino-MICRO
"kmscube" 3d cube on screen (60fps / 10%cpu)
Versions: Lima:1.1.0 EGL:1.4 OpenGLES:2.0 Mesa:20.2.2
Signed-off-by: Sergio Sota
---
Changes in
Hi Arseny,
On Sun, Jan 03, 2021 at 10:54:52PM +0300, Arseny Krasnov wrote:
As SOCK_SEQPACKET guarantees to save record boundaries, so to
do it, new packet operation was added: it marks start of record (with
record length in header). To send record, packet with start marker is
sent
On Mon, 21 Dec 2020 at 21:53, Lecopzer Chen wrote:
>
> commit 367c820ef08082 ("arm64: Enable perf events based hard lockup detector")
> reinitilizes lockup detector after arm64 PMU is initialized and open
> a window for accessing smp_processor_id() in preemptible context.
> Since
On 1/7/21 3:44 PM, Willem de Bruijn wrote:
On Thu, Jan 7, 2021 at 8:33 AM Daniel Borkmann wrote:
On 1/7/21 2:05 PM, Willem de Bruijn wrote:
On Thu, Jan 7, 2021 at 7:52 AM Daniel Borkmann wrote:
On 1/7/21 12:40 PM, Dongseok Yi wrote:
On 2021-01-07 20:05, Daniel Borkmann wrote:
On 1/7/21
On Thu, Jan 07, 2021 at 04:05:48PM -0500, Jon Masters wrote:
> Hi will, everyone,
>
> On 1/7/21 1:14 PM, Will Deacon wrote:
>
> > On Mon, Jan 04, 2021 at 10:57:35PM -0600, Jeremy Linton wrote:
> > > Given that most arm64 platform's PCI implementations needs quirks
> > > to deal with problematic
Hi!
> > > The gcc bugzilla mentions backports into gcc-linaro, but I do not see
> > > them in my git history.
> >
> > So, do we raise the minimum gcc version for the kernel as a whole to 5.1
> > or just for aarch64?
>
> Russell, Arnd, thanks so much for tracking down the root cause of the
>
On Tue, Dec 15, 2020 at 08:59:11AM +0100, Peter Zijlstra wrote:
> On Tue, Dec 15, 2020 at 11:36:35AM +0800, Li, Aubrey wrote:
> > On 2020/12/15 0:48, Peter Zijlstra wrote:
> > > We compute the average cost of the total scan, but then use it as a
> > > per-cpu scan cost when computing the scan
On Fri, Jan 8, 2021 at 10:33 AM Will Deacon wrote:
> On Fri, Jan 08, 2021 at 10:19:56AM +0100, Arnd Bergmann wrote:
> > From: Arnd Bergmann
> >
> > With UBSAN enabled and building with clang, there are occasionally
> > warnings like
> >
> > WARNING: modpost: vmlinux.o(.text+0xc533ec): Section
On 01/08/21 at 10:07am, HAGIO KAZUHITO(萩尾 一仁) wrote:
> Hi Baoquan,
>
> -Original Message-
> > On 09/30/20 at 12:23pm, Alexander Egorenkov wrote:
> > > The offset of the field 'init_uts_ns.name' has changed
> > > since commit 9a56493f6942 ("uts: Use generic ns_common::count").
> >
> >
On Sun, Jan 03, 2021 at 10:57:50PM +0300, Arseny Krasnov wrote:
This extends rx loop for SOCK_SEQPACKET packets and implements
callback which user calls to copy data to its buffer.
Please write a better commit message explaining the changes, e.g. that
you are using 'flags' to
On 1/8/21 3:28 AM, Dongseok Yi wrote:
skbs in fraglist could be shared by a BPF filter loaded at TC. If TC
writes, it will call skb_ensure_writable -> pskb_expand_head to create
a private linear section for the head_skb. And then call
skb_clone_fraglist -> skb_get on each skb in the fraglist.
On Fri, 2021-01-08 at 10:03 +0100, Daniel Vetter wrote:
> On Fri, Jan 8, 2021 at 9:55 AM Randy Dunlap wrote:
> > On 1/6/21 7:01 PM, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > Changes since 20210106:
> > >
> >
> > on x86_64:
> >
> > ld: drivers/gpu/drm/imx/parallel-display.o: in
On Fri, Jan 08, 2021 at 09:52:02AM +0100, Oscar Salvador wrote:
> Format %pG expects a lower case 'p' in order to print the flags.
> Fix it.
>
> Reported-by: Dan Carpenter
> Signed-off-by: Oscar Salvador
> Fixes: 8295d535e2aa ("mm,hwpoison: refactor get_any_page")
Thank you!
Acked-by: Naoya
On 08 January 2021 08:53, Xu Wang wrote:
> Because clk_prepare_enable() and clk_disable_unprepare() already checked
> NULL clock parameter, so the additional checks are unnecessary, just
> remove them.
>
> Signed-off-by: Xu Wang
> ---
> sound/soc/codecs/da7218.c | 13 +
>
On Fri, Jan 8, 2021 at 5:31 PM Michal Hocko wrote:
>
> On Fri 08-01-21 17:01:03, Muchun Song wrote:
> > On Fri, Jan 8, 2021 at 4:43 PM Michal Hocko wrote:
> > >
> > > On Thu 07-01-21 23:11:22, Muchun Song wrote:
> [..]
> > > > But I find a tricky problem to solve. See free_huge_page().
> > > >
Hi Baoquan,
-Original Message-
> On 09/30/20 at 12:23pm, Alexander Egorenkov wrote:
> > The offset of the field 'init_uts_ns.name' has changed
> > since commit 9a56493f6942 ("uts: Use generic ns_common::count").
>
> This patch is merged into 5.11-rc1, but we met the makedumpfile failure
From: Joe Perches
> Sent: 08 January 2021 00:52
...
> > The original goal was to use another helper that worked on static
> > strings like this. Linus rejected that idea, so we're in a weird place.
> > I think we could perhaps build a strcpy() replacement that requires
> > compile-time validated
> > The use of 'goto' is not needed here IMHO. I think:
...
> In context to the previous comment [1], I have implemented this way.
> But, yeah anything is fine for me.
Thanks, I really think it is better.
> In geni_i2c_abort_xfer() function gi2c->cur will be made NULL, so copying it
> before to
On 2021/1/8 17:21, Michal Hocko wrote:
On Fri 08-01-21 10:33:39, Xiaoming Ni wrote:
The process_sysctl_arg() does not check whether val is empty before
invoking strlen(val). If the command line parameter () is incorrectly
configured and val is empty, oops is triggered.
For example,
On Wed, Dec 23, 2020 at 9:04 PM Helen Koike wrote:
>
> Hi Tomasz,
>
> On 12/21/20 12:13 AM, Tomasz Figa wrote:
> > On Thu, Dec 17, 2020 at 10:20 PM Helen Koike
> > wrote:
> >>
> >> Hi Tomasz,
> >>
> >> Thanks for your comments, I have a few questions below.
> >>
> >> On 12/16/20 12:13 AM,
MSFT ActiveSync implementation requires that the size of the response for
incoming query is to be provided in the request input length. Failure to
set the input size proper results in failed request transfer, where the
ActiveSync counterpart reports the NDIS_STATUS_INVALID_LENGTH (0xC0010014L)
On Wed, Dec 23, 2020 at 8:00 PM Robin Murphy wrote:
>
> On 2020-12-23 08:56, Tomasz Figa wrote:
> > On Wed, Dec 16, 2020 at 06:36:06PM +0800, Yong Wu wrote:
> >> In current iommu_unmap, this code is:
> >>
> >> iommu_iotlb_gather_init(_gather);
> >> ret = __iommu_unmap(domain, iova,
Hi Wolfram,
On 2021-01-05 20:57, Wolfram Sang wrote:
+ geni_status = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
+ if (!(geni_status & M_GENI_CMD_ACTIVE))
+ goto out;
+
+ cur = gi2c->cur;
+ geni_i2c_abort_xfer(gi2c);
+ if (cur->flags & I2C_M_RD)
+
On Thu, Dec 31, 2020 at 03:29:38PM +0100, Paul Kocialkowski wrote:
> Bits related to the interface data width are only applicable to the
> parallel interface and are irrelevant when the CSI controller is taking
> input from the MIPI CSI-2 controller.
>
> In prevision of adding support for this
Hi,
On Thu, Dec 31, 2020 at 03:29:46PM +0100, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering
> both the protocol logic and the D-PHY implementation. This controller
> seems to be found on the A83T only and probably was abandoned since.
>
> This
On Wed, Dec 23, 2020 at 8:00 PM Robin Murphy wrote:
>
> On 2020-12-23 08:56, Tomasz Figa wrote:
> > On Wed, Dec 16, 2020 at 06:36:06PM +0800, Yong Wu wrote:
> >> In current iommu_unmap, this code is:
> >>
> >> iommu_iotlb_gather_init(_gather);
> >> ret = __iommu_unmap(domain, iova,
On Thu, Dec 31, 2020 at 12:55:54AM +0800, Shiyang Ruan wrote:
> Memory failure occurs in fsdax mode will finally be handled in
> filesystem. We introduce this interface to find out files or metadata
> affected by the corrupted range, and try to recover the corrupted data
> if possiable.
>
>
It happens on a dax_device. We should not interwind dax and block_device
even more after a lot of good work has happened to detangle them.
On Tue, Dec 29, 2020 at 8:06 PM Yong Wu wrote:
>
> On Wed, 2020-12-23 at 17:36 +0900, Tomasz Figa wrote:
> > On Wed, Dec 09, 2020 at 04:00:53PM +0800, Yong Wu wrote:
> > > In the previous SoC, the M4U HW is in the EMI power domain which is
> > > always on. the latest M4U is in the display power
On Thu, Dec 31, 2020 at 03:29:42PM +0100, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY block on the
On Thu, Dec 31, 2020 at 03:29:41PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
On Thu, Dec 31, 2020 at 03:29:40PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
> its own dedicated port in the fwnode graph.
>
> Support for this input is added with this change:
> - two pads are defined for the media entity instead of
On Fri, 2021-01-08 at 17:22 +0800, Zheng Yongjun wrote:
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/staging/media/hantro/hantro_v4l2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
The changes introduce a new security feature, RunTime Integrity Check
(RTIC), designed to protect Linux Kernel at runtime. The motivation
behind these changes is:
1. The system protection offered by SE for Android relies on the
assumption of kernel integrity. If the kernel itself is compromised
On 2021/1/5 上午7:34, Darrick J. Wong wrote:
On Fri, Dec 18, 2020 at 10:11:54AM +0800, Ruan Shiyang wrote:
On 2020/12/16 上午4:51, Darrick J. Wong wrote:
On Tue, Dec 15, 2020 at 08:14:13PM +0800, Shiyang Ruan wrote:
With the support of ->rmap(), it is possible to obtain the superblock on
a
On Fri, Jan 08, 2021 at 09:37:45AM +, David Laight wrote:
> The lack of spinlocks in userspace really kills you.
Glibc has them, but please don't complain about lock holder preemption
issues if you do actually use them ;-)
From: Al Viro
> Sent: 07 January 2021 18:34
>
> On Thu, Jan 07, 2021 at 09:43:54AM -0800, Linus Torvalds wrote:
>
> > Before, it would do the whole CLAC/STAC dance inside that loop for
> > every entry (and with that commit d55564cfc22 it would be a function
> > call, of course).
> >
> > Can you
Hi Robert,
On Thu, Jan 7, 2021 at 11:21 PM Robert Foss wrote:
>
> The Bayer GRBG10 mode used for earlier modes 3280x2460 and
> 1640x1232 isn't the mode output by the sensor for the
> 3264x2448 and 1632x1224 modes.
>
> Switch from MEDIA_BUS_FMT_SGRBG10_1X10 to MEDIA_BUS_FMT_SBGGR10_1X10
> for
On Thu, Dec 31, 2020 at 03:29:39PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports two distinct input interfaces:
> parallel and an external MIPI CSI-2 bridge. The parallel interface
> is often connected to a set of hardware pins while the MIPI CSI-2
> bridge is an internal
On Fri, Jan 08, 2021 at 09:54:30AM +0100, Borislav Petkov wrote:
> +#ifdef CONFIG_X86_THERMAL_VECTOR
> +static void unexpected_thermal_interrupt(void)
> +{
> + pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
> + smp_processor_id());
> +}
> +
> +static void
Hi Samuel,
Thanks a lot for working on this
I'm fine with the rest of the work, but I have a couple of questions
On Sun, Jan 03, 2021 at 04:30:52AM -0600, Samuel Holland wrote:
> The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional
> functionality compared to the sun7i/sun9i NMI
On Thursday 17 Dec 2020 at 16:20:49 (+0530), Viresh Kumar wrote:
> On 16-12-20, 19:37, Ionela Voinescu wrote:
> > I did not yet test this, but reading this comment made me wonder..
> >
> > arch_scale_freq_invariant() (or topology_scale_freq_invariant()) is also
> > called from schedutil when
On Thu, 31 Dec 2020 at 16:49, Rob Herring wrote:
>
> On Thu, Dec 24, 2020 at 04:42:08PM +0530, Roja Rani Yarubandi wrote:
> > While most devices within power-domains which support performance states,
> > scale the performance state dynamically, some devices might want to
> > set a static/default
From: Linus Torvalds
> Sent: 07 January 2021 19:34
>
> On Thu, Jan 7, 2021 at 11:04 AM Al Viro wrote:
> >
> > BTW, changing 'event' field in place from another thread is going to
> > be interesting - you have two 16bit values next to each other and
> > two CPUs modifying those with no exclusion.
On Thu, Jan 07, 2021 at 11:08:39PM +, Satya Tangirala wrote:
> > error = sb->s_op->freeze_super(sb);
> > else
> > @@ -600,6 +602,7 @@ int thaw_bdev(struct block_device *bdev)
> > if (!sb)
> > goto out;
> >
> > + bdev->bd_fsfreeze_sb = NULL;
> This causes
On Thu, Jan 07, 2021 at 04:28:43PM +0100, Sebastian Siewior wrote:
> This sleep can be triggered by ptrace/strace() and with brief testing I
> can trigger the sleep there but I don't get it anywhere near where I
> would notice it with cyclictest.
It's a single task wakeup (the caller), doing that
Hi Arnd,
On Fri, Jan 08, 2021 at 10:19:56AM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> With UBSAN enabled and building with clang, there are occasionally
> warnings like
>
> WARNING: modpost: vmlinux.o(.text+0xc533ec): Section mismatch in reference
> from the function
On Fri 08-01-21 17:01:03, Muchun Song wrote:
> On Fri, Jan 8, 2021 at 4:43 PM Michal Hocko wrote:
> >
> > On Thu 07-01-21 23:11:22, Muchun Song wrote:
[..]
> > > But I find a tricky problem to solve. See free_huge_page().
> > > If we are in non-task context, we should schedule a work
> > > to
From: Al Viro
> Sent: 07 January 2021 19:58
>
> On Thu, Jan 07, 2021 at 11:33:36AM -0800, Linus Torvalds wrote:
>
> > In fact, even some threaded app that does what I suspect it could do
> > would likely be ok with it 99% of the time. Because the situation
> > where you change the fd in the poll
On Thu 2021-01-07 21:18:20, Vineet Gupta wrote:
> On 1/7/21 7:48 PM, Sergey Senozhatsky wrote:
> > On (21/01/07 09:58), Vineet Gupta wrote:
> > > On 1/7/21 9:04 AM, Petr Mladek wrote:
> > > > On Thu 2021-01-07 08:43:16, Vineet Gupta wrote:
> > > > > Hi John,
> > > > >
> > > > > On 1/7/21 1:02 AM,
On 1/8/21 2:22 PM, Oscar Salvador wrote:
> Format %pG expects a lower case 'p' in order to print the flags.
> Fix it.
>
> Reported-by: Dan Carpenter
> Signed-off-by: Oscar Salvador
> Fixes: 8295d535e2aa ("mm,hwpoison: refactor get_any_page")
Reviewed-by: Anshuman Khandual
> ---
>
From: Hou Zhiqiang
The current Layerscape PCIe driver directly uses the physical layer
LTSSM code to check the link-up state, which treats the > L0 states
as link-up. This is not correct, since there is not explicit map
between link-up state and LTSSM. So this patch changes to use the
DWC common
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
V3:
- Rebased against the latest code base
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
Hi Sebastian,
On Friday, January 8, 2021 5:05 PM, Sebastian Siewior wrote:
>
> On 2021-01-08 08:45:14 [+], Ran Wang wrote:
> > Hi Sebastian, Peter
> Hi,
>
> > > I had a similar patch in -RT and dropped it in v5.10-rc7-rt16.
> > > It was added because RT couldn't boot since creating the
From: Hou Zhiqiang
Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally
put the PCIe controller into D3 state after the L2/L3 ready
state transition process completion.
Signed-off-by: Hou Zhiqiang
---
V3:
- Rebased against the latest code base
From: Hou Zhiqiang
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V3:
- Rebased against the latest code base
From: Hou Zhiqiang
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang
Acked-by: Rob Herring
---
V3:
- Rebased against the latest code
From: Hou Zhiqiang
This patch series is to add PCIe power management support for NXP
Layerscape platfroms.
Hou Zhiqiang (7):
PCI: dwc: Fix a bug of the case dw_pci->ops is NULL
PCI: layerscape: Change to use the DWC common link-up check function
dt-bindings: pci: layerscape-pci: Add a
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
V3:
- Rebased against the latest code base
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file
From: Hou Zhiqiang
The dw_pci->ops may be a NULL, and fix it by adding one more check.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
Acked-by: Gustavo Pimentel
---
V3:
- Rebased against the latest code base
drivers/pci/controller/dwc/pcie-designware-host.c | 2 +-
On Fri, Jan 08, 2021 at 10:21:54AM +0100, Peter Zijlstra wrote:
> On Thu, Jan 07, 2021 at 10:20:38PM +0100, Arnd Bergmann wrote:
> > On Thu, Jan 7, 2021 at 2:37 PM Russell King - ARM Linux admin
>
> > > So, do we raise the minimum gcc version for the kernel as a whole to 5.1
> > > or just for
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