04.03.2021 02:08, Michał Mirosław пишет:
> On Tue, Mar 02, 2021 at 03:44:44PM +0300, Dmitry Osipenko wrote:
>> Display controller (DC) performs isochronous memory transfers, and thus,
>> has a requirement for a minimum memory bandwidth that shall be fulfilled,
>> otherwise framebuffer data can't
allyesconfig
mips allmodconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a005-20210304
i386 randconfig-a003-20210304
i386 randconfig-a002-20210304
i386
On Thu, Mar 4, 2021 at 8:54 PM Winkler, Tomas wrote:
> > Winkler, Tomas writes:
> > >> "Winkler, Tomas" writes:
> > >>
> > >> >> The user space API is achieved via a number of synchronous IOCTLs.
> > >> >>
> > >> >> * RPMB_IOC_VER_CMD - simple versioning API
> > >> >> * RPMB_IOC_CAP_CMD -
Earlycon support is identical to S3C2410, but Apple SoCs also need
MMIO mapped as nGnRnE. This is handled generically for normal drivers
including the normal UART path here, but earlycon uses fixmap and
runs before that scaffolding is ready.
Since this is the only case where we need this fix, it
This currently supports:
* SMP (via spin-tables)
* AIC IRQs
* Serial (with earlycon)
* Framebuffer
A number of properties are dynamic, and based on system firmware
decisions that vary from version to version. These are expected
to be filled in by the loader.
Signed-off-by: Hector Martin
---
Apple SoCs are a distant descendant of Samsung designs and use yet
another variant of their UART style, with different interrupt handling.
In particular, this variant has the following differences with existing
ones:
* It includes a built-in interrupt controller with different registers,
using
Apple SoCs run firmware that sets up a simplefb-compatible framebuffer
for us. Add a compatible for it, and two missing supported formats.
Signed-off-by: Hector Martin
---
.../devicetree/bindings/display/simple-framebuffer.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git
This picks up the non-posted I/O mode needed for Apple platforms to
work properly.
This removes the request/release functions, which are no longer
necessary, since devm_ioremap_resource takes care of that already. Most
other drivers already do it this way, anyway.
Signed-off-by: Hector Martin
This decouples the TTY layer PORT_ types, which are exposed to
userspace, from the driver-internal flag of what kind of port this is.
This removes s3c24xx_serial_has_interrupt_mask, which was just checking
for a specific type anyway.
Signed-off-by: Hector Martin
---
* Split out s3c24xx_serial_tx_chars from s3c24xx_serial_tx_irq,
where only the latter acquires the port lock. This will be necessary
on platforms which have edge-triggered IRQs, as we need to call
s3c24xx_serial_tx_chars to kick off transmission from outside IRQ
context, with the port lock
Instead of patching a single global ops structure depending on the port
type, use a separate s3c64xx_serial_ops for the S3C64XX type. This
allows us to mark the structures as const.
Also split out s3c64xx_serial_shutdown into a separate function now that
we have a separate ops structure; this
This simplifies the code by removing the only distinction between the
S3C2410 and S3C2440 codepaths.
Signed-off-by: Hector Martin
---
drivers/tty/serial/samsung_tty.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/tty/serial/samsung_tty.c
This adds a Kconfig option to toggle support for Apple ARM SoCs.
At this time this targets the M1 and later "Apple Silicon" Mac SoCs.
Signed-off-by: Hector Martin
---
arch/arm64/Kconfig.platforms | 8
arch/arm64/configs/defconfig | 1 +
2 files changed, 9 insertions(+)
diff --git
Apple mobile devices originally used Samsung SoCs (starting with the
S5L8900), and their current in-house SoCs continue to use compatible
UART peripherals. We'll call this UART variant apple,s5l-uart.
Signed-off-by: Hector Martin
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Linus Walleij
---
AIC is the Apple Interrupt Controller found on Apple ARM SoCs, such as
the M1.
Signed-off-by: Hector Martin
Reviewed-by: Linus Walleij
---
.../interrupt-controller/apple,aic.yaml | 88 +++
MAINTAINERS | 1 +
This is used on Apple ARM platforms, which require most MMIO
(except PCI devices) to be mapped as nGnRnE.
Signed-off-by: Hector Martin
---
arch/arm64/include/asm/io.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index
Apple ARM64 SoCs have a ton of vendor-specific registers we're going to
have to deal with, and those don't really belong in sysreg.h with all
the architectural registers. Make a new home for them, and add some
registers which are useful for early bring-up.
Signed-off-by: Hector Martin
---
These definitions are in arm-gic-v3.h for historical reasons which no
longer apply. Move them to sysreg.h so the AIC driver can use them, as
it needs to peek into vGIC registers to deal with the GIC maintentance
interrupt.
Signed-off-by: Hector Martin
---
arch/arm64/include/asm/sysreg.h| 60
This is the root interrupt controller used on Apple ARM SoCs such as the
M1. This irqchip driver performs multiple functions:
* Handles both IRQs and FIQs
* Drives the AIC peripheral itself (which handles IRQs)
* Dispatches FIQs to downstream hard-wired clients (currently the ARM
timer).
*
ARM64 currently defaults to posted MMIO (nGnRnE), but some devices
require the use of non-posted MMIO (nGnRE). Introduce a new ioremap()
variant to handle this case. ioremap_np() is aliased to ioremap() by
default on arches that do not implement this variant.
sparc64 is the only architecture that
This implements the 'nonposted-mmio' and 'posted-mmio' boolean
properties. Placing these properties in a bus marks all child devices as
requiring non-posted or posted MMIO mappings. If no such properties are
found, the default is posted MMIO.
of_mmio_is_nonposted() performs the tree walking to
This documents the newly introduced ioremap_np() along with all the
other common ioremap() variants, and some higher-level abstractions
available.
Signed-off-by: Hector Martin
---
Documentation/driver-api/device-io.rst | 218 +
1 file changed, 218 insertions(+)
diff
This is different from the legacy AAPL prefix used on PPC, but
consensus is that we prefer `apple` for these new platforms.
Signed-off-by: Hector Martin
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Linus Walleij
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file
On Thu, 25 Feb 2021 19:49:49 -0400
Jason Gunthorpe wrote:
> On Thu, Feb 25, 2021 at 03:21:13PM -0700, Alex Williamson wrote:
>
> > This is where it gets tricky. The vm_pgoff we get from
> > file_operations.mmap is already essentially describing an offset from
> > the base of a specific
From: Marc Zyngier
It seems that the CPU known as Apple M1 has the terrible habit
of being stuck with HCR_EL2.E2H==1, in violation of the architecture.
Try and work around this deplorable state of affairs by detecting
the stuck bit early and short-circuit the nVHE dance. It is still
unknown
The implementor will be used to condition the FIQ support quirk.
The specific CPU types are not used at the moment, but let's add them
for documentation purposes.
Signed-off-by: Hector Martin
---
arch/arm64/include/asm/cputype.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
This series brings up initial support for the Apple M1 SoC, used in the
2020 Mac Mini, MacBook Pro, and MacBook Air models.
The following features are supported in this initial port:
- UART (samsung-style) with earlycon support
- Interrupts, including affinity and IPIs (Apple Interrupt
From: Arnd Bergmann
This adds more detailed descriptions of the various read/write
primitives available for use with I/O memory/ports.
Signed-off-by: Arnd Bergmann
Signed-off-by: Hector Martin
---
Documentation/driver-api/device-io.rst | 138 +
1 file changed, 138
This allows the devicetree to correctly represent the available set of
timers, which varies from device to device, without the need for fake
dummy interrupts for unavailable slots.
Also add the hyp-virt timer/PPI, which is not currently used, but worth
representing.
Signed-off-by: Hector Martin
Not all platforms provide the same set of timers/interrupts, and Linux
only needs one (plus kvm/guest ones); some platforms are working around
this by using dummy fake interrupts. Implementing interrupt-names allows
the devicetree to specify an arbitrary set of available interrupts, so
the timer
These are the CPU cores in the "Apple Silicon" M1 SoC.
Signed-off-by: Hector Martin
---
Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml
b/Documentation/devicetree/bindings/arm/cpus.yaml
index
This introduces bindings for all three 2020 Apple M1 devices:
* apple,j274 - Mac mini (M1, 2020)
* apple,j293 - MacBook Pro (13-inch, M1, 2020)
* apple,j313 - MacBook Air (M1, 2020)
Signed-off-by: Hector Martin
---
.../devicetree/bindings/arm/apple.yaml| 64 +++
On 2/8/2021 11:41 AM, Michael Kelley wrote:
> From: Nuno Das Neves Sent: Friday,
> November 20, 2020 4:30 PM
>>
>> Reserve ioctl number in userpsace-api/ioctl/ioctl-number.rst
>> Introduce MSHV_REQUEST_VERSION ioctl.
>> Introduce documentation for /dev/mshv in Documentation/virt/mshv
>>
>>
On Tue, Mar 02, 2021 at 03:02:25PM -0800, Stephen Boyd wrote:
Quoting Sasha Levin (2021-03-02 03:55:07)
From: AngeloGioacchino Del Regno
[ Upstream commit 785c02eb35009a4be6dbc68f4f7d916e90b7177d ]
In some rare occasions, we want to only set the RETAIN_MEM bit, but
not the RETAIN_PERIPH one:
On Thu, Mar 04, 2021 at 11:05:15AM -0800, Paul E. McKenney wrote:
> On Thu, Mar 04, 2021 at 10:35:24AM -0500, Alan Stern wrote:
> > On Wed, Mar 03, 2021 at 09:04:07PM -0800, Paul E. McKenney wrote:
> > > On Wed, Mar 03, 2021 at 10:21:01PM -0500, Alan Stern wrote:
> > > > On Wed, Mar 03, 2021 at
On Wed, Mar 3, 2021 at 2:29 PM Greg Kroah-Hartman
wrote:
>
> On Fri, Feb 19, 2021 at 03:37:08PM -0500, Al Cooper wrote:
> > Add a UART driver for the new Broadcom 8250 based STB UART. The new
> > UART is backward compatible with the standard 8250, but has some
> > additional features. The new
Hi Jason,
On Thu, 4 Mar 2021 15:02:53 -0400, Jason Gunthorpe wrote:
> On Thu, Mar 04, 2021 at 11:01:44AM -0800, Jacob Pan wrote:
>
> > > For something like qemu I'd expect to put the qemu process in a cgroup
> > > with 1 PASID. Who cares what qemu uses the PASID for, or how it was
> > >
On Thu, Mar 04, 2021 at 08:09:52AM +0100, Christophe Leroy wrote:
>
>
> Le 04/03/2021 à 05:47, Daniel Walker a écrit :
> > It looks like there's some seepage of cmdline stuff into
> > the generic device tree code. This conflicts with the
> > generic cmdline implementation so I remove it in the
On Thu, Mar 4, 2021 at 11:15 AM Marc Zyngier wrote:
>
> On Thu, 04 Mar 2021 18:45:44 +,
> Sami Tolvanen wrote:
> >
> > allmodconfig + CONFIG_LTO_CLANG_THIN=y fails to build due to following
> > linker errors:
> >
> > ld.lld: error: irqbypass.c:(function __guest_enter: .text+0x21CC):
>
> I
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: f69d02e37a85645aa90d18cacfff36dba370f797
commit: 21b55dbc0653018b8cd4513c37cbca303b0f0d50 io_uring: add
IOURING_REGISTER_RESTRICTIONS opcode
date: 5 months ago
config: powerpc-randconfig-r023-20210304
On Thu, Mar 04, 2021 at 08:00:49AM +0100, Christophe Leroy wrote:
>
>
> Le 04/03/2021 à 05:47, Daniel Walker a écrit :
> > This code allows architectures to use a generic builtin command line.
> > The state of the builtin command line options across architecture is
> > diverse. On x86 and mips
Hi all,
Commits
1b40fa66ac2b ("io_uring: reliably cancel linked timeouts")
42699d33e969 ("io_uring: cancel-match based on flags")
are missing a Signed-off-by from their committer.
--
Cheers,
Stephen Rothwell
pgpEpNW5VNmJl.pgp
Description: OpenPGP digital signature
On Thu, Mar 04, 2021 at 05:58:49PM +0100, Greg Kroah-Hartman wrote:
> On Thu, Mar 04, 2021 at 05:30:00PM +0100, Anthony Iliopoulos wrote:
> > On Thu, Mar 04, 2021 at 04:16:26PM +0100, Greg Kroah-Hartman wrote:
> > > On Thu, Mar 04, 2021 at 04:08:24PM +0100, Anthony Iliopoulos wrote:
> > > > commit
The pull request you sent on Wed, 3 Mar 2021 17:52:40 +0200:
> git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git/
> tags/tpmdd-next-v5.12-rc2
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/3cb60ee6323968b694208c4cbd56a7176396e931
Thank you!
--
On Thu, Mar 4, 2021 at 9:56 AM Naresh Kamboju wrote:
>
> On Thu, 4 Mar 2021 at 01:34, Guenter Roeck wrote:
> >
> > Upstream has:
> >
> > e71a8d5cf4b4 tty: fix up iterate_tty_read() EOVERFLOW handling
> > ddc5fda74561 tty: fix up hung_up_tty_read() conversion
>
> I have applied these two patches
On Wed, Mar 03 2021 at 16:37, Oleg Nesterov wrote:
> On 03/03, Sebastian Andrzej Siewior wrote:
>> +static void __sigqueue_cache_or_free(struct sigqueue *q)
>> +{
>> +struct user_struct *up;
>> +
>> +if (q->flags & SIGQUEUE_PREALLOC)
>> +return;
>> +
>> +up = q->user;
>> +
From: Vignesh Raghavendra
Add CPSW3g DT node with two external ports, MDIO and CPTS support. For
CPSW3g DMA channels the ASEL is set to 15 (AM642x per DMA channel coherency
feature), so that CPSW DMA channel participates in Coherency and thus avoid
need to cache maintenance for SKBs. This
Hi all,
In commit
f4c5e949056d ("scsi: ibmvfc: Reinitialize sub-CRQs and perform channel
enquiry after LPM")
Fixes tag
Fixes: 3034ebe26389 ("ibmvfc: add alloc/dealloc routines for SCSI Sub-CRQ
Channels")
has these problem(s):
- Subject does not match target commit subject
In commit
From: Vignesh Raghavendra
On am642-evm the CPSW3g ext. Port1 is directly connected to TI DP83867 PHY
and Port2 is connected to TI DP83869 PHY which is shared with ICSS
subsystem. The TI DP83869 PHY MII interface is configured using pinmux for
CPSW3g, while MDIO bus is connected through GPIO
Add DT node for the Main domain CPTS.
Signed-off-by: Grygorii Strashko
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Lokesh Vutla
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
From: Vignesh Raghavendra
AM642 SK board has 2 CPSW3g ports connected through TI DP83867 PHYs. Add DT
entries for the same.
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Grygorii Strashko
Reviewed-by: Lokesh Vutla
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 73
Hi
This series adds corresponding AM642x CPSW3g nodes required to enable networking
on TI am642-evm/sk platforms and adds required pinmux/PHY nodes in corresponding
board files.
Kernel Boot Log:
EVM: https://pastebin.ubuntu.com/p/6Qkbw35Jg3/
SK: https://pastebin.ubuntu.com/p/Pd3xxP9J9K/
On Wed, Mar 03 2021 at 16:37, Oleg Nesterov wrote:
> On 03/03, Sebastian Andrzej Siewior wrote:
>>
>> +static struct sigqueue *sigqueue_from_cache(struct task_struct *t)
>> +{
>> +struct sigqueue *q = t->sigqueue_cache;
>> +
>> +if (q && cmpxchg(>sigqueue_cache, q, NULL) == q)
>> +
On Wed, Mar 3, 2021 at 2:54 PM Alex Bennée wrote:
>
> + /* the rpmb is single open! */
> + if (test_and_set_bit(RPMB_DEV_OPEN, >status))
> + return -EBUSY;
open counters on device nodes are fundamentally broken, because
they do not stop you from using dup() or sharing
On 3/4/21 9:47 PM, Sasha Levin wrote:
On Tue, Mar 02, 2021 at 08:25:49PM +0100, Marek Vasut wrote:
On 12/23/20 3:13 AM, Sasha Levin wrote:
Hello Sasha,
From: Marek Vasut
[ Upstream commit 65277100caa2f2c62b6f3c4648b90d6f0435f3bc ]
In case RSI9116 SDIO WiFi operates in STA mode against
On Thu, Mar 4, 2021 at 9:53 PM Marco Elver wrote:
>
> cache_alloc_debugcheck_after() performs checks on an object, including
> adjusting the returned pointer. None of this should apply to KFENCE
> objects. While for non-bulk allocations, the checks are skipped when we
> allocate via KFENCE, for
On Thu, Mar 04 2021 at 13:04, Eric W. Biederman wrote:
> Thomas Gleixner writes:
>>
>> We could of course do the caching unconditionally for all tasks.
>
> Is there any advantage to only doing this for realtime tasks?
It was mostly to avoid tons of cached entries hanging around all over
the
On 04/03/2021 09:21, Tony Lindgren wrote:
When the timer is configured in posted mode, we need to check the write-
posted status register (TWPS) before writing to the register.
We now check TWPS after the write starting with commit 52762fbd1c47
("clocksource/drivers/timer-ti-dm: Add
On Wed, Mar 3, 2021 at 2:54 PM Alex Bennée wrote:
>
> A number of storage technologies support a specialised hardware
> partition designed to be resistant to replay attacks. The underlying
> HW protocols differ but the operations are common. The RPMB partition
> cannot be accessed via standard
On 04/03/2021 09:21, Tony Lindgren wrote:
We have of_translate_address() already do of_node_put() as needed.
I probably looked at __of_translate_address() earlier by accident
that of_translate_address() uses.
I do not see of_node_put() in of_translate_address() and
__of_translate_address()
cache_alloc_debugcheck_after() performs checks on an object, including
adjusting the returned pointer. None of this should apply to KFENCE
objects. While for non-bulk allocations, the checks are skipped when we
allocate via KFENCE, for bulk allocations cache_alloc_debugcheck_after()
is called via
[CCing the git list]
On Wed, Mar 03, 2021 at 12:53:18PM -0800, Linus Torvalds wrote:
> Hey peeps - some of you may have already noticed that in my public git
> tree, the "v5.12-rc1" tag has magically been renamed to
> "v5.12-rc1-dontuse". It's still the same object, it still says
> "v5.12-rc1"
On Thu, Mar 4, 2021 at 6:44 AM Maximilian Heyne wrote:
>
> This is a follow up of commit ea3274695353 ("net: sched: avoid
> duplicates in qdisc dump") which has fixed the issue only for the qdisc
> dump.
>
> The duplicate printing also occurs when dumping the classes via
> tc class show dev
On Thu, Mar 04, 2021 at 08:32:37AM -0600, Rob Herring wrote:
> On Wed, Mar 3, 2021 at 10:48 PM Daniel Walker wrote:
> >
> > It looks like there's some seepage of cmdline stuff into
> > the generic device tree code. This conflicts with the
> > generic cmdline implementation so I remove it in the
On Tue, Mar 02, 2021 at 08:25:49PM +0100, Marek Vasut wrote:
On 12/23/20 3:13 AM, Sasha Levin wrote:
Hello Sasha,
From: Marek Vasut
[ Upstream commit 65277100caa2f2c62b6f3c4648b90d6f0435f3bc ]
In case RSI9116 SDIO WiFi operates in STA mode against Intel 9260 in AP mode,
the association
On Wed, 03 Mar 2021 19:41:40 -0800, Brad Larson wrote:
> Add Pensando common and Elba SoC specific device nodes
> and corresponding binding documentation.
>
> Signed-off-by: Brad Larson
> ---
> .../bindings/gpio/pensando,elba-spics.txt | 24 ++
> .../devicetree/bindings/mmc/cdns,sdhci.yaml
On Thu, 04 Mar 2021 08:33:07 +0100, Ãlvaro Fernández Rojas wrote:
> Some devices may need to perform a reset before using the RNG, such as the
> BCM6368.
>
> Signed-off-by: Ãlvaro Fernández Rojas
> ---
> v5: no changes.
> v4: pass dt_binding_check.
> v3: make resets required if
On Wed, 03 Mar 2021 22:08:10 -0800, Sowjanya Komatineni wrote:
> This patch adds cpu-idle-states and corresponding state nodes to
> Tegra194 CPU in dt-binding document
>
> Signed-off-by: Sowjanya Komatineni
> ---
> .../bindings/arm/nvidia,tegra194-ccplex.yaml | 53
>
On Wed, 03 Mar 2021 14:24:33 +0800, Qing Zhang wrote:
> Add liointc-2.0 properties support, so update the maxItems and description.
>
> Signed-off-by: Jiaxun Yang
> Signed-off-by: Qing Zhang
> ---
>
> v2:
> - Add new patch
>
> .../bindings/interrupt-controller/loongson,liointc.yaml | 9
cc mailing list.
On 3/4/21 1:10 PM, Hsuan-Chi Kuo wrote:
Hello,
Should this line be atomic_read(>seccomp.filter_count));
https://elixir.bootlin.com/linux/latest/source/kernel/seccomp.c#L600
I think the desired behavior is to synchronize the filter count.
Thank you
> -Original Message-
> From: Brad Larson
> Sent: Wednesday, March 3, 2021 9:42 PM
> Subject: [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control
.
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
...
> +config GPIO_ELBA_SPICS
> + bool "Pensando Elba SPI
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use “flexible array members”[1] for these cases. The older
style of one-element or zero-length arrays should no longer be used[2].
weeks ago
config: powerpc64-randconfig-r026-20210304 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project
eec7f8f7b1226be422a76542cb403d02538f453a)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin
Hi Masami,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.12-rc1 next-20210304]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https
allyesconfig
mips allmodconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210304
x86_64 randconfig-a001-20210304
x86_64 randconfig-a004
mips allmodconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210304
x86_64 randconfig-a001-20210304
x86_64 randconfig-a004-20210304
x86_64
On 02/27, Jaegeuk Kim wrote:
> On 02/04, Chao Yu wrote:
> > Jaegeuk,
> >
> > On 2021/2/2 16:00, Chao Yu wrote:
> > > - for (i = 0; i < dic->nr_cpages; i++) {
> > > + for (i = 0; i < cc->nr_cpages; i++) {
> > > struct page *page = dic->cpages[i];
> >
> > por_fsstress still hang
On Thu, Mar 04, 2021 at 11:05:57AM -0800, Andy Lutomirski wrote:
> For kernel threads, task_pt_regs is currently all zeros, a valid user state
> (if kernel_execve() has been called), or some combination thereof during
> execution of kernel_execve(). If a stack trace is printed, the unwinder
>
On Wed, Mar 03, 2021 at 01:17:36PM +0800, Jin Yao wrote:
SNIP
> The set bits in 'bits' indicate the invalid bits used in config.
> Finally use strbuf to report the invalid bits.
>
> Some architectures may not export supported bits through sysfs,
> so if masks is 0, perf_pmu__config_valid just
On Thu, Mar 4, 2021 at 5:55 AM David Laight wrote:
>
> > (a) the traditional include guard optimization HAS NO HIDDEN SEMANTIC
> > MEANING. It's a pure optimization that doesn't actually change
> > anything else. If you don't do the optimization, absolutely nothing
> > changes.
>
> And if the
Andi Kleen writes:
>
> Normally disk encryption is in specialized work queues. It's total
> overkill to restrict all of the kernel if you just want to restrict
> those work queues.
>
> I would suggest some more analysis where secrets are actually stored
> and handled first.
Also thinking about
Hello,
syzbot found the following issue on:
HEAD commit:5695e516 Merge tag 'io_uring-worker.v3-2021-02-25' of git:..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=10bc7b96d0
kernel config: https://syzkaller.appspot.com/x/.config?x=e33ab2de74f48295
The initial value of the OF node based on presence of parent, but
at the same time this operation somehow appeared separately from others
that handle the OF case. On the other hand there is no need to assign
dev->fwnode in the OF case if code properly retrieves fwnode, i.e.
via dev_fwnode()
On Thu, Mar 4, 2021 at 2:15 PM Andy Shevchenko
wrote:
>
> On Thu, Mar 04, 2021 at 11:24:49AM +0100, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > Implement a new, modern GPIO testing module controlled by configfs
> > attributes instead of module parameters. The goal of this
In the ACPI case we may use the firmware node in the similar way
as it's done for OF case. We may use that fwnode for other purposes
in the future.
Signed-off-by: Andy Shevchenko
Reviewed-by: Linus Walleij
---
drivers/gpio/gpiolib-acpi.c | 7 +++
drivers/gpio/gpiolib-acpi.h | 4
When IRQ domain is created for an ACPI case, the name of it becomes unknown-%d
since for now it utilizes of_node member only and doesn't consider fwnode case.
Convert IRQ domain creation code to utilize fwnode instead.
Before/After the change on Intel Galileo Gen 2 with two GPIO (IRQ)
On Thu, Mar 04, 2021 at 06:29:32PM +, Marc Zyngier wrote:
> On Thu, 04 Mar 2021 15:02:11 +,
> Andy Shevchenko wrote:
> Please move this as an inline helper in linux/irqdomain.h, so that we
> can drop this export altogether.
Done in v3, thanks!
--
With Best Regards,
Andy Shevchenko
GPIO library uses of_node and fwnode in the core in non-unified way.
The series cleans this up and improves IRQ domain creation for non-OF cases
where currently the names of the domain are 'unknown'.
This has been tested on Intel Galileo Gen 2.
In v3:
- fix subtle bug in gpiod_count
- make
We have (historically) different approaches how we identify the type
of a given fwnode. Let's standardize them across the library code.
Signed-off-by: Andy Shevchenko
Reviewed-by: Linus Walleij
---
drivers/gpio/gpiolib.c | 28 +---
1 file changed, 13 insertions(+), 15
Linus Walleij pointed out that ird_domain_add_simple() gained
additional functionality and can't be anymore replaced with
a simple conditional. In preparation to upgrade GPIO library
to use fwnode, introduce irq_domain_create_simple() API which is
functional equivalent to the existing
Hi Michael,
On 24/02/2021, 11:06, "Michael S. Tsirkin" wrote:
CAUTION: This email originated from outside of the organization. Do not
click links or open attachments unless you can confirm the sender and know the
content is safe.
On Wed, Feb 24, 2021 at 10:47:30AM +0200, Adrian
On Wed, Mar 03, 2021 at 11:26:58PM -0800, Drew Fustini wrote:
> Add typo "overlfow" for "overflow". This typo was found and fixed in
> net/sctp/tsnmap.c.
>
> Link:
> https://lore.kernel.org/netdev/20210304055548.56829-1-d...@beagleboard.org/
> Suggested-by: Kees Cook
> Signed-off-by: Drew
On Wed, Mar 03, 2021 at 11:22:14PM +0800, John Garry wrote:
> Calling perf_pmu__find_map(NULL) returns the cpumap for the common CPU
> PMU. However arm64 supports heterogeneous-CPU based systems, and so there
> may be no common CPU PMU. As such, perf_pmu__find_map(NULL) returns NULL
> for arm64.
>
On Tue, Mar 02, 2021 at 03:00:00PM +, Quentin Perret wrote:
> We will soon unmap the .hyp sections from the host stage 2 in Protected
> nVHE mode, which obvisouly works with at least page granularity, so make
> sure to align them correctly.
s/obvisouly/obviously/
>
> Signed-off-by: Quentin
On Thu, Mar 04, 2021 at 12:58:54PM +0100, Rafael J. Wysocki wrote:
> On 3/4/2021 1:23 AM, paul...@kernel.org wrote:
> > From: Frederic Weisbecker
> >
> > Enqueuing a local timer after the tick has been stopped will result in
> > the timer being ignored until the next random interrupt.
> >
> >
On Thu, Feb 18, 2021 at 1:23 AM Shengjiu Wang wrote:
>
> On Thu, Feb 11, 2021 at 6:18 AM Rob Herring wrote:
> >
> > On Sun, Feb 07, 2021 at 06:23:55PM +0800, Shengjiu Wang wrote:
> > > Imx-rpmsg is a new added machine driver for supporting audio on Cortex-M
> > > core. The Cortex-M core will
On Tue, Mar 02, 2021 at 02:59:57PM +, Quentin Perret wrote:
> In order to ease its re-use in other code paths, refactor
> stage2_map_set_prot_attr() to not depend on a stage2_map_data struct.
> No functional change intended.
>
> Signed-off-by: Quentin Perret
> ---
>
On Wed, Feb 24, 2021 at 7:38 AM Michal Simek wrote:
>
> Hi Rob,
>
> On 2/11/21 3:42 PM, Rob Herring wrote:
> > On Thu, Feb 11, 2021 at 3:35 AM Michal Simek
> > wrote:
> >>
> >> Hi Rob,
> >>
> >> On 2/10/21 11:22 PM, Rob Herring wrote:
> >>> On Tue, Feb 09, 2021 at 11:48:09AM +0100, Michal Simek
On Tue, Mar 02, 2021 at 02:59:56PM +, Quentin Perret wrote:
> Once we start unmapping portions of memory from the host stage 2 (such
> as e.g. the hypervisor memory sections, or pages that belong to
> protected guests), we will need a way to track page ownership. And
> given that all mappings
On Thu, Mar 04, 2021 at 01:14:16PM -0600, Hsuan-Chi Kuo wrote:
> cc mailing list.
>
> On 3/4/21 1:10 PM, Hsuan-Chi Kuo wrote:
> > Hello,
> >
> > Should this line be atomic_read(>seccomp.filter_count));
> >
> > https://elixir.bootlin.com/linux/latest/source/kernel/seccomp.c#L600
> >
> > I think
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