Am 08.03.21 um 21:02 schrieb Felix Kuehling:
Am 2021-03-08 um 2:33 p.m. schrieb Arnd Bergmann:
On Mon, Mar 8, 2021 at 8:11 PM Felix Kuehling wrote:
Am 2021-03-08 um 2:05 p.m. schrieb Arnd Bergmann:
On Mon, Mar 8, 2021 at 5:24 PM Felix Kuehling wrote:
The driver build should work without IOM
On Wed, 03 Mar 2021 22:10:03 +0100, Heiko Thiery wrote:
> Add the Kontron pITX-imx8m board.
>
> Signed-off-by: Heiko Thiery
> Reviewed-by: Krzysztof Kozlowski
> ---
> v2:
> - bring in correct alphabetical order
>
> v3:
> - no change
>
> v4:
> - no change
>
> Documentation/devicetree/bindi
On Wed, 03 Mar 2021 12:02:50 -0800, Atish Patra wrote:
> Add YAML DT binding documentation for the Microchip PolarFire SoC.
> It is documented at:
>
> https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
>
> Signed-off-by: Atish Patra
> ---
> .../devicetree/binding
On Mon, Mar 08, 2021, Tom Lendacky wrote:
> On 2/25/21 2:47 PM, Sean Christopherson wrote:
> > Introduce MMU_PRESENT to explicitly track which SPTEs are "present" from
> > the MMU's perspective. Checking for shadow-present SPTEs is a very
> > common operation for the MMU, particularly in hot paths
Hi Yang,
On 2021-03-07 11:18 p.m., Yang Li wrote:
> In one of the error paths of the for_each_child_of_node() loop,
> add missing call to of_node_put().
>
> Fix the following coccicheck warning:
> ./sound/soc/bcm/cygnus-ssp.c:1346:1-33: WARNING: Function
> "for_each_available_child_of_node" shoul
On Wed, 03 Mar 2021 17:47:54 +0530, Rajendra Nayak wrote:
> From: Sai Prakash Ranjan
>
> Add compatible for watchdog timer on SC7280 SoC.
>
> Signed-off-by: Sai Prakash Ranjan
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/watchdog/qcom-
On Wed, 03 Mar 2021 17:47:51 +0530, Rajendra Nayak wrote:
> From: Sai Prakash Ranjan
>
> Add the SoC specific compatible for SC7280 implementing
> arm,mmu-500.
>
> Signed-off-by: Sai Prakash Ranjan
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Stephen Boyd
> ---
> Documentation/devicetree/b
Hello:
This series was applied to netdev/net.git (refs/heads/master):
On Sun, 7 Mar 2021 13:17:47 + you wrote:
> When the probe fails or requests to be defered, we must disable the
> regulator that was previously enabled.
>
> Fixes: 7994fe55a4a2 ("dm9000: Add regulator and reset support to
On Wed, 03 Mar 2021 17:47:48 +0530, Rajendra Nayak wrote:
> Add the compatible string for sc7180 SoC from Qualcomm
>
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
On Wed, 03 Mar 2021 17:47:46 +0530, Rajendra Nayak wrote:
> Add compatible for sc7280 SoC
>
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring
On Wed, 03 Mar 2021 17:47:45 +0530, Rajendra Nayak wrote:
> Document the sc7280 SoC and the IDP board bindings
>
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Stephen Boyd
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob He
On Wed, 03 Mar 2021 12:39:51 +0100, Benjamin Gaignard wrote:
> The current bindings seem to make the assumption that the
> two VPUs hardware blocks (G1 and G2) are only one set of
> registers.
> After implementing the VPU reset driver and G2 decoder driver
> it shows that all the VPUs are independe
On Wed, Mar 03, 2021 at 05:39:50PM +0800, Vic Wu wrote:
> The crypto mediatek driver has been replaced by the inside-secure driver now.
> Remove DT bindings documentation and update crypto engine nodes to the
> mt7623.dtsi files.
Wrap lines.
>
> Signed-off-by: Vic Wu
> Acked-by: Ryder Lee
> -
Hi Manish,
Thank you for the patch.
On Tue, Mar 09, 2021 at 12:19:16AM +0530, Manish Narani wrote:
> The current driver is not handling the clock enable/disable operations
> properly. The clocks need to be handled correctly by enabling or
> disabling at appropriate places. This patch adds code to
On Mon, Mar 08, 2021 at 08:47:47PM +0100, Rafael J. Wysocki wrote:
> On Mon, Mar 8, 2021 at 8:45 PM Andy Shevchenko
> wrote:
> >
> > It's quite spread code to initialize IRQ domain options.
> > Let's fold it into a simple oneliner.
> >
> > Signed-off-by: Andy Shevchenko
>
> Please see the commen
On 08/03/2021 18.21, Rob Herring wrote:
> On Fri, Feb 26, 2021 at 03:14:10PM +0100, Rasmus Villemoes wrote:
>> While a ripple counter can not usually be interfaced with (directly)
>> from software, it may still be a crucial component in a board
>> layout. To prevent its input clock from being disab
Am 2021-03-08 um 2:33 p.m. schrieb Arnd Bergmann:
> On Mon, Mar 8, 2021 at 8:11 PM Felix Kuehling wrote:
>> Am 2021-03-08 um 2:05 p.m. schrieb Arnd Bergmann:
>>> On Mon, Mar 8, 2021 at 5:24 PM Felix Kuehling
>>> wrote:
The driver build should work without IOMMUv2. In amdkfd/Makefile, we
>>>
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Sat, 6 Mar 2021 14:12:32 -0800 you wrote:
> Errors in protocol should be logged when the driver aborts operations.
> If the driver can carry on and "humor" the device, then emitting
> the message as debug output level is fin
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Sun, 7 Mar 2021 01:12:56 -0800 you wrote:
> When priv->rx_skbuff or priv->tx_skbuff is NULL, no error return code of
> uhdlc_init() is assigned.
> To fix this bug, ret is assigned with -ENOMEM in these cases.
>
> Reported-b
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Sat, 6 Mar 2021 14:12:31 -0800 you wrote:
> Several error paths in bind/probe code will only emit
> output using dev_dbg. But if we are going to fail the
> bind/probe, emit related output with "err" priority.
>
> Signed-off
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Sun, 7 Mar 2021 00:40:12 -0800 you wrote:
> When hns_assemble_skb() returns NULL to skb, no error return code of
> hns_nic_clear_all_rx_fetch() is assigned.
> To fix this bug, ret is assigned with -ENOMEM in this case.
>
>
> -Original Message-
> From: Dan Williams
> Sent: Tuesday, February 9, 2021 11:30 AM
> To: Greg KH
> Cc: Chen, Mike Ximing ; Linux Kernel Mailing List
> ; Arnd Bergmann ; Pierre-Louis
> Bossart ; Gage Eads
>
> Subject: Re: [PATCH v10 01/20] dlb: add skeleton for DLB driver
>
> On Tue
On Wed, Mar 03, 2021 at 09:11:58AM +0100, Steen Hegelund wrote:
> This provides reset driver support for the Microchip Sparx5 PCB134 and
> PCB135 reference boards.
This still looks like an incompatible change with no explanation.
What happens on an old kernel that expects "microchip,sparx5-chip-r
On 3/8/21 3:17 AM, John Garry wrote:
On 06/03/2021 04:43, Bart Van Assche wrote:
On 3/5/21 7:14 AM, John Garry wrote:
diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c
index 7ff1b20d58e7..5950fee490e8 100644
--- a/block/blk-mq-tag.c
+++ b/block/blk-mq-tag.c
@@ -358,11 +358,16 @@ void blk_mq_
Update drivers/hv/Kconfig so CONFIG_HYPERV can be selected on
ARM64, causing the Hyper-V specific code to be built.
Signed-off-by: Michael Kelley
Reviewed-by: Sunil Muthuswamy
---
drivers/hv/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/hv/Kconfig b/drive
The Hyper-V frame buffer driver may be built as a module, and
it needs access to screen_info. So export screen_info.
Signed-off-by: Michael Kelley
Acked-by: Ard Biesheuvel
---
arch/arm64/kernel/efi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel
Add function to inform Hyper-V about a guest panic.
Also add functions to set up and remove kexec and panic
handlers, which are currently unused on ARM64 but are
called from architecture independent code in the VMbus
driver.
This code is built only when CONFIG_HYPERV is enabled.
Signed-off-by: M
hyperv-tlfs.h defines Hyper-V interfaces from the Hyper-V Top Level
Functional Spec (TLFS), and #includes the architecture-independent
part of hyperv-tlfs.h in include/asm-generic. The published TLFS
is distinctly oriented to x86/x64, so the ARM64-specific
hyperv-tlfs.h includes information for AR
Add ARM64-specific code to initialize the Hyper-V
hypervisor when booting as a guest VM. Provide functions
and data structures indicating hypervisor status that
are needed by VMbus driver.
This code is built only when CONFIG_HYPERV is enabled.
Signed-off-by: Michael Kelley
---
arch/arm64/hyperv
Add architecture specific definitions and functions needed
by the architecture independent Hyper-V clocksource driver.
Update the Hyper-V clocksource driver to be initialized
on ARM64.
Signed-off-by: Michael Kelley
Reviewed-by: Sunil Muthuswamy
---
arch/arm64/include/asm/mshyperv.h | 12 ++
Hypercalls to Hyper-V on ARM64 may return results in registers other
than X0 thru X3, as permitted by the SMCCC spec version 1.2 and later.
Accommodate this by adding a variant of arm_smccc_1_1_hvc that allows
the caller to specify which 3 registers are returned in addition to X0.
Signed-off-by: M
This series enables Linux guests running on Hyper-V on ARM64
hardware. New ARM64-specific code in arch/arm64/hyperv initializes
Hyper-V, including its interrupts and hypercall mechanism.
Existing architecture independent drivers for Hyper-V's VMbus and
synthetic devices just work when built for ARM
On Mon, 8 Mar 2021 19:41:02 +0100 Álvaro Fernández Rojas wrote:
> This controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268
> SoCs.
>
> Signed-off-by: Álvaro Fernández Rojas
make[2]: *** Deleting file 'Module.symvers'
ERROR: modpost: missing MODULE_LICENSE() in drivers/net/m
Hi Daniel,
On 3/8/21 7:31 PM, Daniel Lezcano wrote:
On 01/03/2021 22:21, Daniel Lezcano wrote:
In order to increase the self-encapsulation of the dtpm generic code,
the following changes are adding a power update ops to the dtpm
ops. That allows the generic code to call directly the dtpm backe
On Mon, 8 Mar 2021 13:27:48 +
wrote:
> On 06.03.2021 19:30, Jonathan Cameron wrote:
> > On Mon, 1 Mar 2021 16:32:56 +0200
> > Eugen Hristev wrote:
> >
> >> Add support to sama7g5 ADC which is similar with sama5d2/sam9x60 device.
> >> Differences are highlighted by compatible.
> >> Main di
On Mon, Mar 08, 2021 at 09:46:52PM +0200, Andy Shevchenko wrote:
> On Mon, Mar 08, 2021 at 08:43:19PM +0100, Rafael J. Wysocki wrote:
> I just sent v5 without this, sorry :-)
I will do it in v6.
--
With Best Regards,
Andy Shevchenko
On Mon, Mar 08, 2021, Ashish Kalra wrote:
> On Fri, Feb 26, 2021 at 09:44:41AM -0800, Sean Christopherson wrote:
> > +Will and Quentin (arm64)
> >
> > Moving the non-KVM x86 folks to bcc, I don't they care about KVM details at
> > this
> > point.
> >
> > On Fri, Feb 26, 2021, Ashish Kalra wrote:
On Mon, Mar 08, 2021 at 09:36:52PM +0200, Andy Shevchenko wrote:
> On Mon, Mar 08, 2021 at 08:29:27PM +0100, Bartosz Golaszewski wrote:
> > On Mon, Mar 8, 2021 at 8:26 PM Rafael J. Wysocki wrote:
> > > On Mon, Mar 8, 2021 at 8:23 PM Bartosz Golaszewski
> > > wrote:
>
> ...
>
> > > My impression
The Brcmstb PCIe RC uses a reset control "rescal" for certain chips. This
reset implements a "pulse reset" so it matches more the reset/rearm
calls instead of the deassert/assert calls.
Also, add reset_control calls in suspend/resume functions.
Fixes: 740d6c3708a9 ("PCI: brcmstb: Add control of
This driver may use one of two resets controllers. Keep them in separate
variables to keep things simple. The reset controller "rescal" is shared
between the AHCI driver and the PCIe driver for the BrcmSTB 7216 chip. Use
devm_reset_control_get_optional_shared() to handle this sharing.
Fixes: 27
v4 -- does not rely on a pending commit, unlike v3.
v3 -- discard commit from v2; instead rely on the new function
reset_control_rearm provided in a recent commit [1] applied
to reset/next.
-- New commit to correct pcie-brcmstb.c usage of a reset controller
to use reset/rearm
On Wed, 03 Mar 2021 16:05:13 +0800, dillon.min...@gmail.com wrote:
> From: dillon min
>
> Signed-off-by: dillon min
> ---
> Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring
On Wed, 03 Mar 2021 16:05:12 +0800, dillon.min...@gmail.com wrote:
> From: dillon min
>
> Art-pi based on stm32h750xbh6, with following resources:
>
> -8MiB QSPI flash
> -16MiB SPI flash
> -32MiB SDRAM
> -AP6212 wifi, bt, fm
>
> detail information can be found at:
> https://art-pi.gitee.io/webs
Implement an access to the page cache as lock-free variant. This
is done because there are extra places where an access is required,
therefore making it lock-less will remove any lock contention.
For example we have a shrinker path as well as a reclaim kthread.
In both cases a current CPU can acce
From: Zhang Qiang
Add a drain_page_cache() function to drain a per-cpu page cache.
The reason behind of it is a system can run into a low memory
condition, in that case a page shrinker can ask for its users
to free their caches in order to get extra memory available for
other needs in a system.
On Mon, 8 Mar 2021 04:28:42 +
Sudeep Holla wrote:
> Hi Jonathan,
>
> On Tue, Feb 23, 2021 at 10:30:37AM -0800, Jyoti Bhayana wrote:
> > Hi Jonathan,
> >
> > Thanks for the detailed and careful review of this patch. Good to hear
> > that v7 is not required. Please find below answers to your
On 08/03/21 19:52, Tom Lendacky wrote:
On 2/25/21 2:47 PM, Sean Christopherson wrote:
Introduce MMU_PRESENT to explicitly track which SPTEs are "present" from
the MMU's perspective. Checking for shadow-present SPTEs is a very
common operation for the MMU, particularly in hot paths such as page
Hi Joerg
On Mon, Mar 08, 2021 at 09:58:26AM +0800, Lu Baolu wrote:
> Hi Joerg,
>
> On 3/4/21 8:26 PM, Joerg Roedel wrote:
> >On Thu, Feb 25, 2021 at 02:26:51PM +0800, Lu Baolu wrote:
> >>When the first level page table is used for IOVA translation, it only
> >>supports Read-Only and Read-Write pe
On Mon, Mar 8, 2021 at 8:45 PM Andy Shevchenko
wrote:
>
> It's quite spread code to initialize IRQ domain options.
> Let's fold it into a simple oneliner.
>
> Signed-off-by: Andy Shevchenko
Please see the comments I've just sent:
https://lore.kernel.org/linux-acpi/cajz5v0gpnzybdkfbxobyskuxs15gr
On Mon, Mar 08, 2021 at 08:43:19PM +0100, Rafael J. Wysocki wrote:
> On Mon, Mar 8, 2021 at 8:33 PM Andy Shevchenko
> wrote:
...
> It looks like the ops local var is redundant.
>
> > unsigned int type;
> > unsigned int i;
> >
> > @@ -1496,11 +1496,7 @@ static int gpiochip_add_ir
GPIO library uses of_node and fwnode in the core in non-unified way.
The series cleans this up and improves IRQ domain creation for non-OF cases
where currently the names of the domain are 'unknown'.
This has been tested on Intel Galileo Gen 2.
It touches GPIO core parts and it's expected that th
When IRQ domain is created for an ACPI case, the name of it becomes unknown-%d
since for now it utilizes of_node member only and doesn't consider fwnode case.
Convert IRQ domain creation code to utilize fwnode instead.
Before/After the change on Intel Galileo Gen 2 with two GPIO (IRQ) controllers:
It's quite spread code to initialize IRQ domain options.
Let's fold it into a simple oneliner.
Signed-off-by: Andy Shevchenko
---
drivers/gpio/gpiolib.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index afee48e7dd41.
In the ACPI case we may use the firmware node in the similar way
as it's done for OF case. We may use that fwnode for other purposes
in the future.
Signed-off-by: Andy Shevchenko
Reviewed-by: Linus Walleij
---
drivers/gpio/gpiolib-acpi.c | 7 +++
drivers/gpio/gpiolib-acpi.h | 4
driver
We have (historically) different approaches how we identify the type
of a given fwnode. Let's standardize them across the library code.
Signed-off-by: Andy Shevchenko
Reviewed-by: Linus Walleij
---
drivers/gpio/gpiolib.c | 28 +---
1 file changed, 13 insertions(+), 15 de
Linus Walleij pointed out that ird_domain_add_simple() gained
additional functionality and can't be anymore replaced with
a simple conditional. In preparation to upgrade GPIO library
to use fwnode, introduce irq_domain_create_simple() API which is
functional equivalent to the existing irq_domain_ad
The initial value of the OF node based on presence of parent, but
at the same time this operation somehow appeared separately from others
that handle the OF case. On the other hand there is no need to assign
dev->fwnode in the OF case if code properly retrieves fwnode, i.e.
via dev_fwnode() helper.
The following commit has been merged into the x86/seves branch of tip:
Commit-ID: 229164175ff0c61ff581e6bf37fbfcb608b6e9bb
Gitweb:
https://git.kernel.org/tip/229164175ff0c61ff581e6bf37fbfcb608b6e9bb
Author:Tom Lendacky
AuthorDate:Thu, 04 Mar 2021 16:40:11 -06:00
Committer:
On 3/3/21 10:16 PM, Alistair Popple wrote:
Some devices require exclusive write access to shared virtual
memory (SVM) ranges to perform atomic operations on that memory. This
requires CPU page tables to be updated to deny access whilst atomic
operations are occurring.
In order to do this intro
On Mon, Mar 8, 2021 at 8:33 PM Andy Shevchenko
wrote:
>
> It's quite spread code to initialize IRQ domain options.
> Let's fold it into a simple oneliner.
>
> Signed-off-by: Andy Shevchenko
> ---
> v4: new patch (see changelog of previous one)
> drivers/gpio/gpiolib.c | 8 ++--
> 1 file chan
On Mon, 8 Mar 2021 20:50:00 +0200
Ovidiu Panait wrote:
> Adjust the rss_stat tracepoint to print the name of the resident page type
> that got updated(e.g. MM_ANONPAGES/MM_FILEPAGES), rather than the numeric
> index corresponding to it(the __entry->member value):
>
> Before this patch:
> --
On 3/8/21 3:21 AM, Flavio Suligoi wrote:
> This patch series add a new way to consider the module parameters for the
> watchdog module.
>
> Instead of adding this kind of module parameters independently to each
> driver, the best solution is declaring each feature only once,
> in the watchdog core
On Mon, Mar 08, 2021 at 11:26:20PM +0800, kernel test robot wrote:
>
> Greeting,
>
> FYI, we noticed the following commit (built with gcc-9):
>
> commit: 9ddc8abf031750362cda61a9fb8a28be8871eaae ("[PATCH v4] mm: cma:
> support sysfs")
> url:
> https://github.com/0day-ci/linux/commits/Minchan-K
On Mon, Mar 08, 2021 at 08:29:27PM +0100, Bartosz Golaszewski wrote:
> On Mon, Mar 8, 2021 at 8:26 PM Rafael J. Wysocki wrote:
> > On Mon, Mar 8, 2021 at 8:23 PM Bartosz Golaszewski
> > wrote:
...
> > My impression was that Andy wanted me to take them.
> >
> > However, if you'd rather take care
y-a-new-debugfs-interface-for-splitting-THP-tests/20210308-232339
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git next
> config: x86_64-randconfig-a015-20210308 (attached as .config)
> compiler: clang version 13.0.0 (https://github.com/llvm/llvm-pro
On Mon, Mar 8, 2021 at 8:33 PM Andy Shevchenko
wrote:
>
> When IRQ domain is created for an ACPI case, the name of it becomes unknown-%d
> since for now it utilizes of_node member only and doesn't consider fwnode
> case.
> Convert IRQ domain creation code to utilize fwnode instead.
>
> Before/Aft
Hello RT-list!
I'm pleased to announce the 4.14.224-rt107 stable release.
Note that there was a futex/mutex code collision when I merge v4.14.218. I
believe
that it's fixed correctly but anyone with suspicions about futex/mutex behavior
in this release, that's where I'd start looking.
You can g
On Mon, Mar 08, 2021 at 08:26:39PM +0100, Rafael J. Wysocki wrote:
> On Mon, Mar 8, 2021 at 8:23 PM Bartosz Golaszewski
> wrote:
> > On Mon, Mar 8, 2021 at 7:22 PM Rafael J. Wysocki wrote:
> > > On Thu, Mar 4, 2021 at 9:13 PM Andy Shevchenko
> > > wrote:
> > AFAICT this should go through the GP
On 3/8/21 2:50 AM, John Garry wrote:
Please let me know further thoughts.
Hi John,
My guess is that it is safe to nest these two locks. I was asking
because I had not found any information about the nesting in the patch
description.
Bart.
On Mon, Mar 8, 2021 at 8:11 PM Felix Kuehling wrote:
>
> Am 2021-03-08 um 2:05 p.m. schrieb Arnd Bergmann:
> > On Mon, Mar 8, 2021 at 5:24 PM Felix Kuehling
> > wrote:
> >> The driver build should work without IOMMUv2. In amdkfd/Makefile, we
> >> have this condition:
> >>
> >> ifneq ($(CONFIG_AM
Hi all,
Friendly ping: who can review/take this, please?
Thanks!
--
Gustavo
On Tue, Feb 02, 2021 at 05:51:18PM -0600, Gustavo A. R. Silva wrote:
> There is a regular need in the kernel to provide a way to declare having
> a dynamically sized set of trailing elements in a structure. Kernel code
>
When IRQ domain is created for an ACPI case, the name of it becomes unknown-%d
since for now it utilizes of_node member only and doesn't consider fwnode case.
Convert IRQ domain creation code to utilize fwnode instead.
Before/After the change on Intel Galileo Gen 2 with two GPIO (IRQ) controllers:
It's quite spread code to initialize IRQ domain options.
Let's fold it into a simple oneliner.
Signed-off-by: Andy Shevchenko
---
v4: new patch (see changelog of previous one)
drivers/gpio/gpiolib.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpiolib.
On 01/03/2021 22:21, Daniel Lezcano wrote:
> In order to increase the self-encapsulation of the dtpm generic code,
> the following changes are adding a power update ops to the dtpm
> ops. That allows the generic code to call directly the dtpm backend
> function to update the power values.
>
> Th
On 08.03.21 20:11, Yang Shi wrote:
On Mon, Mar 8, 2021 at 11:01 AM Zi Yan wrote:
On 8 Mar 2021, at 13:11, David Hildenbrand wrote:
On 08.03.21 18:49, Zi Yan wrote:
On 8 Mar 2021, at 11:17, David Hildenbrand wrote:
On 08.03.21 16:22, Zi Yan wrote:
From: Zi Yan
By writing ",," to
/split_
One of the changes to the macb driver between 5.10 and 5.11 has broken
the SiFive HiFive Unleashed. These are the last messages before the
system hangs:
[ 12.468674] libphy: Fixed MDIO Bus: probed
[ 12.746518] macb 1009.ethernet: Registered clk switch
'sifive-gemgxl-mgmt'
[ 12.753119]
From: Nuno Das Neves Sent: Monday, March 8,
2021 11:14 AM
>
> On 2/8/2021 11:45 AM, Michael Kelley wrote:
> > From: Nuno Das Neves Sent: Friday,
> > November
> 20, 2020 4:30 PM
> >>
[snip]
> >> @@ -245,16 +249,318 @@ hv_call_delete_partition(u64 partition_id)
> >>return -hv_status_to_err
On Mon, Mar 8, 2021 at 8:26 PM Rafael J. Wysocki wrote:
>
> On Mon, Mar 8, 2021 at 8:23 PM Bartosz Golaszewski
> wrote:
> >
> > On Mon, Mar 8, 2021 at 7:22 PM Rafael J. Wysocki wrote:
> > >
> > > On Thu, Mar 4, 2021 at 9:13 PM Andy Shevchenko
> > > wrote:
> > > >
> > > > GPIO library uses of_no
On Mon, Mar 8, 2021 at 8:23 PM Bartosz Golaszewski
wrote:
>
> On Mon, Mar 8, 2021 at 7:22 PM Rafael J. Wysocki wrote:
> >
> > On Thu, Mar 4, 2021 at 9:13 PM Andy Shevchenko
> > wrote:
> > >
> > > GPIO library uses of_node and fwnode in the core in non-unified way.
> > > The series cleans this up
On 08.03.21 19:48, Oscar Salvador wrote:
On Thu, Mar 04, 2021 at 10:42:59AM -0800, Dave Hansen wrote:
On 3/1/21 12:32 AM, Oscar Salvador wrote:
We never get to allocate 1GB pages when mapping the vmemmap range.
Drop the dead code both for the aligned and unaligned cases and leave
only the direc
submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Zi-Yan/mm-huge_memory-a-new-debugfs-interface-for-splitting-THP-tests/20210308-232339
base:
https://git.kernel.org/pub/scm/linux/
Hi Lorenzo,
On Tue, 02 Mar 2021 10:27:44 +,
Lorenzo Pieralisi wrote:
>
> GIC CPU interfaces versions predating GIC v4.1 were not built to
> accommodate vINTID within the vSGI range; as reported in the GIC
> specifications (8.2 "Changes to the CPU interface"), it is
> CONSTRAINED UNPREDICTABL
On Mon, Mar 8, 2021 at 7:22 PM Rafael J. Wysocki wrote:
>
> On Thu, Mar 4, 2021 at 9:13 PM Andy Shevchenko
> wrote:
> >
> > GPIO library uses of_node and fwnode in the core in non-unified way.
> > The series cleans this up and improves IRQ domain creation for non-OF cases
> > where currently the
On Tue, Mar 02, 2021 at 08:03:02PM +0100, Martin Devera wrote:
> Add new rx-tx-swap property to allow for RX & TX pin swapping.
>
> Signed-off-by: Martin Devera
> ---
> .../devicetree/bindings/serial/st,stm32-uart.yaml | 32
> +++---
> 1 file changed, 22 insertions(+), 10 delet
On Mon, Mar 08, 2021 at 12:52:12PM -0600, Bjorn Helgaas wrote:
> On Mon, Mar 08, 2021 at 02:20:16PM +0200, Andy Shevchenko wrote:
> > From: Jonathan Yong
> >
> > There is already one and at least one more user is coming which
> > requires an access to Primary to Sideband bridge (P2SB) in order to
On Fri, 5 Mar 2021 10:54:56 +0530, Anshuman Khandual wrote:
> This series fixes pfn_valid() for ZONE_DEVICE based memory and also improves
> its performance for normal hotplug memory. While here, it also reorganizes
> pfn_valid() on CONFIG_SPARSEMEM. This series is based on v5.12-rc1.
>
> Cc: Cata
On Sun, Mar 7, 2021 at 11:28 PM Marek Szyprowski
wrote:
>
> Hi Saravana,
>
> On 05.03.2021 19:02, Saravana Kannan wrote:
> > On Fri, Mar 5, 2021 at 3:45 AM Marek Szyprowski
> > wrote:
> >> On 04.03.2021 20:51, Saravana Kannan wrote:
> >>> The uevents generated for an amba device need PID and CID
Before, the bus type related APIs that were defined in the
include/linux/device/bus.h were not referenced anywhere in the docs, so
I linked it to the bus types api documentation.
Signed-off-by: Wren Turkal
---
Documentation/driver-api/driver-model/bus.rst | 8
Documentation/driver-api/i
On Tue, Feb 16, 2021 at 4:13 PM Yang Shi wrote:
>
> Use per memcg's nr_deferred for memcg aware shrinkers. The shrinker's
> nr_deferred
> will be used in the following cases:
> 1. Non memcg aware shrinkers
> 2. !CONFIG_MEMCG
> 3. memcg is disabled by boot parameter
>
> Signed-off-by:
On 2/8/2021 11:45 AM, Michael Kelley wrote:
> From: Nuno Das Neves Sent: Friday,
> November 20, 2020 4:30 PM
>>
>> Introduce ioctls for mapping and unmapping regions of guest memory.
>>
>> Uses a table of memory 'slots' similar to KVM, but the slot
>> number is not visible to userspace.
>>
>> For
Skip patches generation for structs/unions with a single field.
Changing a zero-length array to a flexible array member in a struct
with no named members breaks the compilation. However, reporting
such cases is still valuable, e.g. commit 637464c59e0b
("ACPI: NFIT: Fix flexible_array.cocci warnings
On Tue, Feb 16, 2021 at 4:13 PM Yang Shi wrote:
>
> Currently the number of deferred objects are per shrinker, but some slabs,
> for example,
> vfs inode/dentry cache are per memcg, this would result in poor isolation
> among memcgs.
>
> The deferred objects typically are generated by __GFP_NOFS
On Wed, Mar 3, 2021 at 12:47 PM Nick Desaulniers
wrote:
>
> + Sami
>
> On Wed, Mar 3, 2021 at 10:34 AM Masahiro Yamada wrote:
> >
> > This guarding is wrong. As Documentation/kbuild/llvm.rst notes, LLVM=1
> > switches the default of tools, but you can still override CC, LD, etc.
> > individually.
On Mon, Mar 8, 2021 at 11:01 AM Zi Yan wrote:
>
> On 8 Mar 2021, at 13:11, David Hildenbrand wrote:
>
> > On 08.03.21 18:49, Zi Yan wrote:
> >> On 8 Mar 2021, at 11:17, David Hildenbrand wrote:
> >>
> >>> On 08.03.21 16:22, Zi Yan wrote:
> From: Zi Yan
>
> By writing ",," to
>
Am 2021-03-08 um 2:05 p.m. schrieb Arnd Bergmann:
> On Mon, Mar 8, 2021 at 5:24 PM Felix Kuehling wrote:
>> The driver build should work without IOMMUv2. In amdkfd/Makefile, we
>> have this condition:
>>
>> ifneq ($(CONFIG_AMD_IOMMU_V2),)
>> AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o
>> endif
>>
>
J. Bruce Fields wrote:
> On Mon, Mar 08, 2021 at 09:13:55AM +, David Howells wrote:
> > Amir Goldstein wrote:
> > > With ->fiemap() you can at least make the distinction between a non
> > > existing
> > > and an UNWRITTEN extent.
> >
> > I can't use that for XFS, Ext4 or btrfs, I suspect.
On Mon, Mar 8, 2021 at 5:24 PM Felix Kuehling wrote:
>
> The driver build should work without IOMMUv2. In amdkfd/Makefile, we
> have this condition:
>
> ifneq ($(CONFIG_AMD_IOMMU_V2),)
> AMDKFD_FILES += $(AMDKFD_PATH)/kfd_iommu.o
> endif
>
> In amdkfd/kfd_iommu.h we define inline stubs of the func
On 8 Mar 2021, at 13:11, David Hildenbrand wrote:
> On 08.03.21 18:49, Zi Yan wrote:
>> On 8 Mar 2021, at 11:17, David Hildenbrand wrote:
>>
>>> On 08.03.21 16:22, Zi Yan wrote:
From: Zi Yan
By writing ",," to
/split_huge_pages_in_range_pid, THPs in the process with the
g
On Mon, Mar 08, 2021 at 10:21:10AM -0800, Florian Fainelli wrote:
> On 3/8/21 1:24 AM, Thomas Bogendoerfer wrote:
> > BMIPS is one of the few platforms that do change the exception base.
> > After commit 2dcb39645441 ("memblock: do not start bottom-up allocations
> > with kernel_end") we started se
On Tue, Feb 23, 2021 at 07:44:47AM -0800, Ben Levinsky wrote:
> R5 is included in Xilinx Zynq UltraScale MPSoC so by adding this
> remoteproc driver, we can boot the R5 sub-system in two different
> configurations -
> * Split
> * Lockstep
>
> The Xilinx R5 Remoteproc Driver boots the R
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