Shadow stack accesses are those that are performed by the CPU where it
expects to encounter a shadow stack mapping. These accesses are performed
implicitly by CALL/RET at the site of the shadow stack pointer. These
accesses are made explicitly by shadow stack management instructions like
WRUSSQ.
A shadow stack PTE must be read-only and have _PAGE_DIRTY set. However,
read-only and Dirty PTEs also exist for copy-on-write (COW) pages. These
two cases are handled differently for page faults. Introduce
VM_SHADOW_STACK to track shadow stack VMAs.
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kiri
When Shadow Stack is introduced, [R/O + _PAGE_DIRTY] PTE is reserved for
shadow stack. Copy-on-write PTEs have [R/O + _PAGE_COW].
When a PTE goes from [R/W + _PAGE_DIRTY] to [R/O + _PAGE_COW], it could
become a transient shadow stack PTE in two cases:
The first case is that some processors can s
The read-only and Dirty PTE has been used to indicate copy-on-write pages.
However, newer x86 processors also regard a read-only and Dirty PTE as a
shadow stack page. In order to separate the two, the software-defined
_PAGE_COW is created to replace _PAGE_DIRTY for the copy-on-write case, and
pte_
There is essentially no room left in the x86 hardware PTEs on some OSes
(not Linux). That left the hardware architects looking for a way to
represent a new memory type (shadow stack) within the existing bits.
They chose to repurpose a lightly-used state: Write=0, Dirty=1.
The reason it's lightly
After the introduction of _PAGE_COW, a modified page's PTE can have either
_PAGE_DIRTY or _PAGE_COW. Change _PAGE_DIRTY to _PAGE_DIRTY_BITS.
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kees Cook
Reviewed-by: Kirill A. Shutemov
Cc: David Airlie
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Daniel Vett
To prepare the introduction of _PAGE_COW, move pmd_write() and
pud_write() up in the file, so that they can be used by other
helpers below.
Signed-off-by: Yu-cheng Yu
Reviewed-by: Kirill A. Shutemov
---
arch/x86/include/asm/pgtable.h | 24
1 file changed, 12 insertions(
The x86 family of processors do not directly create read-only and Dirty
PTEs. These PTEs are created by software. One such case is that kernel
read-only pages are historically setup as Dirty.
New processors that support Shadow Stack regard read-only and Dirty PTEs as
shadow stack pages. This re
A control-protection fault is triggered when a control-flow transfer
attempt violates Shadow Stack or Indirect Branch Tracking constraints.
For example, the return address for a RET instruction differs from the copy
on the shadow stack; or an indirect JMP instruction, without the NOTRACK
prefix, ar
Introduce CPU setup and boot option parsing for CET features.
Signed-off-by: Yu-cheng Yu
Cc: Kees Cook
---
v25:
- Remove software-defined X86_FEATURE_CET.
v24:
- Update #ifdef placement to reflect Kconfig changes of splitting shadow stack
and ibt.
arch/x86/include/uapi/asm/processor-flags.h |
Control-flow Enforcement (CET) is a new Intel processor feature that blocks
return/jump-oriented programming attacks. Details are in "Intel 64 and
IA-32 Architectures Software Developer's Manual" [1].
CET can protect applications and the kernel. This series enables only
application-level protect
Control-flow Enforcement Technology (CET) introduces these MSRs:
MSR_IA32_U_CET (user-mode CET settings),
MSR_IA32_PL3_SSP (user-mode shadow stack pointer),
MSR_IA32_PL0_SSP (kernel-mode shadow stack pointer),
MSR_IA32_PL1_SSP (Privilege Level 1 shadow stack pointer),
MSR_IA32
On Thu, Apr 15, 2021, Jim Mattson wrote:
> On Mon, Apr 12, 2021 at 3:23 PM Sean Christopherson wrote:
> >
> > Convert a comment above kvm_io_bus_unregister_dev() into an actual
> > lockdep assertion, and opportunistically add curly braces to a multi-line
> > for-loop.
> >
> > Signed-off-by: Sean C
Add CPU feature flags for Control-flow Enforcement Technology (CET).
CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack
CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect Branch Tracking
Signed-off-by: Yu-cheng Yu
Cc: Kees Cook
---
v25:
- Make X86_FEATURE_IBT depend on X86_FEATURE_SHSTK.
v24:
- Update for split
Shadow Stack provides protection against function return address
corruption. It is active when the processor supports it, the kernel has
CONFIG_X86_SHADOW_STACK enabled, and the application is built for the
feature. This is only implemented for the 64-bit kernel. When it is
enabled, legacy non-S
Explain no_user_shstk/no_user_ibt kernel parameters, and introduce a new
document on Control-flow Enforcement Technology (CET).
Signed-off-by: Yu-cheng Yu
Cc: Kees Cook
---
v24:
- Update for Kconfig changes from X86_CET to X86_SHADOW_STACK, X86_IBT.
- Update for the change of VM_SHSTK to VM_SHAD
On 4/14/21 12:11 PM, Jesse Brandeburg wrote:
> Nitesh Narayan Lal wrote:
>
>>> The original issue as seen, was that if you rmmod/insmod a driver
>>> *without* irqbalance running, the default irq mask is -1, which means
>>> any CPU. The older kernels (this issue was patched in 2014) used to use
>>
On 4/15/21 1:58 AM, Andrii Nakryiko wrote:
On Wed, Apr 14, 2021 at 4:32 PM Daniel Borkmann wrote:
On 4/15/21 1:19 AM, Andrii Nakryiko wrote:
On Wed, Apr 14, 2021 at 3:51 PM Toke Høiland-Jørgensen wrote:
Andrii Nakryiko writes:
On Wed, Apr 14, 2021 at 3:58 AM Toke Høiland-Jørgensen wrote:
Do not set uv_system_type for hubless UV systems as it tricks the
is_uv_system function into thinking it's a UV hubbed system and includes
a UV HUB RTC. This causes UV RTC init to panic on UV hubless systems.
Fixes: 41e2da9b5e67 ("x86/platform/uv: Use x2apic enabled bit as set by BIOS to
indicat
Hi all,
On Thu, 15 Apr 2021 14:00:16 + "Ong, Boon Leong"
wrote:
>
> I check linux-next merge fix above and spotted an additional fix needed.
> Please see below.
>
> >+ /**
> >+ * dma_recycle_rx_skbufs - recycle RX dma buffers
> >+ * @priv: private structure
> >+ * @queue: RX queue index
On Wed, Apr 14, 2021 at 10:09:49PM +0530, Rajeev Nandan wrote:
> If the panel connected to the bridge supports backlight control
> using DPCD registers on the DisplayPort aux channel, setting
> "use-aux-backlight" property in the bridge node will enable the
> registration of a DP aux backlight devi
On 2021-04-15 13:06, Stephen Boyd wrote:
Quoting khs...@codeaurora.org (2021-04-15 10:37:29)
On 2021-04-14 14:09, Stephen Boyd wrote:
> Quoting Kuogee Hsieh (2021-04-13 16:11:44)
>> Make sure main link is in connection state before start aux
>> read/write operation to avoid unnecessary long dela
On Tue, Apr 13, 2021 at 11:36:22AM +0800, Longfang Liu wrote:
> Register the live migration driver of the accelerator module to vfio
>
> Signed-off-by: Longfang Liu
> drivers/vfio/pci/vfio_pci.c | 11 +++
> drivers/vfio/pci/vfio_pci_private.h | 9 +
> 2 files changed, 20
On Wed, Apr 14, 2021 at 05:43:49PM +0200, Andrew Lunn wrote:
> On Wed, Apr 14, 2021 at 05:26:55PM +0200, Michael Walle wrote:
> > It is already possible to read the MAC address via a NVMEM provider. But
> > there are boards, esp. with many ports, which only have a base MAC
> > address stored. Thus
On Mon, Apr 12, 2021 at 3:23 PM Sean Christopherson wrote:
>
> Convert a comment above kvm_io_bus_unregister_dev() into an actual
> lockdep assertion, and opportunistically add curly braces to a multi-line
> for-loop.
>
> Signed-off-by: Sean Christopherson
> ---
> virt/kvm/kvm_main.c | 6 --
Hi all,
In commit
af5247b169a0 ("iommu/mediatek: Always enable the clk on resume")
Fixes tag
Fixes: commit c0b57581b73b ("iommu/mediatek: Add power-domain operation")
has these problem(s):
- leading word 'commit' unexpected
--
Cheers,
Stephen Rothwell
pgpG5YnhRgXwK.pgp
Description:
On Mon, Apr 12, 2021 at 3:21 PM Sean Christopherson wrote:
>
> If allocating a new instance of an I/O bus fails when unregistering a
> device, wait to destroy the device until after all readers are guaranteed
> to see the new null bus. Destroying devices before the bus is nullified
> could lead t
allnoconfig
x86_64 randconfig-a003-20210415
x86_64 randconfig-a002-20210415
x86_64 randconfig-a005-20210415
x86_64 randconfig-a001-20210415
x86_64 randconfig-a006-20210415
x86_64 randconfig-a004-20210415
i386
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Wed, 14 Apr 2021 10:34:28 +0800 you wrote:
> From: Jason Xing
>
> Fix this panic by adding more rules to calculate the value of @rss_size_max
> which could be used in allocating the queues when bpf is loaded, which,
> howev
[Cc+ NVIDIA folks both from migration and vfio-pci-core discussion]
On Tue, 13 Apr 2021 11:36:20 +0800
Longfang Liu wrote:
> The live migration solution relies on the vfio_device_migration_info protocol.
> The structure vfio_device_migration_info is placed at the 0th offset of
> the VFIO_REGION_
On Thu, 15 Apr 2021 21:16:34 +0530, Aswath Govindraju wrote:
> From: Faiz Abbas
>
> Some transceivers need a configuration step (for example, pulling the
> standby or enable lines) for them to start sending messages. The
> transceiver can be implemented as a phy with the configuration done in the
On Thu, 15 Apr 2021 09:19:09 -0500, Nishanth Menon wrote:
> Convert the ti,message-manager to yaml for better checks and documentation.
> Differences being mostly in the examples:
> - I've dropped the example usage of mailbox client, it is better done in
> tisci node definition
> - included heade
On Thu, 15 Apr 2021 18:47:27 +0800, Shawn Guo wrote:
> Add optional brcm,ccode-map property to support translation from ISO3166
> country code to brcmfmac firmware country code and revision.
>
> The country revision is needed because the RF parameters that provide
> regulatory compliance are tweak
On Thu, Apr 15, 2021 at 06:47:26PM +0800, Shawn Guo wrote:
> This is a couple of patches adding optional brcm,ccode-map bindings for
> brcmfmac driver to parse country code map from DT.
>
> Changes for v2:
> - Rebase bindings patch on top of yaml conversion patch [1].
> - Improve commit log with
On 4/15/2021 5:19 PM, Liang, Kan wrote:
Hi Steve,
On 4/15/2021 4:37 PM, Steve Wahl wrote:
If an uncore has no pci_init routine, or that routine fails,
uncore_pci_init is not called, and memory is not allocated for
uncore_extra_pci_dev.
So check to make sure uncore_extra_pci_dev is not NULL
From: Kan Liang
There may be a kernel panic on the Haswell server and the Broadwell
server, if the snbep_pci2phy_map_init() return error.
The uncore_extra_pci_dev[HSWEP_PCI_PCU_3] is used in the cpu_init() to
detect the existence of the SBOX, which is a MSR type of PMON unit.
The uncore_extra_pc
Aditya Srivastava writes:
> Currently kernel-doc does not identify some cases of probable kernel
> doc comments, for e.g. pointer used as declaration type for identifier,
> space separated identifier, etc.
>
> Some example of these cases in files can be:
> i)" * journal_t * jbd2_journal_init_dev
[...]
>
> Mike Leach (10):
> coresight: syscfg: Initial coresight system configuration
> coresight: syscfg: Add registration and feature loading for cs devices
> coresight: config: Add configuration and feature generic functions
> coresight: etm-perf: update to handle configuration select
> From: Stephen Hemminger
> Sent: Thursday, April 15, 2021 2:15 PM
> > ...
> > + netif_carrier_off(ndev);
> > +
> > + get_random_bytes(apc->hashkey, MANA_HASH_KEY_SIZE);
>
> Current practice for network drivers is to use netdev_rss_key_fill() for this.
Will change to netdev_rss_key_fill(). T
Commit 04324f44cb69 ("MIPS: Remove get_fs/set_fs") changed the access_ok
for strnlen_user to check the whole range, which broke some callers
of strndup_user(). Restore the old behaviour and just check the first byte.
Fixes: 04324f44cb69 ("MIPS: Remove get_fs/set_fs")
Signed-off-by: Thomas Bogendoe
On Mon, Apr 12, 2021 at 1:45 AM Flora Fu wrote:
>
> On Fri, 2021-04-09 at 13:25 -0500, Rob Herring wrote:
> > On Wed, Apr 07, 2021 at 11:28:02AM +0800, Flora Fu wrote:
> > > Document the apusys bindings.
> > >
> > > Signed-off-by: Flora Fu
> > > ---
> > > .../arm/mediatek/mediatek,apusys.yaml
On Thu, Apr 15, 2021 at 08:59:41PM +0100, Matthew Wilcox wrote:
> On Thu, Apr 15, 2021 at 08:57:04PM +0100, Matthew Wilcox wrote:
> > On Thu, Apr 15, 2021 at 10:49:55PM +0300, Sakari Ailus wrote:
> > > On Thu, Apr 15, 2021 at 06:14:09PM +0100, Matthew Wilcox wrote:
> > > > On Thu, Apr 15, 2021 at 0
On Wed, Apr 14, 2021 at 04:20:52PM +0300, bpe...@marvell.com wrote:
> From: Ben Peled
>
> Adding optional system-controller and mac-reset-bit-mask
> needed for linkdown procedure.
Same comment as v1.
BTW, it's PATCH not "PATCH". Don't do anything and git will do the right
thing here.
>
> Sig
On Mon, Apr 12, 2021 at 03:07:56PM +0200, Miklos Szeredi wrote:
> Hi Al,
>
> Fixed fileattr branch pushed to:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git fileattr_v6
Merged and pushed out...
Hi Steve,
On 4/15/2021 4:37 PM, Steve Wahl wrote:
If an uncore has no pci_init routine, or that routine fails,
uncore_pci_init is not called, and memory is not allocated for
uncore_extra_pci_dev.
So check to make sure uncore_extra_pci_dev is not NULL before use.
I think more after yesterday'
On Tue, Apr 13, 2021 at 05:45:35PM -0500, Nishanth Menon wrote:
> Convert the ti,secure-proxy to yaml for better checks and documentation.
> Differences being mostly in the examples:
> - I've dropped the example usage of mailbox client, it is better done in
> tisci node definition
> - Switched re
Hi Christoph,
On Thu, 15 Apr 2021 07:44:59 +0100, Christoph Hellwig
wrote:
> > *
> > * Returns 0 on success and < 0 on error.
> > @@ -28,6 +28,9 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm,
> > ioasid_t min, ioasid_t max) int ret = 0;
> > ioasid_t pasid;
> >
> > + if (mm != cur
On Wed, 14 Apr 2021 22:45:19 -0700
Dexuan Cui wrote:
> +static int mana_probe_port(struct mana_context *ac, int port_idx,
> +struct net_device **ndev_storage)
> +{
> + struct gdma_context *gc = ac->gdma_dev->gdma_context;
> + struct mana_port_context *apc;
> +
On Tue, 13 Apr 2021 19:40:14 +0200, Erwan Le Ray wrote:
> Remove data type from tx-threshold trigger level as defined now as a
> serial generic property.
>
> Signed-off-by: Erwan Le Ray
>
Reviewed-by: Rob Herring
On Tue, 13 Apr 2021 19:40:13 +0200, Erwan Le Ray wrote:
> Override rx-threshold and tx-threshold properties:
> - extend description
> - provide default and expected values
>
> Signed-off-by: Fabrice Gasnier
> Signed-off-by: Erwan Le Ray
>
> Changes in v2:
> Change added properties naming and fa
On Tue, 13 Apr 2021 19:40:12 +0200, Erwan Le Ray wrote:
> Add two optional DT properties to configure RX and TX FIFO thresholds:
> - rx-threshold
> - tx-threshold
>
> Signed-off-by: Erwan Le Ray
>
Reviewed-by: Rob Herring
From: Matthew Wilcox
> Sent: 15 April 2021 19:22
>
> On Thu, Apr 15, 2021 at 08:08:32PM +0200, Jesper Dangaard Brouer wrote:
> > +static inline
> > +dma_addr_t page_pool_dma_addr_read(dma_addr_t dma_addr)
> > +{
> > + /* Workaround for storing 64-bit DMA-addr on 32-bit machines in struct
> > +
On Tue, 13 Apr 2021 16:31:40 +0200, Amelie Delaunay wrote:
> This patch adds vbus-supply optional property to phy sub-nodes using
> connector node.
> A regulator for USB VBUS may be needed for host mode.
>
> Signed-off-by: Amelie Delaunay
> ---
> Changes in v2:
> - add connector vbus-supply prope
On Tue, 13 Apr 2021 15:18:48 +0200, Jiri Prchal wrote:
> Added dt binding documentation.
>
> Signed-off-by: Jiri Prchal
> ---
> -v2: fixed dt_binding_check warnings thanks to Rob Herring
> ---
> .../devicetree/bindings/eeprom/at25.yaml | 31 +++
> 1 file changed, 25 insertio
There are rs485 transceivers (e.g. MAX13487E/MAX13488E) which
automatically disable or enable the driver and receiver to keep the bus
in the correct state.
In these cases we don't need a GPIO for flow control.
Fixes: 4a0ac0f55b18 ("OMAP: add RS485 support")
Signed-off-by: Dario Binacchi
---
Cha
On Thu, Apr 15, 2021 at 8:57 AM Toke Høiland-Jørgensen wrote:
>
> Andrii Nakryiko writes:
>
> > On Wed, Apr 14, 2021 at 3:51 PM Toke Høiland-Jørgensen
> > wrote:
> >>
> >> Andrii Nakryiko writes:
> >>
> >> > On Wed, Apr 14, 2021 at 3:58 AM Toke Høiland-Jørgensen
> >> > wrote:
> >> >>
> >> >>
> -Original Message-
> From: Stephen Hemminger
> Sent: Thursday, April 15, 2021 5:08 PM
> To: Dexuan Cui
> Cc: da...@davemloft.net; k...@kernel.org; KY Srinivasan
> ; Haiyang Zhang ; Stephen
> Hemminger ; wei@kernel.org; Wei Liu
> ; net...@vger.kernel.org; l...@kernel.org;
> and...
On Thu, Apr 15, 2021 at 08:19:46PM +0530, Aswath Govindraju wrote:
> Add binding documentation for TI TCAN104x CAN transceivers.
>
> Signed-off-by: Aswath Govindraju
> ---
> .../bindings/phy/ti,tcan104x-can.yaml | 56 +++
> MAINTAINERS |
On Wed, 14 Apr 2021 22:45:19 -0700
Dexuan Cui wrote:
> +static int mana_query_vport_cfg(struct mana_port_context *apc, u32
> vport_index,
> + u32 *max_sq, u32 *max_rq, u32 *num_indir_entry)
> +{
> + struct mana_query_vport_cfg_resp resp = {};
> + struct mana_q
Data received during half-duplex transmission must be filtered.
If the target device responds quickly, emptying the FIFO at the end of
the transmission can erase not only the echo characters but also part of
the response message.
By keeping the receive interrupt enabled even during transmission, it
From: Colin Ian King
The inline keyword should be between storage class and type. Fix
this by swapping void inline to inline void.
Signed-off-by: Colin Ian King
---
arch/x86/um/shared/sysdep/stub_32.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/um/shared/sysdep
Em Thu, Apr 15, 2021 at 12:01:23PM +0800, Tiezhu Yang escreveu:
> (1) tools/bpf/bpftool build failed due to the following reason:
>
> Error: failed to load BTF from /boot/vmlinux-5.12.0-rc2: No such
> file or directory
> make: *** [Makefile:158: vmlinux.h] Error 2
>
> (2) When set CONFIG_DEBUG_IN
Wu XiangCheng writes:
> Hi all,
>
> This set of patches aim to add a new translation tool - trslt.py, which
> can control the transltions version corresponding to source files.
>
> For a long time, kernel documentation translations lacks a way to control the
> version corresponding to the source
On Tue, Apr 13, 2021 at 07:11:11PM +0200, Dmitry Vyukov wrote:
> On Tue, Apr 13, 2021 at 6:57 PM Alan Stern wrote:
> >
> > On Tue, Apr 13, 2021 at 06:47:47PM +0200, Dmitry Vyukov wrote:
> > > On Tue, Apr 13, 2021 at 6:13 PM Alan Stern
> > > wrote:
> > > > Hopefully this patch will make the race
On Thu, 15 Apr 2021 13:50:02 +0300, Claudiu Beznea wrote:
> Add RAM controller and RAM PHY controller DT bindings.
>
> Signed-off-by: Claudiu Beznea
> ---
> .../devicetree/bindings/arm/atmel-sysregs.txt | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
Acked-by: Rob
On 4/15/21 14:58, Kees Cook wrote:
> On Wed, Apr 14, 2021 at 06:45:15PM -0500, Gustavo A. R. Silva wrote:
>> Fix the following out-of-bounds warnings by adding a new structure
>> wl3501_req instead of duplicating the same members in structure
>> wl3501_join_req and wl3501_scan_confirm:
>>
>> arc
'printk(KERN_DEBUG pr_fmt(...))' can be replaced by a much less verbose
'pr_debug()'.
Signed-off-by: Christophe JAILLET
---
drivers/input/evbug.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/input/evbug.c b/drivers/input/evbug.c
index e47bdf92088a.
This is a left-over from commit 1a59d1b8e05e ("treewide: Replace GPLv2
boilerplate/reference with SPDX - rule 156")
Axe an empty and useless comment block.
Signed-off-by: Christophe JAILLET
---
drivers/input/evbug.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/input/evbug.c b/d
On Tue, Apr 6, 2021 at 10:47 AM Jonathan Cameron
wrote:
>
> On Thu, 1 Apr 2021 07:31:03 -0700
> Dan Williams wrote:
>
> > While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI
> > BAR, CXL root bridges have their MMIO base address described by platform
> > firmware. Refactor th
David Gow writes:
> The kernel now has a number of testing and debugging tools, and we've
> seen a bit of confusion about what the differences between them are.
>
> Add a basic documentation outlining the testing tools, when to use each,
> and how they interact.
>
> This is a pretty quick overvie
Wu XiangCheng writes:
> From: Bernard Zhao
>
> Add new zh translations
> * zh_CN/dev-tools/gcov.rst
> * zh_CN/dev-tools/index.rst
> and link them to zh_CN/index.rst
>
> Signed-off-by: Bernard Zhao
> Reviewed-by: Wu XiangCheng
> Reviewed-by: Alex Shi
> Reviewed-by: Fangrui Song
> Signed-off-b
On Tue, 13 Apr 2021 17:14:45 +0800
Keqian Zhu wrote:
> From: Kunkun Jiang
>
> In the past, we clear dirty log immediately after sync dirty
> log to userspace. This may cause redundant dirty handling if
> userspace handles dirty log iteratively:
>
> After vfio clears dirty log, new dirty log st
On 4/15/2021 3:04 AM, Roberto Sassu wrote:
> This patch set depends on:
>
> https://lore.kernel.org/linux-integrity/20210409114313.4073-1-roberto.sa...@huawei.com/
> https://lore.kernel.org/linux-integrity/20210407105252.30721-1-roberto.sa...@huawei.com/
>
> One of the challenges that must be tackl
Setting the realtime clock triggers an IPI to all CPUs to reprogram
the clock event device.
However, only realtime and TAI clocks have their offsets updated
(and therefore potentially require a reprogram).
Instead of sending an IPI unconditionally, check each per CPU hrtimer base
whether it has a
On Thu, 2021-04-15 at 18:58 +0100, Valentin Schneider wrote:
> Consider the following topology:
>
> Long story short, preempted misfit tasks are affected by task_hot(),
> while
> currently running misfit tasks are intentionally preempted by the
> stopper
> task to migrate them over to a higher-cap
If an uncore has no pci_init routine, or that routine fails,
uncore_pci_init is not called, and memory is not allocated for
uncore_extra_pci_dev.
So check to make sure uncore_extra_pci_dev is not NULL before use.
And fix the case that led us to discover the null derefs; don't fail
snbep_pci2phy_m
On Thu, 15 Apr 2021 12:05:33 +0800, dillon.min...@gmail.com wrote:
> From: dillon min
>
> The DaSheng Com-9xx is and ARM based signle board computer (SBC)
> featuring:
> - i.MX6Q
> - 2GiB LPDDR3 DRAM
> - 8GiB eMMC 5.0 FLASH
> - 4MiB SPI Flash
> - USB 2.0 Host/Device
> - Multiple multi-protocol RS
Hi James,
On Fri, Feb 12, 2021 at 04:45:06PM +0200, James Clark wrote:
> Hi All,
>
> Since my previous RFC, I've fixed --per-thread mode and solved
> most of the open questions. I've also changed --dump-raw-trace
> to use the same code path so it's also working now.
>
> I think the only open que
On Mon, Apr 12, 2021 at 11:53:02AM +, Bence Csókás wrote:
> While the preamble field _is_ technically big-endian, its value is always
> 0x2A2A,
> which is the same in either endianness, therefore it should be u16 instead.
Just replace the assignment with htons(0x2A2A) and be done with that -
On Thu, 15 Apr 2021 12:05:32 +0800, dillon.min...@gmail.com wrote:
> From: dillon min
>
> Add vendor prefix for DaSheng, Inc.
>
> Signed-off-by: dillon min
> Reviewed-by: Krzysztof Kozlowski
> ---
> v3:
> - move v2 patch 4 to v3 patch 1
> - add 'Reviewed-by: Krzysztof Kozlowski '
>
> Documen
On Mon, 12 Apr 2021 18:06:38 +0800, Zhen Lei wrote:
> Currently, if there are more than two ports, or if there is only one port
> but other properties(such as "#address-cells") is required, these ports
> are placed under the "ports" node. So add the schema of property "ports".
>
> Otherwise, warni
On Mon, 12 Apr 2021 18:06:37 +0800, Zhen Lei wrote:
> When I do dt_binding_check, below warning is reported:
> Documentation/devicetree/bindings/sound/renesas,rsnd.example.dt.yaml: \
> sound@ec50: 'dais' is a required property
>
> I looked at all the dts files in the "arch/arm64/boot/dts/renes
On Thu, 15 Apr 2021 13:56:24 +0200 "Christian König"
wrote:
> @@ -530,6 +525,11 @@ void ttm_pool_fini(struct ttm_pool *pool)
> for (j = 0; j < MAX_ORDER; ++j)
> ttm_pool_type_fini(&pool->caching[i].orders[j]);
> }
> +
> + /* We remove
On Wed, Apr 14, 2021 at 10:49:42AM -0400, Tianyu Lan wrote:
> From: Tianyu Lan
>
> For Hyper-V isolation VM with AMD SEV SNP, the bounce buffer(shared memory)
> needs to be accessed via extra address space(e.g address above bit39).
> Hyper-V code may remap extra address space outside of swiotlb.
On Wed, Apr 14, 2021 at 10:49:40AM -0400, Tianyu Lan wrote:
> From: Tianyu Lan
>
> VMbus ring buffer are shared with host and it's need to
> be accessed via extra address space of Isolation VM with
> SNP support. This patch is to map the ring buffer
> address in extra address space via ioremap().
On Thu, Apr 15, 2021 at 8:35 AM Dave Hansen wrote:
> > This can help enable more flexible demotion policies to be
> > configured, such as to allow a cgroup to allocate from all fast tier
> > nodes, but only demote to a local slow tier node. Such a policy can
> > reduce memory stranding at the fas
Hi Greg,
Please consider this patch as a fix for v5.12-rc7. Applies cleanly
to your char-misc-linus branch (e49d033bddf5).
Thanks,
Mathieu
Mike Leach (1):
coresight: etm-perf: Fix define build issue when built as module
drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +-
1 file changed
From: Mike Leach
CONFIG_CORESIGHT_SOURCE_ETM4X is undefined when built as module,
CONFIG_CORESIGHT_SOURCE_ETM4X_MODULE is defined instead.
Therefore code in format_attr_contextid_show() not correctly complied
when coresight built as module.
Use IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) to corre
Em Thu, Apr 15, 2021 at 03:09:28PM -0500, Rob Herring escreveu:
> On Thu, Apr 15, 2021 at 2:37 PM Arnaldo Carvalho de Melo
> wrote:
> > Ok, b4 failed on it, probably some missing Reply to, so I'll apply it by
> > hand:
>
> That's my fault. A duplicate message-id is the issue. git-send-email
> di
Hi Bence,
On Mon, Apr 12, 2021 at 11:53:02AM +, Bence Csókás wrote:
> While the preamble field _is_ technically big-endian, its value is always
> 0x2A2A,
> which is the same in either endianness, therefore it should be u16 instead.
Why should it be u16? I don't see it.
I thought the fix wou
On Thu, Apr 15, 2021 at 03:44:56PM -0400, Waiman Long wrote:
> On 4/15/21 3:40 PM, Johannes Weiner wrote:
> > On Thu, Apr 15, 2021 at 02:47:31PM -0400, Waiman Long wrote:
> > > On 4/15/21 2:10 PM, Johannes Weiner wrote:
> > > > On Thu, Apr 15, 2021 at 12:35:45PM -0400, Waiman Long wrote:
> > > > >
Avri
Please let me know if you have some concerns.
Kimito
On 4/15/2021 6:32 AM, Ulf Hansson wrote:
+ Avri
On Fri, 2 Apr 2021 at 01:02, wrote:
From: Kimito Sakata
Signed-off-by: Kimito Sakata
This looks okay to me, but I have looped in Avri who might have some comments.
Kind regards
Uff
On 15/04/2021 20:09, Valentin Schneider wrote:
> On 14/04/21 20:23, Ruifeng Zhang wrote:
>> From: Ruifeng Zhang
>>
>> In Unisoc, the sc9863a SoC which using cortex-a55, it has two software
>> version, one of them is the kernel running on EL1 using aarch32.
>> user(EL0)
On Thu, Apr 15, 2021 at 2:37 PM Arnaldo Carvalho de Melo
wrote:
>
> Em Thu, Apr 15, 2021 at 04:14:31AM +0900, Namhyung Kim escreveu:
> > On Thu, Apr 15, 2021 at 3:23 AM Arnaldo Carvalho de Melo
> > wrote:
> > >
> > > Em Wed, Apr 14, 2021 at 03:02:08PM -0300, Arnaldo Carvalho de Melo
> > > escrev
On Thu, Apr 15, 2021 at 10:33:19AM +1200, Chris Packham wrote:
> I've tested on T2081 and P2041 based systems with a number of i2c and smbus
> devices.
>
> I've included some clean ups provided by Andy Shevchenko to make applying the
> series easier.
Applied to for-next, thanks!
signature.asc
On Thu, Apr 15, 2021 at 03:46:46PM -0400, Chris von Recklinghausen wrote:
> Hibernation fails on a system in fips mode because md5 is used for the e820
> integrity check and is not available. Use crc32 instead.
>
> This patch changes the integrity check algorithm from md5 to crc32.
The second par
On 4/15/2021 6:07 AM, Oleksij Rempel wrote:
> Port some parts of the stmmac selftest and reuse it as basic generic selftest
> library. This patch was tested with following combinations:
> - iMX6DL FEC -> AT8035
> - iMX6DL FEC -> SJA1105Q switch -> KSZ8081
> - iMX6DL FEC -> SJA1105Q switch -> KSZ
Quoting khs...@codeaurora.org (2021-04-15 10:37:29)
> On 2021-04-14 14:09, Stephen Boyd wrote:
> > Quoting Kuogee Hsieh (2021-04-13 16:11:44)
> >> Make sure main link is in connection state before start aux
> >> read/write operation to avoid unnecessary long delay due to
> >> main link had been unp
On Thu, Apr 15, 2021 at 04:47:54PM +0200, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.10.31 release.
> There are 25 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know
On Thu, Apr 15, 2021 at 2:51 PM Arnaldo Carvalho de Melo
wrote:
>
> Em Thu, Apr 15, 2021 at 04:48:34PM -0300, Arnaldo Carvalho de Melo escreveu:
> > Em Thu, Apr 15, 2021 at 04:46:46PM -0300, Arnaldo Carvalho de Melo escreveu:
> > > Em Wed, Apr 14, 2021 at 03:53:36PM -0500, Rob Herring escreveu:
>
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