QE tested this series of patches with virtio_net regression tests,
everything works fine.
Tested-by: Lei Yang
On Tue, Mar 18, 2025 at 5:57 PM Akihiko Odaki wrote:
>
> Jason Wang recently proposed an improvement to struct
> virtio_net_rss_config:
> https://lore.kernel.org/r/CACGkMEud0Ki8p=z299q7
The pull request you sent on Fri, 28 Mar 2025 12:18:27 -0500:
> https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git
> tags/hwlock-v6.15
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/7d4eca7ac5f92eceeadfae0321621ddef1346c5a
Thank you!
--
Deet-doot-
The pull request you sent on Fri, 28 Mar 2025 14:26:04 -0500:
> https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git
> tags/rproc-v6.15
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/472863ab2aca6f4d2b7db828f77c36c5d1f43d9a
Thank you!
--
Deet-doot-d
Currently, the ->gpwrap is not tested (at all per my testing) due to the
requirement of a large delta between a CPU's rdp->gp_seq and its node's
rnp->gpseq.
This results in no testing of ->gpwrap being set. This patch by default
adds 5 minutes of testing with ->gpwrap forced by lowering the delta
March 28, 2025 at 10:05 PM, "Shuah Khan" wrote:
>
> On 3/18/25 10:05, Yosry Ahmed wrote:
>
> > 'realpath' is not always available, fallback to 'readlink -f' if is not
> > available. They seem to work equally well in this context.
>
> Can you add more specifics on "realpath" is not always avail
Hi,
On 3/29/25 3:42 PM, Stafford Horne wrote:
Thanks for the respin.
I will take this version and put it in linux next to see if any issues come up.
-Stafford
Sounds good. Let me know if any more changes are required.
On Sat, Mar 29, 2025 at 03:16:19PM +0530, Sahil Siddiq wrote:
Hi,
The
On Fri, Mar 28, 2025 at 04:23:38PM -0600, Shuah Khan wrote:
> On 3/24/25 16:01, Thomas Weißschuh wrote:
> > The include of sys/io.h is not necessary anymore since
> > commit 67eb617a8e1e ("selftests/nolibc: simplify call to ioperm").
> > It's existence is also problematic as the header does not exi
On Sat, 29 Mar 2025, Dmitry V. Levin wrote:
> > > +#if defined(_MIPS_SIM) && _MIPS_SIM == _MIPS_SIM_NABI32
> > > +/*
> > > + * MIPS N32 is the only architecture where __kernel_ulong_t
> > > + * does not match the bitness of syscall arguments.
> > > + */
> > > +typedef unsigned long long kernel_ulo
On 3/28/25 23:45, David Heidelberg wrote:
On 26/03/2025 11:26, Caleb Connolly wrote:
On 3/26/25 07:57, Krzysztof Kozlowski wrote:
On 25/03/2025 14:23, Caleb Connolly wrote:
On 3/25/25 08:36, Krzysztof Kozlowski wrote:
On 24/03/2025 19:00, David Heidelberg wrote:
On 10/03/2025 10:45, K
On Fri, Mar 28, 2025 at 05:04:54PM -0600, Shuah Khan wrote:
> On 1/15/25 16:37, Dmitry V. Levin wrote:
> > MIPS n32 is one of two ILP32 architectures supported by the kernel
> > that have 64-bit syscall arguments (another one is x32).
> >
> > When this test passed 32-bit arguments to syscall(), th
On Fri, Mar 28, 2025 at 08:14:41AM -0600, Mathieu Poirier wrote:
>On Fri, Mar 28, 2025 at 12:50:12PM +0800, Peng Fan wrote:
>> On Thu, Mar 27, 2025 at 11:46:33AM -0600, Mathieu Poirier wrote:
>> >Hi,
>> >
>> >On Wed, Mar 26, 2025 at 10:02:14AM +0800, Peng Fan (OSS) wrote:
>> >> From: Peng Fan
>> >
On 2025-03-26 23:04:30+0100, Sebastian Andrzej Siewior wrote:
> On 2025-03-26 22:51:54 [+0100], Thomas Weißschuh wrote:
> > > mips32le works as-is.
> > > For mips64le I had to s/-march=mips64r6/-march=mips64r2 to match the
> > > ABI. Which makes me wonder: Why do do we need to pass -march here and
Add cacheinfo support for OpenRISC.
Currently, a few CPU cache attributes pertaining to OpenRISC processors
are exposed along with other unrelated CPU attributes in the procfs file
system (/proc/cpuinfo). However, a few cache attributes remain unexposed.
Provide a mechanism that the generic cache
According to the OpenRISC architecture manual, the dcache and icache may
not be present. When these caches are present, the invalidate and flush
registers may be absent. The current implementation does not perform
checks to verify their presence before utilizing cache registers, or
invalidating and
Hi,
The main purpose of this series is to expose CPU cache attributes for
OpenRISC in sysfs using the cacheinfo API. The core implementation
to achieve this is in patch #3. Patch #1 and #2 add certain enhancements
to simplify the implementation of cacheinfo support.
Patch #1 removes duplication o
The "cpuinfo_or1k" structure currently has identical data members for
different cache components.
Remove these fields out of struct cpuinfo_or1k and into its own struct.
This reduces duplication while keeping cpuinfo_or1k extensible so more
cache descriptors can be added in the future.
Also add a
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