[PATCH] Staging: comedi: fix redundant parens in return in amplc_dio200_common.c

This patch fixes a coding style issue found by the checkpatch.pl tool in amplc_dio200_common.c by removing the unnecessary parentheses around the expression in a return statement. Signed-off-by: Aapo Vienamo --- drivers/staging/comedi/drivers/amplc_dio200_common.c | 2 +- 1 file changed, 1

Re: [PATCH] Staging: comedi: fix redundant parens in return in amplc_dio200_common.c

On Thu, Dec 18, 2014 at 02:45:01PM -0800, Jeremiah Mahler wrote: > Aapo, > > On Thu, Dec 18, 2014 at 05:32:52PM +0200, Aapo Vienamo wrote: > > This patch fixes a coding style issue found by the checkpatch.pl tool in > > amplc_dio200_common.c by removing the unnecessary p

Re: [PATCH] Staging: comedi: fix redundant parens in return in amplc_dio200_common.c

On Fri, Dec 19, 2014 at 06:13:10AM -0800, Jeremiah Mahler wrote: > Aapo, > > On Fri, Dec 19, 2014 at 12:37:16PM +0200, Aapo Vienamo wrote: > > On Thu, Dec 18, 2014 at 02:45:01PM -0800, Jeremiah Mahler wrote: > > > Aapo, > > > > > > On Thu, Dec 18, 20

[PATCH v3 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

From: Peter De-Schrijver These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-id.h | 2

[PATCH v3 1/4] clk: tegra: Fix includes required by fence_udelay()

Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo --- drivers/clk/tegra/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e1f8846..e3b9c22 100644 --- a/drivers

[PATCH v3 3/4] clk: tegra: Add sdmmc mux divider clock

will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile| 1 + drivers/clk/tegra/clk-sdmmc-mux.c | 250

[PATCH v3 2/4] clk: tegra: refactor 7.1 div calculation

From: Peter De Schrijver Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-divider.c | 30

[PATCH v4 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

From: Peter De-Schrijver These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-id.h | 2

[PATCH v4 1/4] clk: tegra: Fix includes required by fence_udelay()

Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo --- drivers/clk/tegra/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e1f8846..e3b9c22 100644 --- a/drivers

[PATCH v4 0/4] Multiplex sdmmc low jitter clock path

includes for fence_udelay() in a separate patch v2: - Fix the type compatibility error on do_div Aapo Vienamo (1): clk: tegra: Fix includes required by fence_udelay() Peter De Schrijver (1): clk: tegra: refactor 7.1 div calculation Peter De-Schrijver (2): clk: tegra: Add sdmmc mux divider

[PATCH v4 3/4] clk: tegra: Add sdmmc mux divider clock

will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile| 1 + drivers/clk/tegra/clk-sdmmc-mux.c | 250

[PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

From: Peter De Schrijver Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-divider.c | 30

[PATCH 0/6] Tegra PMC pinctrl pad configuration

Hi all, The Tegra Power Management Controller (PMC) can set pad power states and voltage configuration. This series implements pinctrl interfaces for configuring said pad properties. Aapo Vienamo (6): soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD

[PATCH 3/6] soc/tegra: pmc: Implement tegra_io_pad_is_powered()

Implement a function to query whether a pad is in deep power down mode. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 17 + include/soc/tegra/pmc.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 83b39cd

[PATCH 4/6] soc/tegra: pmc: Use X macro to generate IO pad tables

Refactor the IO pad tables into macro tables so that they can be reused to generate pinctrl pin descriptors. Also add a name field which is needed by pinctrl. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 231 ++-- 1 file changed, 126

[PATCH 2/6] soc/tegra: pmc: Factor out DPD register bit calculation

Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 20 +--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a

[PATCH 1/6] soc/tegra: pmc: Fix pad voltage configuration for Tegra186

Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 54

[PATCH 5/6] dt-bindings: Add Tegra PMC pad configuration bindings

: Aapo Vienamo --- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 +++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 3 files changed, 197 insertions(+) create mode 100644

[PATCH 6/6] soc/tegra: pmc: Implement pad configuration via pinctrl

Register a pinctrl device and implement get and set functions for PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 192 +++- 1 file changed, 190 insertions(+), 2 deletions

Re: [PATCH 4/6] soc/tegra: pmc: Use X macro to generate IO pad tables

On Wed, 11 Jul 2018 09:30:57 +0100 Jon Hunter wrote: > On 10/07/18 13:47, Aapo Vienamo wrote: > > Refactor the IO pad tables into macro tables so that they can be reused > > to generate pinctrl pin descriptors. Also add a name field which is > > needed by pinctrl. > &g

Re: [PATCH 6/6] soc/tegra: pmc: Implement pad configuration via pinctrl

On Wed, 11 Jul 2018 09:40:01 +0100 Jon Hunter wrote: > On 10/07/18 13:54, Aapo Vienamo wrote: > > Register a pinctrl device and implement get and set functions for > > PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. > > > > Signed-off-by: Aapo Vienam

Re: [PATCH 6/6] soc/tegra: pmc: Implement pad configuration via pinctrl

On Wed, 11 Jul 2018 10:46:21 +0100 Jon Hunter wrote: > On 11/07/18 10:38, Aapo Vienamo wrote: > > On Wed, 11 Jul 2018 09:40:01 +0100 > > Jon Hunter wrote: > > > >> On 10/07/18 13:54, Aapo Vienamo wrote: > >>> Register a pinctrl devi

[PATCH v2 1/7] soc/tegra: pmc: Fix pad voltage configuration for Tegra186

Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 55

[PATCH v2 0/7] Tegra PMC pinctrl pad configuration

TEGRA_IO_PAD() and TEGRA_IO_PIN_DESC() - Fix a typo in the dt-bindings docs - Remove old pmc pad voltage configuration APIs - Check return value of tegra_io_pad_find() in tegra_io_pad_pinconf_get()/_set() Aapo Vienamo (7): soc/tegra: pmc: Fix pad voltage

[PATCH v2 2/7] soc/tegra: pmc: Factor out DPD register bit calculation

Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 20 +--- 1 file changed, 17 insertions(+), 3

[PATCH v2 3/7] soc/tegra: pmc: Implement tegra_io_pad_is_powered()

Implement a function to query whether a pad is in deep power down mode. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 17 + include/soc/tegra/pmc.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc

[PATCH v2 4/7] soc/tegra: pmc: Use X macro to generate IO pad tables

Refactor the IO pad tables into macro tables so that they can be reused to generate pinctrl pin descriptors. Also add a name field which is needed by pinctrl. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 233 ++-- 1 file changed, 127

[PATCH v2 5/7] dt-bindings: Add Tegra PMC pad configuration bindings

: Aapo Vienamo Acked-by: Jon Hunter --- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 +++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 3 files changed, 197 insertions

[PATCH v2 6/7] soc/tegra: pmc: Remove public pad voltage APIs

igned-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 17 - include/soc/tegra/pmc.h | 13 - 2 files changed, 8 insertions(+), 22 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index f68dbfa..8926831 100644 --- a/drivers/soc/tegra/pmc.c

[PATCH v2 7/7] soc/tegra: pmc: Implement pad configuration via pinctrl

Register a pinctrl device and implement get and set functions for PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 187 +++- 1 file changed, 185 insertions(+), 2 deletions

[PATCH v5 0/4] Multiplex sdmmc low jitter clock path

mux_non_lj_idx[] const - Make tegra_clk_sdmmc_mux_ops static - Fix the includes for fence_udelay() in a separate patch v2: - Fix the type compatibility error on do_div Aapo Vienamo (1): clk: tegra: Fix includes required by fence_udelay() Peter De Schrijver (1): clk: tegra

[PATCH v5 2/4] clk: tegra: refactor 7.1 div calculation

From: Peter De Schrijver Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-divider.c | 30

[PATCH v5 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

From: Peter De-Schrijver These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-id.h | 2

[PATCH v5 3/4] clk: tegra: Add sdmmc mux divider clock

will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile| 1 + drivers/clk/tegra/clk-sdmmc-mux.c | 249

[PATCH v5 1/4] clk: tegra: Fix includes required by fence_udelay()

Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e1f8846

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

8 at 05:17:05PM +0100, Jon Hunter wrote: > >>>> > >>>> On 09/07/18 17:38, Aapo Vienamo wrote: > >>>>> From: Peter De Schrijver > >>>>> > >>>>> Move this to a separate file so it can be used to calculate the sdmmc > &

Re: [PATCH v2 3/7] soc/tegra: pmc: Implement tegra_io_pad_is_powered()

On Wed, 11 Jul 2018 16:26:42 +0100 Jon Hunter wrote: > On 11/07/18 16:23, Jon Hunter wrote: > > > > On 11/07/18 15:01, Aapo Vienamo wrote: > >> Implement a function to query whether a pad is in deep power down mode. > > Can you elaborate on why this public func

[PATCH v6 3/4] clk: tegra: Add sdmmc mux divider clock

will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile| 1 + drivers/clk/tegra/clk-sdmmc-mux.c | 251

[PATCH v6 2/4] clk: tegra: Refactor fractional divider calculation

From: Peter De Schrijver Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver Acked-by: Jon Hunter --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk

[PATCH v6 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

From: Peter De-Schrijver These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/clk-id.h | 2

[PATCH v6 0/4] Multiplex sdmmc low jitter clock path

files - Make mux_lj_idx[] and mux_non_lj_idx[] const - Make tegra_clk_sdmmc_mux_ops static - Fix the includes for fence_udelay() in a separate patch v2: - Fix the type compatibility error on do_div Aapo Vienamo (1): clk: tegra: Fix includes required by fence_udelay

[PATCH v6 1/4] clk: tegra: Fix includes required by fence_udelay()

Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver Acked-by: Jon Hunter --- drivers/clk/tegra/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra

[PATCH v3 0/7] Tegra PMC pinctrl pad configuration

c pad voltage configuration APIs - Check return value of tegra_io_pad_find() in tegra_io_pad_pinconf_get()/_set() Aapo Vienamo (7): soc/tegra: pmc: Fix pad voltage configuration for Tegra186 soc/tegra: pmc: Factor out DPD register bit calculation soc/tegra: pmc: Impl

[PATCH v3 4/7] soc/tegra: pmc: Use X macro to generate IO pad tables

Refactor the IO pad tables into macro tables so that they can be reused to generate pinctrl pin descriptors. Also add a name field which is needed by pinctrl. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 233 ++-- 1 file changed, 127

[PATCH v3 7/7] soc/tegra: pmc: Implement pad configuration via pinctrl

Register a pinctrl device and implement get and set functions for PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 187 +++- 1 file changed, 185 insertions(+), 2 deletions

[PATCH v3 2/7] soc/tegra: pmc: Factor out DPD register bit calculation

Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 20 +--- 1 file changed, 17 insertions(+), 3

[PATCH v3 3/7] soc/tegra: pmc: Implement tegra_io_pad_is_powered()

Implement a function to query whether a pad is in deep power down mode. This will is needed by the pinctrl callbacks. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b

[PATCH v3 6/7] soc/tegra: pmc: Remove public pad voltage APIs

igned-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 17 - include/soc/tegra/pmc.h | 19 --- 2 files changed, 8 insertions(+), 28 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 38cb915..7d3c3de 100644

[PATCH v3 5/7] dt-bindings: Add Tegra PMC pad configuration bindings

: Aapo Vienamo Acked-by: Jon Hunter --- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 84 +++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 95 ++ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 3 files changed, 197 insertions

[PATCH v3 1/7] soc/tegra: pmc: Fix pad voltage configuration for Tegra186

Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc

[PATCH 05/40] soc/tegra: pmc: Fix pad voltage configuration for Tegra186

Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc

[PATCH 01/40] dt-bindings: Add Tegra PMC pad configuration bindings

-off-by: Aapo Vienamo Acked-by: Jon Hunter Reviewed-by: Rob Herring --- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 92 ++ .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 103 + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 18 3 files

[PATCH 03/40] dt-bindings: Add Tegra SDHCI pad pdpu offset bindings

Add bindings documentation for pad pull up and pull down offset values to be programmed before executing automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 36 ++ 1 file changed, 36 insertions

[PATCH 06/40] soc/tegra: pmc: Factor out DPD register bit calculation

Factor out the the code to calculate the correct DPD register and bit number for a given pad. This logic will be needed to query the status register. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 20 +--- 1 file changed, 17 insertions(+), 3

[PATCH 07/40] soc/tegra: pmc: Implement tegra_io_pad_is_powered()

Implement a function to query whether a pad is in deep power down mode. This will is needed by the pinctrl callbacks. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b

[PATCH 08/40] soc/tegra: pmc: Use X macro to generate IO pad tables

Refactor the IO pad tables into macro tables so that they can be reused to generate pinctrl pin descriptors. Also add a name field which is needed by pinctrl. Signed-off-by: Aapo Vienamo --- drivers/soc/tegra/pmc.c | 233 ++-- 1 file changed, 127

[PATCH 09/40] soc/tegra: pmc: Remove public pad voltage APIs

igned-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 17 - include/soc/tegra/pmc.h | 19 --- 2 files changed, 8 insertions(+), 28 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 38cb915..979f4b4 100644

[PATCH 14/40] mmc: tegra: Set calibration pad voltage reference

Configure the voltage reference used by the automatic pad drive strength calibration procedure. The value is a magic number from the TRM. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 56 +- 1 file changed, 33 insertions(+), 23

[PATCH 13/40] mmc: tegra: Poll for calibration completion

Implement polling with 10 ms timeout for automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci

[PATCH 15/40] mmc: tegra: Power on the calibration pad

Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen

[PATCH 24/40] mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186

Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't set the custom tuning callback used on previous SoC generations. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/driver

[PATCH 10/40] soc/tegra: pmc: Implement pad configuration via pinctrl

Register a pinctrl device and implement get and set functions for PIN_CONFIG_LOW_POWER_MODE and PIN_CONFIG_POWER_SOURCE parameters. Signed-off-by: Aapo Vienamo Acked-by: Jon Hunter --- drivers/soc/tegra/pmc.c | 187 +++- 1 file changed, 185

[PATCH 16/40] mmc: tegra: Disable card clock during pad calibration

Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host

[PATCH 12/40] mmc: tegra: Reconfigure pad voltages during voltage switching

for Tegra210 and Tegra186. The pad configuration is done in the mmc callback because the order of pad reconfiguration and sdhci voltage switch depend on the voltage to which the transition occurs. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 138

[PATCH 11/40] mmc: sdhci: Add a quirk to skip clearing the transfer mode register on tuning

Add SDHCI_QUIRK2_TUNE_SKIP_XFERRMODE_REG_PROG to skip programming the SDHCI_TRANSFER_MODE in sdhci_set_transfer_mode() if tuning command is being sent. On Tegra210 and Tegra186 the tuning sequence hangs if the SDHCI transfer mode register is touched. Signed-off-by: Aapo Vienamo --- drivers/mmc

[PATCH 17/40] mmc: tegra: Program pad autocal offsets from dt

Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 152 - 1 file changed, 151 insertions

[PATCH 18/40] mmc: tegra: Perform pad calibration after voltage switch

Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c in

[PATCH 19/40] mmc: tegra: Enable pad calibration on Tegra210 and Tegra186

Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci

[PATCH 25/40] mmc: sdhci: Add a quirk to disable card clock during tuning

. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci.c | 15 +++ drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 04dc443..166b16f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host

[PATCH 22/40] mmc: tegra: Configure default tap values

Set the default inbound timing adjustment tap value on reset and on non-tunable modes. The default tap value is not programmed on tunable modes because the tuning sequence is used instead to determine the tap value. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 131

[PATCH 20/40] mmc: tegra: Add a workaround for tap value change glitch

Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci

[PATCH 21/40] mmc: tegra: Parse default trim and tap from dt

Parse the default inbound and outbound sampling trimmer values from the device tree. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index

[PATCH 26/40] mmc: tegra: Enable workaround for tuning transfer mode bug

Set SDHCI_QUIRK2_TUNE_SKIP_XFERMODE_REG_PROG on Tegra210 and Tegra186. This prevents the controller from hanging during tuning. This bug does not seem to be documented but it's handled in a similar way in the downstream kernel. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.

[PATCH 23/40] mmc: tegra: Configure default trim value on reset

Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike the outbound tap value this does not depend on the signaling mode and needs to be only programmed once. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion

[PATCH 30/40] arm64: dts: Add Tegra210 sdmmc pinctrl voltage states

Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra210. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 27 +++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts

[PATCH 27/40] mmc: tegra: Set SDHCI_QUIRK2_TUNE_DIS_CARD_CLK on Tegra210

This prevents a possible hardware hang during tuning. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 6daee7e..2e07dcd 100644 --- a/drivers

[PATCH 32/40] arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V

applies. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi

[PATCH 02/40] dt-bindings: mmc: tegra: Add pad voltage control properties

Document the pinctrl bindings used by the SDHCI driver to reconfigure pad voltages on controllers supporting multiple voltage levels. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen Reviewed-by: Rob Herring --- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 22

[PATCH 34/40] arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1

Allow sdmmc1 to set the signaling voltage to 1.8 V in order to support faster signaling modes. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts

[PATCH 28/40] mmc: tegra: Enable UHS and HS200 modes for Tegra210

Set nvquirks to enable higher speed modes. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2e07dcd..03a6bf7 100644 --- a/drivers/mmc/host

[PATCH 31/40] arm64: dts: Add Tegra186 sdmmc pinctrl voltage states

Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra186. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 40 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot

[PATCH 33/40] arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply

On p2180 sdmmc4 is powered from a fixed 1.8 V regulator. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia

[PATCH 00/40] Tegra SDHCI add support for HS200 and UHS signaling

- Only call udelay(1) on enable in tegra_sdhci_configure_cal_pad() - Add nvidia, prefix to pad autocal offset dt props in the example See the original patch sets for earlier changelogs. Aapo Vienamo (40): dt-bindings: Add Tegra PMC pad configuration bindings dt-bindings: mmc: tegra: Add pad voltage con

[PATCH 29/40] mmc: tegra: Enable UHS and HS200 modes for Tegra186

Set nvquirks to enable higher speed modes. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 03a6bf7..7f1ac4a 100644 --- a/drivers/mmc/host

[PATCH 39/40] arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4

Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by setting the assigned-clocks device tree properties. pllc4 offer better jitter performance and should be used with higher speed modes like HS200 and HS400. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi

[PATCH 36/40] arm64: dts: tegra210: Add sdmmc pad auto calibration offsets

Add the calibration offset properties used for automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts

[PATCH 40/40] arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4

Use assigned-clock properties to configure pllc4 as the parent clock for sdmmc4 on Tegra210. pllc4 offers better jitter perfomance than the default pllp and is required by HS200 and HS400 modes. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 1 file

[PATCH 35/40] arm64: dts: tegra186: Add sdmmc pad auto calibration offsets

Add the calibration offset properties used for automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 20 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot

[PATCH 37/40] arm64: dts: tegra210: Add SDHCI tap and trim values

Add SDHCI inbound and outbound SDHCI sampling trimmer values for Tegra210. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi

[PATCH 38/40] arm64: dts: tegra186: Add SDHCI tap and trim values

Add SDHCI inbound and outbound SDHCI sampling trimmer values for Tegra186. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi

[PATCH 04/40] dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values

Document the Tegra SDHCI inbound and outbound sampling trimmer values. Signed-off-by: Aapo Vienamo --- .../devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b

[PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186

Hi all, This series implements support for HS400 signaling on Tegra210 and Tegra186. This includes programming the DQS trimmer values, implementing enhanced strobe and HS400 delay line calibration. This series depends on the "Tegra SDHCI add support for HS200 and UHS signaling" ser

[PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI

Document HS400 DQS trim value device tree property. Signed-off-by: Aapo Vienamo --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree

[PATCH 2/8] mmc: tegra: Parse and program DQS trim value

Parse and program the HS400 DQS trim value from dt. Program a fallback value in case the property is missing. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 32 +--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host

[PATCH 4/8] mmc: tegra: Implement HS400 delay line calibration

Implement HS400 specific delay line calibration procedure. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 29 + 1 file changed, 29 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index d81143b..d0b68b7

[PATCH 3/8] mmc: tegra: Implement HS400 enhanced strobe

Implement HS400 enhanced strobe. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci-tegra.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 426f7ea..d81143b 100644 --- a/drivers/mmc/host/sdhci

[PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value

Add the HS400 DQS trim value for Tegra186 SDMMC4. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6e9ef26..9e07bc6 100644 --- a

[PATCH 6/8] arm64: dts: tegra210: Add SDMMC4 DQS trim value

Add the HS400 DQS trim value for Tegra210 SDMMC4. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 14da98a..f8e5f09 100644 --- a

[PATCH 7/8] arm64: dts: tegra186: Enable HS400

Enable HS400 signaling on Tegra186 SDMMC4 controller. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9e07bc6..2f3c8e2 100644

[PATCH 8/8] arm64: dts: tegra210: Enable HS400

Enable HS400 signaling on Tegra210 SDMMC4 controller. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f8e5f09..8fe47d6 100644

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