Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support

On Tue, Apr 17, 2018 at 1:38 AM, Alan Kao wrote: > +static inline void write_counter(int idx, u64 value) > +{ > + /* currently not supported */ > +} CSR writes can be emulated: https://github.com/riscv/riscv-pk/pull/98 Or at least write_counter() should have BUG()

Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support

On Tue, Apr 17, 2018 at 1:38 AM, Alan Kao wrote: > +static inline void write_counter(int idx, u64 value) > +{ > + /* currently not supported */ > +} CSR writes can be emulated: https://github.com/riscv/riscv-pk/pull/98 Or at least write_counter() should have BUG() or WARN_ONCE() or

Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support

This does not compile: /freedom-u-sdk/linux/arch/riscv/kernel/perf_event.c: In function 'riscv_pmu_stop': /freedom-u-sdk/linux/arch/riscv/kernel/perf_event.c:258:12: error: 'const struct riscv_pmu' has no member named 'read' riscv_pmu->read(event); ^~

Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support

This does not compile: /freedom-u-sdk/linux/arch/riscv/kernel/perf_event.c: In function 'riscv_pmu_stop': /freedom-u-sdk/linux/arch/riscv/kernel/perf_event.c:258:12: error: 'const struct riscv_pmu' has no member named 'read' riscv_pmu->read(event); ^~

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

Alan, I merged SBI emulation for perf counters and config: https://github.com/riscv/riscv-pk/pull/98 You should be able to write these CSRs. Thanks, Alex On Mon, Apr 9, 2018 at 12:07 AM, Alan Kao wrote: > On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

Alan, I merged SBI emulation for perf counters and config: https://github.com/riscv/riscv-pk/pull/98 You should be able to write these CSRs. Thanks, Alex On Mon, Apr 9, 2018 at 12:07 AM, Alan Kao wrote: > On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote: >> On Mon, 26 Mar 2018

Re: [PATCH v2 2/2] perf: riscv: Add Document for Future Porting Guide

Doc fixes: diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt index a3e930e..ae90a5e 100644 --- a/Documentation/riscv/pmu.txt +++ b/Documentation/riscv/pmu.txt @@ -20,7 +20,7 @@ the lack of the following general architectural performance monitoring features: *

Re: [PATCH v2 2/2] perf: riscv: Add Document for Future Porting Guide

Doc fixes: diff --git a/Documentation/riscv/pmu.txt b/Documentation/riscv/pmu.txt index a3e930e..ae90a5e 100644 --- a/Documentation/riscv/pmu.txt +++ b/Documentation/riscv/pmu.txt @@ -20,7 +20,7 @@ the lack of the following general architectural performance monitoring features: *

Re: [PATCH v2 1/2] perf: riscv: preliminary RISC-V support

This works for cycle and instruction counts. Alex On Mon, Apr 2, 2018 at 5:31 AM, Alan Kao wrote: > > This patch provide a basic PMU, riscv_base_pmu, which supports two > general hardware event, instructions and cycles. Furthermore, this > PMU serves as a reference

Re: [PATCH v2 1/2] perf: riscv: preliminary RISC-V support

This works for cycle and instruction counts. Alex On Mon, Apr 2, 2018 at 5:31 AM, Alan Kao wrote: > > This patch provide a basic PMU, riscv_base_pmu, which supports two > general hardware event, instructions and cycles. Furthermore, this > PMU serves as a reference implementation to ease the

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

; Hi Alex, > > I'm appreciated for your reply and tests. > > On Wed, Mar 28, 2018 at 03:58:41PM -0700, Alex Solomatnikov wrote: >> Did you test this code? > > I did test this patch on QEMU's virt model with multi-hart, which is the only > RISC-V machine I have for

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

preciated for your reply and tests. > > On Wed, Mar 28, 2018 at 03:58:41PM -0700, Alex Solomatnikov wrote: >> Did you test this code? > > I did test this patch on QEMU's virt model with multi-hart, which is the only > RISC-V machine I have for now. But as I mentioned in > ht