On Fri, Feb 15, 2019 at 2:53 AM Shubhrajyoti Datta
wrote:
>
> HI Alex,
>
> Thanks for the patch.
>
> On Fri, Feb 1, 2019 at 4:22 AM wrote:
> >
> > From: Alex Williams
> >
> > Under certain conditions, Cadence's I2C controller's transfer_size
From: Alex Williams
Under certain conditions, Cadence's I2C controller's transfer_size
register will roll over and generate invalid read transactions. Before
this change, the ISR relied solely on the RXDV bit to determine when to
write more data to the user's buffer. The invalid
From: Alex Williams
Now the DMA engine is free to float elsewhere in the system map.
Signed-off-by: Alex Williams
---
Documentation/devicetree/bindings/net/nixge.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net
From: Alex Williams
The DMA engine is a separate entity altogether, and this allows the DMA
controller's address to float elsewhere in the FPGA's map.
Signed-off-by: Alex Williams
---
drivers/net/ethernet/ni/nixge.c | 74 -
1 file changed, 58
From: Alex Williams
Now the DMA engine is free to float elsewhere in the system map.
Signed-off-by: Alex Williams
---
Documentation/devicetree/bindings/net/nixge.txt | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/net
Hi all,
We're writing a device driver and having some difficulty matching a
subsystem to the driver/device properties. Can anyone help with
direction?
These are some basic properties:
1) Device is used to carry generic data to/from userspace. It's a pair
of dumb streams with one sink and one s
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