Hi Gabriel
On 01/06/2017 02:59 PM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez
---
In commit header, "stm32f7" is not usefull.
Hi Gabriel
On 01/06/2017 02:59 PM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez
---
In commit header, "stm32f7" is not usefull.
arch/arm/boot/dts/stm32f746.dtsi | 29
On 01/09/2017 08:33 PM, Stephen Boyd wrote:
On 01/09, Alexandre Torgue wrote:
Hi Stephen,
On 12/22/2016 01:10 AM, Stephen Boyd wrote:
On 12/13, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez <gabriel.fernan...@st.com>
Creation of dt include file for specific stm32f4
On 01/09/2017 08:33 PM, Stephen Boyd wrote:
On 01/09, Alexandre Torgue wrote:
Hi Stephen,
On 12/22/2016 01:10 AM, Stephen Boyd wrote:
On 12/13, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
Creation of dt include file for specific stm32f4 clocks.
These specific clocks
Hi Stephen,
On 12/22/2016 01:10 AM, Stephen Boyd wrote:
On 12/13, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
Creation of dt include file for specific stm32f4 clocks.
These specific clocks are not derived from system clock (SYSCLOCK)
We should use index
Hi Stephen,
On 12/22/2016 01:10 AM, Stephen Boyd wrote:
On 12/13, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
Creation of dt include file for specific stm32f4 clocks.
These specific clocks are not derived from system clock (SYSCLOCK)
We should use index 1 to use these clocks in
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
ADC driver depends on REGULATOR and IIO that are not yet selected.
Current hardware boards (like stm32f429i-eval) is using fixed
regulators.
Signed-off-by: Fabrice Gasnier
---
arch/arm/configs/stm32_defconfig |
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
ADC driver depends on REGULATOR and IIO that are not yet selected.
Current hardware boards (like stm32f429i-eval) is using fixed
regulators.
Signed-off-by: Fabrice Gasnier
---
arch/arm/configs/stm32_defconfig | 5 +
1 file
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
Enable analog to digital converter on stm32f429i-eval board.
It has on-board potentimeter wired to ADC3 in8 analog pin and
uses fixed regulator to provide reference voltage.
Signed-off-by: Fabrice Gasnier
---
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
Enable analog to digital converter on stm32f429i-eval board.
It has on-board potentimeter wired to ADC3 in8 analog pin and
uses fixed regulator to provide reference voltage.
Signed-off-by: Fabrice Gasnier
---
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
Add ADC support & pinctrl analog phandle (adc3_in8) to stm32f429.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32f429.dtsi | 49
1 file changed, 49
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
Add ADC support & pinctrl analog phandle (adc3_in8) to stm32f429.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32f429.dtsi | 49
1 file changed, 49 insertions(+)
diff --git
Hi Bruno,
On 11/18/2016 04:10 PM, Bruno Meirelles Herrera wrote:
Including new STM32 maintainer. Rebased at stm32-dt-for-v4.10-1 and
stm32-dt-for-v4.10-2 branches. It fix the port/pin initialization in
case boot-loader does not configure/initialize the pins.
Fixing line wrapping from last patch
Hi Bruno,
On 11/18/2016 04:10 PM, Bruno Meirelles Herrera wrote:
Including new STM32 maintainer. Rebased at stm32-dt-for-v4.10-1 and
stm32-dt-for-v4.10-2 branches. It fix the port/pin initialization in
case boot-loader does not configure/initialize the pins.
Fixing line wrapping from last patch
Hi Bruno,
On 11/18/2016 03:58 PM, Bruno Meirelles Herrera wrote:
From: Bruno Herrera
This patch fix memory size to support 16MB of external SDRAM.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f469-disco.dts | 2 +-
1 file changed, 1
Hi Bruno,
On 11/18/2016 03:58 PM, Bruno Meirelles Herrera wrote:
From: Bruno Herrera
This patch fix memory size to support 16MB of external SDRAM.
Signed-off-by: Bruno Herrera
---
arch/arm/boot/dts/stm32f469-disco.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
Can you please add a commit message.
Thx in advance
Alex
---
arch/arm/configs/stm32_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
Can you please add a commit message.
Thx in advance
Alex
---
arch/arm/configs/stm32_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
Can you please add a commit message.
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
Can you please add a commit message.
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: Patrice Chotard
Signed-off-by: M'boumba Cedric Madianga
Please Add a commit message.
---
arch/arm/boot/dts/stm32f429.dtsi | 23 +++
1
Hi Cedric,
On 12/12/2016 05:15 PM, M'boumba Cedric Madianga wrote:
Signed-off-by: Patrice Chotard
Signed-off-by: M'boumba Cedric Madianga
Please Add a commit message.
---
arch/arm/boot/dts/stm32f429.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git
Hi
On 12/07/2016 04:57 AM, Jie Deng wrote:
This series provides the support for 25/40/50/100 GbE
devices using Synopsys DWC Enterprise Ethernet (XLGMAC).
Can you explain which GMAC are you targeted ?
A driver which support some Synopsys GMAC IP already exists. It support
GMAC 3.5, 3.7, 4.0,
Hi
On 12/07/2016 04:57 AM, Jie Deng wrote:
This series provides the support for 25/40/50/100 GbE
devices using Synopsys DWC Enterprise Ethernet (XLGMAC).
Can you explain which GMAC are you targeted ?
A driver which support some Synopsys GMAC IP already exists. It support
GMAC 3.5, 3.7, 4.0,
Hi David,
On 12/08/2016 04:19 PM, David Miller wrote:
From: Alexandre Torgue <alexandre.tor...@st.com>
Date: Thu, 8 Dec 2016 11:44:35 +0100
Acked-by: Alexandre Torgue <alexandre.torgue@stcom>
Typo in your email.
I would suggest that you put this into an editor macro or
simi
Hi David,
On 12/08/2016 04:19 PM, David Miller wrote:
From: Alexandre Torgue
Date: Thu, 8 Dec 2016 11:44:35 +0100
Acked-by: Alexandre Torgue
Typo in your email.
I would suggest that you put this into an editor macro or
similar in order to avoid such typos in the future. That's
what
s does a kzalloc dma_cfg.
Return an error if no DMA configuration is found, that way
we can assume that the DMA configuration always exists.
Signed-off-by: Niklas Cassel <niklas.cas...@axis.com>
Acked-by: Alexandre Torgue <alexandre.torgue@stcom>
---
drivers/net/ethernet/stmicro/stmmac/
an error if no DMA configuration is found, that way
we can assume that the DMA configuration always exists.
Signed-off-by: Niklas Cassel
Acked-by: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
The driver currently always sets the PBLx8/PBLx4 bit, which means that
the pbl values configured via the pbl/txpbl/rxpbl DT properties are
always multiplied by 8/4 in the hardware.
In order to
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
The driver currently always sets the PBLx8/PBLx4 bit, which means that
the pbl values configured via the pbl/txpbl/rxpbl DT properties are
always multiplied by 8/4 in the hardware.
In order to allow the DT to
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
GMAC and newer supports independent programmable burst lengths for
DMA tx/rx. Add new optional devicetree properties representing this.
To be backwards compatible, snps,pbl will still be valid,
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
GMAC and newer supports independent programmable burst lengths for
DMA tx/rx. Add new optional devicetree properties representing this.
To be backwards compatible, snps,pbl will still be valid, but
Hi
On 12/08/2016 10:46 AM, Niklas Cassel wrote:
On 12/08/2016 10:02 AM, Alexandre Torgue wrote:
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel <niklas.cas...@axis.com>
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
cha
Hi
On 12/08/2016 10:46 AM, Niklas Cassel wrote:
On 12/08/2016 10:02 AM, Alexandre Torgue wrote:
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT bindin
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
DMA_BUS_MODE_RPBL_MASK is really 6 bits,
just like DMA_BUS_MODE_PBL_MASK.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 2 +-
1
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
DMA_BUS_MODE_RPBL_MASK is really 6 bits,
just like DMA_BUS_MODE_PBL_MASK.
Signed-off-by: Niklas Cassel
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if
Hi Niklas
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
commit 64c3b252e9fc ("net: stmmac: fixed the pbl setting with DT")
changed the parsing of the DT binding.
Before 64c3b252e9fc, snps,fixed-burst and snps,mixed-burst were parsed
regardless if the property snps,pbl
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: Niklas Cassel
Thanks for this
Hi Niklas,
On 12/07/2016 03:20 PM, Niklas Cassel wrote:
From: Niklas Cassel
Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: Niklas Cassel
Thanks for this patch. You can add my Acked-by.
Regards
Alex
---
Hi Cedric,
On 12/08/2016 09:26 AM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
Can you change the commit header by: ARM: dts: stm32: Add I2C1 support
Hi Cedric,
On 12/08/2016 09:26 AM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/boot/dts/stm32429i-eval.dts | 6 ++
1 file changed, 6 insertions(+)
Can you change the commit header by: ARM: dts: stm32: Add I2C1 support
for STM32429 eval board
Hi Cedric,
On 12/08/2016 09:26 AM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/configs/stm32_defconfig | 3 +++
1 file changed, 3 insertions(+)
Can you change the commit header by ARM: configs: stm32: Add I2C support
Thx
Hi Cedric,
On 12/08/2016 09:26 AM, M'boumba Cedric Madianga wrote:
Signed-off-by: M'boumba Cedric Madianga
---
arch/arm/configs/stm32_defconfig | 3 +++
1 file changed, 3 insertions(+)
Can you change the commit header by ARM: configs: stm32: Add I2C support
Thx
alex
diff --git
Hi Lee,
On 12/06/2016 10:48 AM, Lee Jones wrote:
On Mon, 05 Dec 2016, Alexandre Torgue wrote:
On 12/02/2016 02:22 PM, Lee Jones wrote:
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469
Hi Lee,
On 12/06/2016 10:48 AM, Lee Jones wrote:
On Mon, 05 Dec 2016, Alexandre Torgue wrote:
On 12/02/2016 02:22 PM, Lee Jones wrote:
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469
Hi,
On 12/02/2016 02:22 PM, Lee Jones wrote:
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use
Hi,
On 12/02/2016 02:22 PM, Lee Jones wrote:
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use
Hi Pavel and Peppe,
On 12/02/2016 02:51 PM, Giuseppe CAVALLARO wrote:
On 12/2/2016 1:32 PM, Pavel Machek wrote:
Hi!
Well, if you have a workload that sends and receive packets, it tends
to work ok, as you do tx_clean() in stmmac_poll(). My workload is not
like that -- it is "sending packets
Hi Pavel and Peppe,
On 12/02/2016 02:51 PM, Giuseppe CAVALLARO wrote:
On 12/2/2016 1:32 PM, Pavel Machek wrote:
Hi!
Well, if you have a workload that sends and receive packets, it tends
to work ok, as you do tx_clean() in stmmac_poll(). My workload is not
like that -- it is "sending packets
Hi Pavel,
On 11/28/2016 01:17 PM, Pavel Machek wrote:
Remove code duplication getting basic descriptors.
I agree with your patch, it will make code easier to understand.
After fix kbuild issue you can add my Acked-by;
Regards
Alex
Signed-off-by: Pavel Machek
diff --git
Hi Pavel,
On 11/28/2016 01:17 PM, Pavel Machek wrote:
Remove code duplication getting basic descriptors.
I agree with your patch, it will make code easier to understand.
After fix kbuild issue you can add my Acked-by;
Regards
Alex
Signed-off-by: Pavel Machek
diff --git
Hi Benjamin,
On 12/02/2016 11:17 AM, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use parameters to describe hardware
Hi Benjamin,
On 12/02/2016 11:17 AM, Benjamin Gaignard wrote:
Add general purpose timers and it sub-nodes into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
version 3:
- use "st,stm32-timer-trigger" in DT
version 2:
- use parameters to describe hardware
Hi David and Niklas,
On 11/28/2016 05:29 PM, David Miller wrote:
From: Niklas Cassel
Date: Thu, 24 Nov 2016 15:36:33 +0100
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with
Hi David and Niklas,
On 11/28/2016 05:29 PM, David Miller wrote:
From: Niklas Cassel
Date: Thu, 24 Nov 2016 15:36:33 +0100
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default.
Hi Niklas
On 11/25/2016 01:14 PM, Niklas Cassel wrote:
On 11/25/2016 01:10 PM, Niklas Cassel wrote:
On 11/24/2016 07:11 PM, Alexandre Torgue wrote:
Hi Niklas,
Hello Alexandre
On 11/24/2016 03:36 PM, Niklas Cassel wrote:
From: Niklas Cassel <niklas.cas...@axis.com>
The dwmac4
Hi Niklas
On 11/25/2016 01:14 PM, Niklas Cassel wrote:
On 11/25/2016 01:10 PM, Niklas Cassel wrote:
On 11/24/2016 07:11 PM, Alexandre Torgue wrote:
Hi Niklas,
Hello Alexandre
On 11/24/2016 03:36 PM, Niklas Cassel wrote:
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number
Hi Niklas,
On 11/24/2016 03:36 PM, Niklas Cassel wrote:
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default. For these IPs, the bitfield TXQEN is R/W.
Hi Niklas,
On 11/24/2016 03:36 PM, Niklas Cassel wrote:
From: Niklas Cassel
The dwmac4 IP can synthesized with 1-8 number of tx queues.
On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled
by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0.
Hi Niklas,
On 11/23/2016 03:25 PM, Niklas Cassel wrote:
From: Niklas Cassel
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Previously, when specifying
Hi Niklas,
On 11/23/2016 03:25 PM, Niklas Cassel wrote:
From: Niklas Cassel
devicetree binding for stmmac states:
- compatible: Should be "snps,dwmac-", "snps,dwmac"
For backwards compatibility: "st,spear600-gmac" is also supported.
Previously, when specifying "snps,dwmac-4.10a",
Hi Niklas,
On 11/23/2016 03:24 PM, Niklas Cassel wrote:
From: Niklas Cassel
snps,tso was previously placed under AXI BUS Mode parameters,
suggesting that the property should be in the stmmac-axi-config node.
TSO (TCP Segmentation Offloading) has nothing to do with AXI
Hi Niklas,
On 11/23/2016 03:24 PM, Niklas Cassel wrote:
From: Niklas Cassel
snps,tso was previously placed under AXI BUS Mode parameters,
suggesting that the property should be in the stmmac-axi-config node.
TSO (TCP Segmentation Offloading) has nothing to do with AXI BUS Mode
parameters,
Hi Benjamin,
On 11/22/2016 05:13 PM, Benjamin Gaignard wrote:
Add timers MFD and childs into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard
If you have to send a v2 for this series please change commit
Hi Benjamin,
On 11/22/2016 05:13 PM, Benjamin Gaignard wrote:
Add timers MFD and childs into DT for stm32f4.
Define and enable pwm1 and pwm3 for stm32f469 discovery board
Signed-off-by: Benjamin Gaignard
If you have to send a v2 for this series please change commit header by:
"ARM: dts:
Gabriel,
On 11/04/2016 09:52 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds lsi / lse oscillators. These clocks can be use by
RTC clocks.
The clock drivers needs to disable the power domain write protection using
syscon / regmap to enable
Gabriel,
On 11/04/2016 09:52 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds lsi / lse oscillators. These clocks can be use by
RTC clocks.
The clock drivers needs to disable the power domain write protection using
syscon / regmap to enable these clocks.
Is it
Hi Gabriel,
On 10/14/2016 11:18 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds the QSPI clock for stm32f469 discovery board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32f469-disco.dts | 4
Hi Gabriel,
On 10/14/2016 11:18 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
This patch adds the QSPI clock for stm32f469 discovery board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stm32f469-disco.dts | 4
1 file changed, 4 insertions(+)
diff --git
Hi Gabriel,
On 10/14/2016 11:18 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
v2:
- rename compatible property "st,stm32f46xx-rcc" into "st,stm32f469-rcc"
- cosmetic: remove bad copy/paste
This patch-set introduce RTC and QSPI clocks for STM32F4 socs
Hi Gabriel,
On 10/14/2016 11:18 AM, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
v2:
- rename compatible property "st,stm32f46xx-rcc" into "st,stm32f469-rcc"
- cosmetic: remove bad copy/paste
This patch-set introduce RTC and QSPI clocks for STM32F4 socs
RTC clock has 3 parents
| 97 +++---
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c | 9 +-
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h | 72
11 files changed, 260 insertions(+), 152 deletions(-)
For the series:
Acked-by: Alexandre Torgue <alexandre.tor...@st.com>
Thanks
Alex
| 97 +++---
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c | 9 +-
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.h | 72
11 files changed, 260 insertions(+), 152 deletions(-)
For the series:
Acked-by: Alexandre Torgue
Thanks
Alex
Hi Greg,
On 10/23/2016 11:54 AM, kbuild test robot wrote:
Hi Alexandre,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 0c2b6dc4fd4fa13796b319aae969a009f03222c6
commit: 3489187204eb75e5635d8836babfd0a18be613f4
Hi Greg,
On 10/23/2016 11:54 AM, kbuild test robot wrote:
Hi Alexandre,
First bad commit (maybe != root cause):
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 0c2b6dc4fd4fa13796b319aae969a009f03222c6
commit: 3489187204eb75e5635d8836babfd0a18be613f4
Hi,
Currently 4.9-rc1 is not booting correctly on STM32F4.
By adding gpios irqs support to stm32 pinctrl, a dependency has been
added between pinctrl stm32 and stm32f4 device tree (my mistake).
This series breaks this dependency and has to be taken on 4.9_rcs.
Regards
Alex
Alexandre
Hi,
Currently 4.9-rc1 is not booting correctly on STM32F4.
By adding gpios irqs support to stm32 pinctrl, a dependency has been
added between pinctrl stm32 and stm32f4 device tree (my mistake).
This series breaks this dependency and has to be taken on 4.9_rcs.
Regards
Alex
Alexandre
stm32 pinctrl driver could be probed even if no interrupt controller
is defined to manage gpio irqs. Entries related to gpio irq management
are moved to optional.
Signed-off-by: Alexandre TORGUE <alexandre.tor...@st.com>
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinct
stm32 pinctrl driver could be probed even if no interrupt controller
is defined to manage gpio irqs. Entries related to gpio irq management
are moved to optional.
Signed-off-by: Alexandre TORGUE
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
b/Documentation
This patch allows to probe stm32 pinctrl driver even if no interrupt
controller is defined to manage gpio irqs.
Signed-off-by: Alexandre TORGUE <alexandre.tor...@st.com>
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 200667f..efc4371
This patch allows to probe stm32 pinctrl driver even if no interrupt
controller is defined to manage gpio irqs.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c
b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 200667f..efc4371 100644
--- a/drivers/pinctrl/stm32
Hi Radoslaw,
I add Gabriel in the discussion. Gabriel is updating PLL management for
STM32F429.
Regards
Alex
On 10/10/2016 12:31 PM, Daniel Thompson wrote:
On 10/10/16 10:56, Radosław Pietrzyk wrote:
Hi,
all plls have the same clock parent which is after a main divider.
Currently the
Hi Radoslaw,
I add Gabriel in the discussion. Gabriel is updating PLL management for
STM32F429.
Regards
Alex
On 10/10/2016 12:31 PM, Daniel Thompson wrote:
On 10/10/16 10:56, Radosław Pietrzyk wrote:
Hi,
all plls have the same clock parent which is after a main divider.
Currently the
This driver is for the on-chip Serial Controller on
I sent same kind of patch this morning (but mine have a bad copy paste).
I will abandon my patch.
However for this one:
Acked-by: Alexandre Torgue <alexandre.tor...@st.com>
regards
Alex
he on-chip Serial Controller on
I sent same kind of patch this morning (but mine have a bad copy paste).
I will abandon my patch.
However for this one:
Acked-by: Alexandre Torgue
regards
Alex
Commit-ID: 5a79d596378b65e773d93d00edcb57a33f87ea94
Gitweb: http://git.kernel.org/tip/5a79d596378b65e773d93d00edcb57a33f87ea94
Author: Alexandre TORGUE <alexandre.tor...@st.com>
AuthorDate: Tue, 20 Sep 2016 18:00:59 +0200
Committer: Thomas Gleixner <t...@linutronix.de>
Com
Commit-ID: 5a79d596378b65e773d93d00edcb57a33f87ea94
Gitweb: http://git.kernel.org/tip/5a79d596378b65e773d93d00edcb57a33f87ea94
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:59 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
ARM/dts: Add EXTI
Commit-ID: 47f91519546ce39cceee2c51b0f5045eadc688a9
Gitweb: http://git.kernel.org/tip/47f91519546ce39cceee2c51b0f5045eadc688a9
Author: Alexandre TORGUE <alexandre.tor...@st.com>
AuthorDate: Tue, 20 Sep 2016 18:00:58 +0200
Committer: Thomas Gleixner <t...@linutronix.de>
Com
Commit-ID: 47f91519546ce39cceee2c51b0f5045eadc688a9
Gitweb: http://git.kernel.org/tip/47f91519546ce39cceee2c51b0f5045eadc688a9
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:58 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
ARM/STM32: Select
Commit-ID: e072041688ca73f125719815fa4b0fd23a45152c
Gitweb: http://git.kernel.org/tip/e072041688ca73f125719815fa4b0fd23a45152c
Author: Alexandre TORGUE <alexandre.tor...@st.com>
AuthorDate: Tue, 20 Sep 2016 18:00:57 +0200
Committer: Thomas Gleixner <t...@linutronix.de>
Com
Commit-ID: e072041688ca73f125719815fa4b0fd23a45152c
Gitweb: http://git.kernel.org/tip/e072041688ca73f125719815fa4b0fd23a45152c
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:57 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
drivers/irqchip
Commit-ID: 3027f78bb7243bef28c103507fc857e1471d769d
Gitweb: http://git.kernel.org/tip/3027f78bb7243bef28c103507fc857e1471d769d
Author: Alexandre TORGUE <alexandre.tor...@st.com>
AuthorDate: Tue, 20 Sep 2016 18:00:56 +0200
Committer: Thomas Gleixner <t...@linutronix.de>
Com
Commit-ID: 3027f78bb7243bef28c103507fc857e1471d769d
Gitweb: http://git.kernel.org/tip/3027f78bb7243bef28c103507fc857e1471d769d
Author: Alexandre TORGUE
AuthorDate: Tue, 20 Sep 2016 18:00:56 +0200
Committer: Thomas Gleixner
CommitDate: Wed, 21 Sep 2016 14:13:21 +0200
Documentation/dt
Hi Thomas,
On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
Alexandre,
On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt
Hi Thomas,
On 09/20/2016 10:16 PM, Thomas Gleixner wrote:
Alexandre,
On Tue, 20 Sep 2016, Alexandre TORGUE wrote:
The STM32 external interrupt controller consists of edge detectors that
generate interrupts requests or wake-up events.
Each line can be independently configured as interrupt
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.tor...@st.com>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/
.
Signed-off-by: Maxime Coquelin <mcoquelin.st...@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.tor...@st.com>
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 35df462..1a189d4 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -176,6 +176,14
.
Signed-off-by: Maxime Coquelin
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7f87289..bc62d1f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -264,3 +264,7 @@ config EZNPS_GIC
select IRQ_DOMAIN
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