the driver
does not fully support yet, also the clock part has changed, but it
works like this at least for SD card accesses.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++
1 file changed, 61 insertions(+)
/447512.html
[2]: https://github.com/apritzel/arm-trusted-firmware/commits/allwinner-scpi
Andre Przywara (5):
mailbox: introduce ARM SMC based mailbox
DT: mailbox: add binding doc for the ARM SMC mailbox
arm64: dts: sunxi: add SCPI node to sun50i-a64.dtsi
arm64: dts: sunxi: add SCPI driven
Support for variable frequency clocks is implemented in ARM Trusted
Firmware, which sits in SRAM and waits for SCPI requests.
Add the respective SMC mailbox node and a 512-byte chunk of SRAM to
allow SCPI calls to be handled by the firmware.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts
the driver
does not fully support yet, also the clock part has changed, but it
works like this at least for SD card accesses.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot
/447512.html
[2]: https://github.com/apritzel/arm-trusted-firmware/commits/allwinner-scpi
Andre Przywara (5):
mailbox: introduce ARM SMC based mailbox
DT: mailbox: add binding doc for the ARM SMC mailbox
arm64: dts: sunxi: add SCPI node to sun50i-a64.dtsi
arm64: dts: sunxi: add SCPI driven
The BananaPi M64 is a single board computer with an Allwinner A64 SoC.
In addition to the usual suspects it contains Gigabit Ethernet, 2GB RAM,
an eMMC and a WiFi chip (which are not yet supported by this patch).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/bo
adding a new driver or function for every new SoC.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-multi-gates.c | 105
2 f
The BananaPi M64 is a single board computer with an Allwinner A64 SoC.
In addition to the usual suspects it contains Gigabit Ethernet, 2GB RAM,
an eMMC and a WiFi chip (which are not yet supported by this patch).
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile
adding a new driver or function for every new SoC.
Signed-off-by: Andre Przywara
Acked-by: Jean-Francois Moine
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-multi-gates.c | 105
2 files changed, 106 insertions(+)
create mode 100644
pinctrl driver patch, but got removed
to avoid the dependency on the Kconfig patch [1].
Also add the general PINCTRL symbol, which isn't selected automatically
for the same reason.
Reported-by: Jeroen Dekien <dek...@gmail.com>
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
ommon DTSI and include directly the pine64 DTS]
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/allwinner/Makefile | 5 ++
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 48 ++
pinctrl driver patch, but got removed
to avoid the dependency on the Kconfig patch [1].
Also add the general PINCTRL symbol, which isn't selected automatically
for the same reason.
Reported-by: Jeroen Dekien
Signed-off-by: Andre Przywara
[1]:
http://lists.infradead.org/pipermail/linux-arm-kernel
ommon DTSI and include directly the pine64 DTS]
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/allwinner/Makefile | 5 ++
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 48 ++
.../arm64/boot/dts/allwinner/
to 4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
Hi,
I d
to 4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.
Signed-off-by: Andre Przywara
---
Hi,
I dropped Rob's previous ACK
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicet
-clocks for basic PLL clocks
- use clock names based on manual (periph0 & friends)
- move clocks out of their own subnode into a separate file
- add .dts for BananaPi-M64 (thanks to Nora Lee for a sample board)
Andre Przywara (7):
arm64: sunxi: Kconfig: add essential pinctrl driver
DT: clk: s
-clocks for basic PLL clocks
- use clock names based on manual (periph0 & friends)
- move clocks out of their own subnode into a separate file
- add .dts for BananaPi-M64 (thanks to Nora Lee for a sample board)
Andre Przywara (7):
arm64: sunxi: Kconfig: add essential pinctrl driver
DT: clk: s
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1992aa9..492f92c
for each parent clock used. This allows
to specify any kind of relation efficiently and also keeps the very
same kernel driver for all SoCs at the same time.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bi
for each parent clock used. This allows
to specify any kind of relation efficiently and also keeps the very
same kernel driver for all SoCs at the same time.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/clock/sunxi.txt | 7 +++
1 file changed, 7
Hi Drew,
(CC:ing Dave)
On 01/08/16 13:50, Andrew Jones wrote:
>
> Hi Andre,
>
> I have a couple questions and a bug report regarding the SBSA UART.
>
> When AArch64 Linux is boot with QEMU and UEFI (AAVMF) we can enable
> the use of ACPI. When we do that the PL011 model QEMU provides is
>
Hi Drew,
(CC:ing Dave)
On 01/08/16 13:50, Andrew Jones wrote:
>
> Hi Andre,
>
> I have a couple questions and a bug report regarding the SBSA UART.
>
> When AArch64 Linux is boot with QEMU and UEFI (AAVMF) we can enable
> the use of ACPI. When we do that the PL011 model QEMU provides is
>
Hi Jean-Francois,
On 01/08/16 09:30, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 02:43:06 +0100
> André Przywara wrote:
>
>> As this became quite a long read, here a TL;DR:
>> - We consider using an SCPI based clock system for the A64, alongside
>>
Hi Jean-Francois,
On 01/08/16 09:30, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 02:43:06 +0100
> André Przywara wrote:
>
>> As this became quite a long read, here a TL;DR:
>> - We consider using an SCPI based clock system for the A64, alongside
>> allwinner,simple-gates and fixed clocks.
Hi,
On 25/07/16 20:54, Maxime Ripard wrote:
> On Wed, Jul 20, 2016 at 10:03:16AM +0200, LABBE Corentin wrote:
>> This patch add support for sun8i-emac ethernet MAC hardware.
>> It could be found in Allwinner H3/A83T/A64 SoCs.
>>
>> It supports 10/100/1000 Mbit/s speed with half/full duplex.
>> It
Hi,
On 25/07/16 20:54, Maxime Ripard wrote:
> On Wed, Jul 20, 2016 at 10:03:16AM +0200, LABBE Corentin wrote:
>> This patch add support for sun8i-emac ethernet MAC hardware.
>> It could be found in Allwinner H3/A83T/A64 SoCs.
>>
>> It supports 10/100/1000 Mbit/s speed with half/full duplex.
>> It
and for the deprecated
instructions emulation.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/include/asm/traps.h | 2 ++
arch/arm64/kernel/armv8_deprecated.c | 23 +
arch/arm64/kernel/traps.c| 63
3 files c
and for the deprecated
instructions emulation.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/traps.h | 2 ++
arch/arm64/kernel/armv8_deprecated.c | 23 +
arch/arm64/kernel/traps.c| 63
3 files changed, 53 insertions(+), 35
-A53 cores.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/include/asm/assembler.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/assembler.h
b/arch/arm64/include/asm/assembler.h
index 10b017c..1a021f1 100644
--- a/ar
Currently we call the (optional) enable function for CPU _features_
only. As CPU _errata_ descriptions share the same data structure and
having an enable function is useful for errata as well (for instance
to set bits in SCTLR), lets call it when enumerating erratas too.
Signed-off-by: Andre
p the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault b
-A53 cores.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/assembler.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/assembler.h
b/arch/arm64/include/asm/assembler.h
index 10b017c..1a021f1 100644
--- a/arch/arm64/include/asm/assembl
Currently we call the (optional) enable function for CPU _features_
only. As CPU _errata_ descriptions share the same data structure and
having an enable function is useful for errata as well (for instance
to set bits in SCTLR), lets call it when enumerating erratas too.
Signed-off-by: Andre
p the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault b
or that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/include/asm/alternative.h | 4
arch/arm64/mm/cache.S| 2 +-
2 files changed, 5 insertio
pstream kernel
- revert broken macro patch instead of trying to fix it
- more refactoring for segfault injection
- fixing bug when xzr was used as the address register
- minor nitpicks
[1] commit 301bcfac4289 ("arm64: add Cortex-A53 cache errata workaround")
Andre Przywara (6):
Revert &q
the actual code sequences.
This results in having both the original instruction(s) _and_ the
alternative ones, if enable if false.
Since there is no user of this macros anyway, just revert it.
This reverts commit 77ee306c0aea9a219daec256ad25982944affef8.
Signed-off-by: Andre Przywara <andre.prz
or that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/alternative.h | 4
arch/arm64/mm/cache.S| 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
pstream kernel
- revert broken macro patch instead of trying to fix it
- more refactoring for segfault injection
- fixing bug when xzr was used as the address register
- minor nitpicks
[1] commit 301bcfac4289 ("arm64: add Cortex-A53 cache errata workaround")
Andre Przywara (6):
Revert &q
the actual code sequences.
This results in having both the original instruction(s) _and_ the
alternative ones, if enable if false.
Since there is no user of this macros anyway, just revert it.
This reverts commit 77ee306c0aea9a219daec256ad25982944affef8.
Signed-off-by: Andre Przywara
---
arch/arm
Hi Suzuki,
thanks for having a look!
On 14/06/16 17:16, Suzuki K Poulose wrote:
> On 09/05/16 17:49, Andre Przywara wrote:
>> The ARM errata 819472, 826319, 827319 and 824069 for affected
>> Cortex-A53 cores demand to promote "dc cvau" instructions to
>> "
Hi Suzuki,
thanks for having a look!
On 14/06/16 17:16, Suzuki K Poulose wrote:
> On 09/05/16 17:49, Andre Przywara wrote:
>> The ARM errata 819472, 826319, 827319 and 824069 for affected
>> Cortex-A53 cores demand to promote "dc cvau" instructions to
>> "
rm/drmP.h:207:34: note: in definition of macro
'DRM_DEBUG_DRIVER'
drm_ut_debug_printk(__func__, fmt, ##args); \
.
Use the proper printk format specifier [1] for dma_addr_t which takes
care of those differences.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
[1] Documentation
rm/drmP.h:207:34: note: in definition of macro
'DRM_DEBUG_DRIVER'
drm_ut_debug_printk(__func__, fmt, ##args); \
.
Use the proper printk format specifier [1] for dma_addr_t which takes
care of those differences.
Signed-off-by: Andre Przywara
[1] Documentation/printk-formats.txt
---
dr
efined reference to `irq_gc_ack_set_bit'
drivers/irqchip/irq-sunxi-nmi.c:170: undefined reference to
`irq_gc_mask_clr_bit'
Fixes: commit ce3dd55b99b1 ("arm64: Introduce Allwinner SoC config option")
Cc: Andre Przywara <andre.przyw...@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.po
t'
drivers/irqchip/irq-sunxi-nmi.c:170: undefined reference to
`irq_gc_mask_clr_bit'
Fixes: commit ce3dd55b99b1 ("arm64: Introduce Allwinner SoC config option")
Cc: Andre Przywara
Signed-off-by: Suzuki K Poulose
Signed-off-by: Andre Przywara
---
Hi Olof, Arnd,
as agreed upon in that
-A53 cores.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/mm/proc-macros.S | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
index e6a30e1..5786017 100644
--- a/arch/arm64/mm/proc-macros.S
+++
-A53 cores.
Signed-off-by: Andre Przywara
---
arch/arm64/mm/proc-macros.S | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/mm/proc-macros.S b/arch/arm64/mm/proc-macros.S
index e6a30e1..5786017 100644
--- a/arch/arm64/mm/proc-macros.S
+++ b/arch/arm64/mm/proc-macros.
and for the deprecated
instructions emulation.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/include/asm/traps.h | 3 +++
arch/arm64/kernel/armv8_deprecated.c | 13 --
arch/arm64/kernel/traps.c| 46 ++--
3 files c
and for the deprecated
instructions emulation.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/traps.h | 3 +++
arch/arm64/kernel/armv8_deprecated.c | 13 --
arch/arm64/kernel/traps.c| 46 ++--
3 files changed, 41 insertions(+), 21
or that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/include/asm/alternative.h | 4
arch/arm64/mm/cache.S| 2 +-
2 files changed, 5 insertio
Currently we call the (optional) enable function for CPU _features_
only. As CPU _errata_ descriptions share the same data structure and
having an enable function is useful for errata as well (for instance
to set bits in SCTLR), lets call it when enumerating erratas too.
Signed-off-by: Andre
77ee306c0aea ("arm64: alternatives: add
enable parameter to conditional asm macros").
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm64/include/asm/alternative.h | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/inc
IGSEGV) and
verified with some debugfs entries.
At least one LTP test also issues around 100 cache maintenance
instructions, which this code survived happily.
Cheers,
Andre.
[1] commit 301bcfac4289 ("arm64: add Cortex-A53 cache errata workaround")
Andre Przywara (6):
arm64: alternativ
or that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/alternative.h | 4
arch/arm64/mm/cache.S| 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
Currently we call the (optional) enable function for CPU _features_
only. As CPU _errata_ descriptions share the same data structure and
having an enable function is useful for errata as well (for instance
to set bits in SCTLR), lets call it when enumerating erratas too.
Signed-off-by: Andre
77ee306c0aea ("arm64: alternatives: add
enable parameter to conditional asm macros").
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/alternative.h | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/alternative.h
b/arch/a
IGSEGV) and
verified with some debugfs entries.
At least one LTP test also issues around 100 cache maintenance
instructions, which this code survived happily.
Cheers,
Andre.
[1] commit 301bcfac4289 ("arm64: add Cortex-A53 cache errata workaround")
Andre Przywara (6):
arm64: alternativ
p the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault b
p the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault b
Hi Maxime,
On 05/05/16 14:21, Maxime Ripard wrote:
> On Wed, May 04, 2016 at 11:44:48AM +0100, Andre Przywara wrote:
>> Hi Maxime,
>>
>> On 02/05/16 07:48, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Mon, Apr 25, 2016 at 02:04:52AM +0100, Andre Przyw
Hi Maxime,
On 05/05/16 14:21, Maxime Ripard wrote:
> On Wed, May 04, 2016 at 11:44:48AM +0100, Andre Przywara wrote:
>> Hi Maxime,
>>
>> On 02/05/16 07:48, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Mon, Apr 25, 2016 at 02:04:52AM +0100, Andre Przyw
Hi Maxime,
On 02/05/16 07:48, Maxime Ripard wrote:
> Hi,
>
> On Mon, Apr 25, 2016 at 02:04:52AM +0100, Andre Przywara wrote:
>> The Allwinner NMI irqchip driver requires GENERIC_IRQ_CHIP, but
>> we can't select it directly, because there is no specific Kconfig entry
>>
Hi Maxime,
On 02/05/16 07:48, Maxime Ripard wrote:
> Hi,
>
> On Mon, Apr 25, 2016 at 02:04:52AM +0100, Andre Przywara wrote:
>> The Allwinner NMI irqchip driver requires GENERIC_IRQ_CHIP, but
>> we can't select it directly, because there is no specific Kconfig entry
>>
future SoCs
automatically).
Reported-by: Suzuki K Poulose <suzuki.poul...@arm.com>
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
Hi,
this is a new approach to the problem that Suzuki tried to address
already.
It separates the sun4i IRQ controller driver and the NMI driv
future SoCs
automatically).
Reported-by: Suzuki K Poulose
Signed-off-by: Andre Przywara
---
Hi,
this is a new approach to the problem that Suzuki tried to address
already.
It separates the sun4i IRQ controller driver and the NMI driver as
Maxime requested.
While there should be no difference
Hi,
On 14/04/16 09:56, Suzuki K Poulose wrote:
> On 14/04/16 09:47, Suzuki K Poulose wrote:
>> On 13/04/16 21:07, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Wed, Apr 13, 2016 at 04:59:27PM +0100, Suzuki K Poulose wrote:
The sunxi-nmi and sun4i irq chips are selected by ARCH_SUNXI on both
Hi,
On 14/04/16 09:56, Suzuki K Poulose wrote:
> On 14/04/16 09:47, Suzuki K Poulose wrote:
>> On 13/04/16 21:07, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Wed, Apr 13, 2016 at 04:59:27PM +0100, Suzuki K Poulose wrote:
The sunxi-nmi and sun4i irq chips are selected by ARCH_SUNXI on both
These new syscalls are implemented as generic code, so enable them for
architectures like arm64 which use the generic syscall table.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
include/uapi/asm-generic/unistd.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
These new syscalls are implemented as generic code, so enable them for
architectures like arm64 which use the generic syscall table.
Signed-off-by: Andre Przywara
---
include/uapi/asm-generic/unistd.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/asm
ask_clr_bit'
>
> Fixes: commit ce3dd55b99b1 ("arm64: Introduce Allwinner SoC config option")
> Cc: Andre Przywara <andre.przyw...@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poul...@arm.com>
Acked-by: Andre Przywara <andre.przyw...@arm.com>
Cheers,
Andre
ask_clr_bit'
>
> Fixes: commit ce3dd55b99b1 ("arm64: Introduce Allwinner SoC config option")
> Cc: Andre Przywara
> Signed-off-by: Suzuki K Poulose
Acked-by: Andre Przywara
Cheers,
Andre.
> ---
> arch/arm64/Kconfig.platforms |1 +
> 1 file changed, 1
about the SBSA only.
So:
Tested-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Andre Przywara <andre.przyw...@arm.com>
You can add Juno and Midway to the list of tested systems.
Cheers,
Andre.
> ---
> Changes new in v2:
> * Fixed from address
> * Elaborated on forward (SBS
at least the
current ARM PL011 implementation are totally fine with 32-bit (as well
as 16-bit) accesses.
There is some reluctance about whether this is true for _every_ older
PL011 implementation, but they are out of scope here, as we are talking
about the SBSA only.
So:
Tested-by: Andre Przywara
Acked-by
", so
not starting at 0).
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Hi Linus,
as requested a rebased version of the driver, now based upon
pinctrl/devel.
I adjus
", so
not starting at 0).
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Maxime Ripard
---
Hi Linus,
as requested a rebased version of the driver, now based upon
pinctrl/devel.
I adjusted the PINCTRL_SUNXI symbol name in the Kconfig, which got
renamed lately, that shoul
bi-endian architecture at the moment,
which is unnecessary as long as host and guest use the same endianess.
Patch 3/3 fixes this.
Please have a look and apply!
Cheers,
Andre.
[1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/357884.html
Andre Przywara (3):
irq: move IRQ
interrupt routing.
This also removes the dummy implementations for all other
architectures and only leaves the x86 specific code in x86/irq.c.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
Makefile | 4 +--
arm/irq.c | 9 --
hw/pci-shmem.c| 2 ++
inclu
bi-endian architecture at the moment,
which is unnecessary as long as host and guest use the same endianess.
Patch 3/3 fixes this.
Please have a look and apply!
Cheers,
Andre.
[1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/357884.html
Andre Przywara (3):
irq: move IRQ
interrupt routing.
This also removes the dummy implementations for all other
architectures and only leaves the x86 specific code in x86/irq.c.
Signed-off-by: Andre Przywara
---
Makefile | 4 +--
arm/irq.c | 9 --
hw/pci-shmem.c| 2 ++
include/kvm/irq.h | 5
irq.c
vhost-net, where the queue's IRQFD was setup before the
MSI vectors.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
include/kvm/irq.h | 1 +
irq.c | 31 +++
virtio/pci.c | 36 +---
3 files chang
vhost-net, where the queue's IRQFD was setup before the
MSI vectors.
Signed-off-by: Andre Przywara
---
include/kvm/irq.h | 1 +
irq.c | 31 +++
virtio/pci.c | 36 +---
3 files changed, 65 insertions(+), 3 deletions
this against
the guest endianness.
This enables vhost support on ARM and ARM64.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
include/kvm/virtio.h | 9 +++--
virtio/net.c | 2 +-
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/kvm/virtio.h b/inclu
this against
the guest endianness.
This enables vhost support on ARM and ARM64.
Signed-off-by: Andre Przywara
---
include/kvm/virtio.h | 9 +++--
virtio/net.c | 2 +-
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/include/kvm/virtio.h b/include/kvm/virtio.h
index 768ee96..66530fd
Hi,
On 01/03/16 12:53, Carlo Caione wrote:
> On Tue, Mar 1, 2016 at 1:43 PM, Andre Przywara <andre.przyw...@arm.com> wrote:
>> Hi,
>>
>> On 01/03/16 11:18, Andreas Färber wrote:
>>> Hi Andre,
>>>
>>> Am 01.03.2016 um 12:01 schrieb Andre
Hi,
On 01/03/16 12:53, Carlo Caione wrote:
> On Tue, Mar 1, 2016 at 1:43 PM, Andre Przywara wrote:
>> Hi,
>>
>> On 01/03/16 11:18, Andreas Färber wrote:
>>> Hi Andre,
>>>
>>> Am 01.03.2016 um 12:01 schrieb Andre Przywara:
>>>> On 2
Hi,
On 01/03/16 11:18, Andreas Färber wrote:
> Hi Andre,
>
> Am 01.03.2016 um 12:01 schrieb Andre Przywara:
>> On 29/02/16 23:44, Andreas Färber wrote:
>>> Add GICH and GICV resources for HYP mode - guess based on other vendors.
>>
>> Do you know if the firm
Hi,
On 01/03/16 11:18, Andreas Färber wrote:
> Hi Andre,
>
> Am 01.03.2016 um 12:01 schrieb Andre Przywara:
>> On 29/02/16 23:44, Andreas Färber wrote:
>>> Add GICH and GICV resources for HYP mode - guess based on other vendors.
>>
>> Do you know if the firm
Hi Andreas,
On 29/02/16 23:44, Andreas Färber wrote:
> Add GICH and GICV resources for HYP mode - guess based on other vendors.
Do you know if the firmware allows the kernel to be entered in EL2
(which is the arm64 name for HYP)?
So can we run kvm?
If you have a booted kernel, can you grep for
Hi Andreas,
On 29/02/16 23:44, Andreas Färber wrote:
> Add GICH and GICV resources for HYP mode - guess based on other vendors.
Do you know if the firmware allows the kernel to be entered in EL2
(which is the arm64 name for HYP)?
So can we run kvm?
If you have a booted kernel, can you grep for
.
Also are you happy with the PLL6 reuse patch I sent on Monday and can I
base the A64's PLL7 clock on that?
Or do you prefer another approach here? I am happy to discuss this on
the list then.
Cheers,
Andre.
On 22/02/16 18:20, Andre Przywara wrote:
> Hi,
>
> another update of the Allw
.
Also are you happy with the PLL6 reuse patch I sent on Monday and can I
base the A64's PLL7 clock on that?
Or do you prefer another approach here? I am happy to discuss this on
the list then.
Cheers,
Andre.
On 22/02/16 18:20, Andre Przywara wrote:
> Hi,
>
> another update of the Allw
hub.com/apritzel/linux/commits/a64-v3
Andre Przywara (10):
clk: sunxi: allow PLL6 clock to be reused
ARM: dts: sunxi: make PLL8 in the H3 a proper clock
arm64: Introduce Allwinner SoC config option
drivers: pinctrl: add driver for Allwinner A64 SoC
DT: clk: sunxi: add binding doc for t
Now that we can reuse the A31 PLL6 clock driver for clocks other then
PLL6 itself, describe the PLL8 clock properly.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff
hub.com/apritzel/linux/commits/a64-v3
Andre Przywara (10):
clk: sunxi: allow PLL6 clock to be reused
ARM: dts: sunxi: make PLL8 in the H3 a proper clock
arm64: Introduce Allwinner SoC config option
drivers: pinctrl: add driver for Allwinner A64 SoC
DT: clk: sunxi: add binding doc for t
Now that we can reuse the A31 PLL6 clock driver for clocks other then
PLL6 itself, describe the PLL8 clock properly.
Signed-off-by: Andre Przywara
---
arch/arm/boot/dts/sun8i-h3.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i
. This allows
to specify any kind of relation efficiently and also keeps the very
same kernel driver for all SoCs at the same time.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 6 ++
1
. This allows
to specify any kind of relation efficiently and also keeps the very
same kernel driver for all SoCs at the same time.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/clock/sunxi.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git
son put it: "Those are smaller and these are
missing." ;-)
The two Pine64+ models just differ in the amount of DRAM
(1GB vs. 2GB). Since U-Boot will figure out the right size for us and
patches the DT accordingly we just need to provide one DT for the
Pine64+.
Signed-off-by: Andr
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