Brace expansion might not work properly if _buildshell RPM macro
points to a shell other than bash. Particularly, with _bulidshell
defined to /bin/dash it leads to broken build and source symlinks.
Signed-off-by: Anton Tikhomirov
---
scripts/package/mkspec | 3 ++-
1 file changed, 2 insertions
Hello,
> Hi Anton,
>
> On 13.10.2014 06:54, Anton Tikhomirov wrote:
> > Hi Vivek,
> >
> >> Exynos7 also has a separate special gate clock going to the IP
> >> apart from the usual AHB clock. So add support for the same.
> >
> > As we discussed
Hi Vivek,
> Some Exynos SoCs have a separate regulator controlling a
I guess you meant the Exynos based *boards* instead of SoCs,
since Exynos SoCs don't have any boost regulators.
> Boost 5V supply which goes as input for VBUS regulator.
> So adding a control for the same in driver, to enable
>
Hi Vivek,
> Exynos7 SoC has now separate gate control for 125MHz pipe3 phy
> clock, as well as 60MHz utmi phy clock.
> So get the same and control in the phy-exynos5-usbdrd driver.
In case of the PHY the situation is pretty much the same as with
DWC3 core. Here we should control 6 clocks to make
Hi Vivek,
> Exynos7 also has a separate special gate clock going to the IP
> apart from the usual AHB clock. So add support for the same.
As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
by the driver. Adding only sclk is not enough.
>
> Signed-off-by: Vivek Gautam
> ---
>
Hi,
> Hi,
>
> > -Original Message-
> > From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
> > ow...@vger.kernel.org] On Behalf Of Vivek Gautam
> > Sent: Monday, April 21, 2014 9:17 PM
> >
> > Facilitate getting required 3.3V and 1.0V VDD supply for
> > OHCI controller on Exynos.
> >
Hi,
> -Original Message-
> From: linux-usb-ow...@vger.kernel.org [mailto:linux-usb-
> ow...@vger.kernel.org] On Behalf Of Vivek Gautam
> Sent: Monday, April 21, 2014 9:17 PM
>
> Facilitate getting required 3.3V and 1.0V VDD supply for
> OHCI controller on Exynos.
>
> With patches for reg
Hi,
> Hi Anton,
>
>
> On Wed, Apr 23, 2014 at 2:56 PM, Anton Tikhomirov
> wrote:
> > Hello,
> >
> >> -Original Message-
> >> From: Vivek Gautam [mailto:gautamvivek1...@gmail.com] On Behalf Of
> >> Vivek Gautam
> >> Sent: Mo
.kernel.org; linux-
> arm-ker...@lists.infradead.org; gre...@linuxfoundation.org;
> st...@rowland.harvard.edu; ba...@ti.com; kgene@samsung.com; Vivek
> Gautam; Anton Tikhomirov
> Subject: [PATCH 3/3] usb: dwc3-exynos: Make provision for vdd
> regulators
>
> Facilitate gettin
Hi,
> Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
>
> Hi,
>
> On Thursday 06 March 2014 02:49 PM, Anton Tikhomirov wrote:
> > Hi,
> >
> >> Subject: RE: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
> >>
> >> H
Hi,
> Subject: RE: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
>
> Hi,
>
> > Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
> >
> > Hi,
> >
> > On Thursday 06 March 2014 02:22 PM, Anton Tikhomirov wrote:
> > >
Hi,
> Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
>
> Hi,
>
> On Thursday 06 March 2014 02:22 PM, Anton Tikhomirov wrote:
> > Hello,
> >
> >> Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
> >>
> >&g
Hello,
> Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
>
>
>
> On Thursday 06 March 2014 01:56 PM, Anton Tikhomirov wrote:
> > Hi Kamil,
> >
> > ...
> >
> >> +| 3. Supporting SoCs
> >> ++
> &
Hi Kamil,
...
> +| 3. Supporting SoCs
> ++
> +
> +To support a new SoC a new file should be added to the drivers/phy
> +directory. Each SoC's configuration is stored in an instance of the
> +struct samsung_usb2_phy_config.
> +
> +struct samsung_usb2_phy_config {
> + const
Hi Kamil,
> Hi Anton,
>
> > From: Anton Tikhomirov [mailto:av.tikhomi...@samsung.com]
> > Sent: Tuesday, December 10, 2013 3:43 AM
> >
> > Hi Kamil,
> >
> > Same USB2.0 PHY may be used by several HCDs, for example EHCI and
> OHCI.
> > Consid
Hi Kamil,
Same USB2.0 PHY may be used by several HCDs, for example EHCI and OHCI.
Consider the situation, when EHCI stops using the PHY and calls power_off,
then OHCI becomes non-operational. In other words, PHY power_on and
power_off calls must be balanced.
Shall we handle it in your driver? (u
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