On 12.3.2021 23.09, Bjorn Helgaas wrote:
> On Mon, Mar 08, 2021 at 02:21:30PM +0000, Antti Järvinen wrote:
>> Some TI KeyStone C667X devices do no support bus/hot reset. Its PCIESS
>> automatically disables LTSSM when secondary bus reset is received and
>> device stops
leak state between VMs.
Reference: https://e2e.ti.com/support/processors/f/791/t/954382
Signed-off-by: Antti Järvinen
---
drivers/pci/quirks.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 653660e3ba9e..d9201ad1ca39 100644
--- a
On 7.3.2021 2.22, Krzysztof Wilczyński wrote:
> Hi Antti,
>
> A few nitpicks, so feel free to ignore these, of course.
>
> If possible, capitalise the subject line. Also, perhaps "Add quirk to
> prevent bus (...)" might read better.
>
>> Some TI keystone C667X devices do no support bus/hot r
leak state between VMs.
Reference: https://e2e.ti.com/support/processors/f/791/t/954382
Signed-off-by: Antti Järvinen
---
drivers/pci/quirks.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 653660e3ba9e..d9201ad1ca39 100644
--- a
leak state between VMs.
Reference https://e2e.ti.com/support/processors/f/791/t/954382
Signed-off-by: Antti Järvinen
---
drivers/pci/quirks.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 653660e3ba9e..d9201ad1ca39 100644
--- a
On 22.1.2021 1.55, Bjorn Helgaas wrote:>
> It looks like we would probably be trying a Secondary Bus Reset using
> the bridge leading to the C667X. Can you confirm?
Yes, this is my understanding too.
> Wonder if you
> could try doing what pci_reset_secondary_bus() does by hand:
>
I tried th
TI C667X does not support bus/hot reset.
See https://e2e.ti.com/support/processors/f/791/t/954382
Signed-off-by: Antti Järvinen
---
drivers/pci/quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 653660e3ba9e..c8fcf24c5bd0 100644
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