erry Escande <thierry.esca...@collabora.com>
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gp
On 01/09/2018 08:18 PM, Thierry Escande wrote:
From: Jeffy Chen
We inited connector in attach(), so need a detach() to cleanup.
Also fix wrong use of dw_hdmi_remove() in bind().
Signed-off-by: Jeffy Chen
Signed-off-by: Thierry Escande
Reviewed-by: Archit Taneja
---
drivers/gpu/drm
On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
Parts of PHY code could be useful also for custom PHYs. For example,
Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
with few additional memory mapped registers, so most of the Synopsys PHY
related code could be reused.
It turns
On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
Parts of PHY code could be useful also for custom PHYs. For example,
Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
with few additional memory mapped registers, so most of the Synopsys PHY
related code could be reused.
It turns
On 12/05/2017 06:49 AM, Brian Norris wrote:
Hi Archit,
I'm a relative n00b here, but I'm trying to follow along and I have some
questions:
On Fri, Dec 01, 2017 at 06:29:04PM +0530, Archit Taneja wrote:
On 11/30/2017 11:02 PM, Nickey Yang wrote:
I try to follow as you suggested,use
On 12/05/2017 06:49 AM, Brian Norris wrote:
Hi Archit,
I'm a relative n00b here, but I'm trying to follow along and I have some
questions:
On Fri, Dec 01, 2017 at 06:29:04PM +0530, Archit Taneja wrote:
On 11/30/2017 11:02 PM, Nickey Yang wrote:
I try to follow as you suggested,use
On 11/30/2017 11:02 PM, Nickey Yang wrote:
Hi Archit,
On 2017年10月26日 12:53, Archit Taneja wrote:
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang <nickey.y...@rock-chips.
On 11/30/2017 11:02 PM, Nickey Yang wrote:
Hi Archit,
On 2017年10月26日 12:53, Archit Taneja wrote:
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang
---
.../devicetree/bindings/display/rockchip
m Arnd and John.
Reported-by: Naresh Kamboju <naresh.kamb...@linaro.org>
Cc: Xinliang Liu <xinliang@linaro.org>
Cc: Dan Carpenter <dan.carpen...@oracle.com>
Cc: Sean Paul <seanp...@chromium.org>
Cc: Archit Taneja <arch...@codeaurora.org>
Cc: John Stultz <john.st
d-by: Naresh Kamboju
Cc: Xinliang Liu
Cc: Dan Carpenter
Cc: Sean Paul
Cc: Archit Taneja
Cc: John Stultz
Link: https://bugs.linaro.org/show_bug.cgi?id=3345
Link: https://lkft.validation.linaro.org/scheduler/job/48017#L3551
Fixes: 7af35b0addbc ("drm/kirin: Checking for IS_ERR() instead of N
On 11/15/2017 03:29 PM, Lothar Waßmann wrote:
Hi,
On Tue, 14 Nov 2017 11:16:47 -0800 Eric Anholt wrote:
The panel_bridge bridge attaches to the panel's OF node, not the
lvds-encoder's node. Put in a little no-op bridge of our own so that
our consumers can still find a bridge where they
On 11/15/2017 03:29 PM, Lothar Waßmann wrote:
Hi,
On Tue, 14 Nov 2017 11:16:47 -0800 Eric Anholt wrote:
The panel_bridge bridge attaches to the panel's OF node, not the
lvds-encoder's node. Put in a little no-op bridge of our own so that
our consumers can still find a bridge where they
On 11/29/2017 03:02 AM, John Stultz wrote:
On Sun, Nov 26, 2017 at 4:56 AM, Archit Taneja <arch...@codeaurora.org> wrote:
On 11/17/2017 04:29 AM, John Stultz wrote:
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 0
On 11/29/2017 03:02 AM, John Stultz wrote:
On Sun, Nov 26, 2017 at 4:56 AM, Archit Taneja wrote:
On 11/17/2017 04:29 AM, John Stultz wrote:
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 0e14f15..939c3b9 100644
--- a/drivers
On 11/28/2017 06:35 AM, Brian Norris wrote:
Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.
Reviewed-by: Archit Taneja <a
On 11/28/2017 06:35 AM, Brian Norris wrote:
Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.
Reviewed-by: Archit Taneja
Signed-off
Hi,
Thanks a lot for working on this. Some comments below.
On 11/28/2017 07:25 AM, Nickey Yang wrote:
Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.
Signed-off-by: Nickey Yang
---
Hi,
Thanks a lot for working on this. Some comments below.
On 11/28/2017 07:25 AM, Nickey Yang wrote:
Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.
Signed-off-by: Nickey Yang
---
drivers/gpu/drm/rockchip/Kconfig|
: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Tested-by: Neil Armstrong <narmstr...@baylibre.com>
Reviewed-by: Jose Abreu <joab...@synopsys.com>
Signed-off-by: Archit Taneja <arch...@codeaurora.org>
Link:
http://patchwork.freedesk
Abreu
Signed-off-by: Archit Taneja
Link:
http://patchwork.freedesktop.org/patch/msgid/20170305233557.11945-1-laurent.pinchart+rene...@ideasonboard.com
:04 04 0defad9d1a61c0355f49c679b18eebae2c4b9495
5d260e6db25d6abc1211d61ec3405be99e693a23 M drivers
This commit does not
naresh.kamb...@linaro.org>
Cc: Xinliang Liu <xinliang@linaro.org>
Cc: Dan Carpenter <dan.carpen...@oracle.com>
Cc: Sean Paul <seanp...@chromium.org>
Cc: Hans Verkuil <hans.verk...@cisco.com>
Cc: Archit Taneja <arch...@codeaurora.org>
Link: https://bugs.linaro.org
Carpenter
Cc: Sean Paul
Cc: Hans Verkuil
Cc: Archit Taneja
Link: https://bugs.linaro.org/show_bug.cgi?id=3345
Link: https://lkft.validation.linaro.org/scheduler/job/48017#L3551
Fixes: 7af35b0addbc ("drm/kirin: Checking for IS_ERR() instead of NULL")
Fixes: 3b1b975003e4 ("drm: adv751
On 11/26/2017 01:48 AM, Pierre-Hugues Husson wrote:
Support the "cec" optional clock. The documentation already mentions "cec"
optional clock and it is used by several boards, but currently the driver
doesn't enable it, thus preventing cec from working on those boards.
And even worse: a
On 11/26/2017 01:48 AM, Pierre-Hugues Husson wrote:
Support the "cec" optional clock. The documentation already mentions "cec"
optional clock and it is used by several boards, but currently the driver
doesn't enable it, thus preventing cec from working on those boards.
And even worse: a
Hi,
On 11/20/2017 06:00 PM, Hans Verkuil wrote:
I didn't see this merged for 4.15, is it too late to include this?
All other changes needed to get CEC to work on rk3288 and rk3399 are all merged.
Sorry for the late reply. I was out last week.
Dave recently sent the second pull request for
Hi,
On 11/20/2017 06:00 PM, Hans Verkuil wrote:
I didn't see this merged for 4.15, is it too late to include this?
All other changes needed to get CEC to work on rk3288 and rk3399 are all merged.
Sorry for the late reply. I was out last week.
Dave recently sent the second pull request for
On 11/08/2017 09:15 AM, Bjorn Andersson wrote:
Add a missing #phy-cells to the dsi-phy, to silence dtc warning.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Cc: Archit Taneja <arch...@codeaurora.org>
Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Ad
On 11/08/2017 09:15 AM, Bjorn Andersson wrote:
Add a missing #phy-cells to the dsi-phy, to silence dtc warning.
Reviewed-by: Archit Taneja
Thanks,
Archit
Cc: Archit Taneja
Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support")
Signed-off-by: Bjorn Andersson
---
: Link encoder and bridge in core code
This was merged only in 4.11.
Thanks,
Archit
--
From: Archit Taneja <arch...@codeaurora.org>
[ Upstream commit 0bb70b82c2f91e4667f3c617505235efd6d77e46 ]
The commit "drm: bridge: Link encoder and bridge in core co
: Link encoder and bridge in core code
This was merged only in 4.11.
Thanks,
Archit
--
From: Archit Taneja
[ Upstream commit 0bb70b82c2f91e4667f3c617505235efd6d77e46 ]
The commit "drm: bridge: Link encoder and bridge in core code" updated
the drm_bridge_attach() A
On 10/25/2017 01:34 PM, Sean Paul wrote:
On Wed, Oct 25, 2017 at 11:51:01AM +0800, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
Signed-off-by:
On 10/25/2017 01:34 PM, Sean Paul wrote:
On Wed, Oct 25, 2017 at 11:51:01AM +0800, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
Signed-off-by:
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 ++
1 file changed, 2 insertions(+)
On 10/25/2017 09:21 AM, Nickey Yang wrote:
Configure dsi slave channel when driving a panel
which needs 2 DSI links.
Signed-off-by: Nickey Yang
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi,
On 10/26/2017 06:39 AM, Brian Norris wrote:
On Wed, Oct 25, 2017 at 03:57:19AM -0400, Sean Paul wrote:
Archit asked a question about moving to
dw-mipi-dsi
That question made me think though: this approach seems backwards. It
seems like someone did copy/paste/fork, and then we're asking
Hi,
On 10/26/2017 06:39 AM, Brian Norris wrote:
On Wed, Oct 25, 2017 at 03:57:19AM -0400, Sean Paul wrote:
Archit asked a question about moving to
dw-mipi-dsi
That question made me think though: this approach seems backwards. It
seems like someone did copy/paste/fork, and then we're asking
;pipeline.mixer->lm;
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w;
uint32_t roi_h;
I guess we could get rid of roi_w, roi_h and the call to get_roi() in this fucn
too?
Otherwise:
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
@@ -8
uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
uint32_t roi_w;
uint32_t roi_h;
I guess we could get rid of roi_w, roi_h and the call to get_roi() in this fucn
too?
Otherwise:
Reviewed-by: Archit Taneja
@@ -857,12 +898,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc
On 10/20/2017 05:47 PM, Rob Clark wrote:
It's only likely to paper over bugs. Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.
Acked-by: Archit Taneja <a
On 10/20/2017 05:47 PM, Rob Clark wrote:
It's only likely to paper over bugs. Unlike the gpu, where we want to
keep things alive a bit longer in expectation of the next frame's
submit, when the display is shut down we can power off immediately.
Acked-by: Archit Taneja
Signed-off-by: Rob
series. I guess it would be easier
to queue this to drm-misc as a part of the eDP support series. For that:
Acked-by: Archit Taneja <arch...@codeaurora.org>
Acked-by: Jingoo Han <jingooh...@gmail.com>
Best regards,
Jingoo Han
---
Changes in v4: None
Changes in v3: None
Changes i
-by: Archit Taneja
Acked-by: Jingoo Han
Best regards,
Jingoo Han
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 50 +
-
drivers/gpu/drm/exynos/exynos_dp.c | 26 ++-
drivers
Hi,
Comment below.
On 09/26/2017 01:25 PM, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
@@ -1226,6 +1367,13 @@ static int
Hi,
Comment below.
On 09/26/2017 01:25 PM, Nickey Yang wrote:
This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.
@@ -1226,6 +1367,13 @@ static int
Hi,
On 09/26/2017 01:25 PM, Nickey Yang wrote:
This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback
Hi,
On 09/26/2017 01:25 PM, Nickey Yang wrote:
This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback
dge" flag
from stm driver internal structure.
version 2:
- does the same for vc4 and dw-mipi-dsi
For the series:
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Feel free to queue to drm-misc-next.
Thanks,
Archit
Benjamin Gaignard (5):
drm/bridge: make drm_panel_bridge_r
dge" flag
from stm driver internal structure.
version 2:
- does the same for vc4 and dw-mipi-dsi
For the series:
Reviewed-by: Archit Taneja
Feel free to queue to drm-misc-next.
Thanks,
Archit
Benjamin Gaignard (5):
drm/bridge: make drm_panel_bridge_remove more robust
drm/drm_of:
t
vc4 will create the host early on.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Eric Anholt <e...@anholt.net>
---
drivers/gpu/drm/panel/Kconfig | 8 +
drivers/gpu/drm/panel/Makefile | 1 +
.../gpu/drm/p
t
vc4 will create the host early on.
Reviewed-by: Archit Taneja
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/panel/Kconfig | 8 +
drivers/gpu/drm/panel/Makefile | 1 +
.../gpu/drm/panel/panel-raspberrypi-touchscreen.c | 517 +
Hi Benjamin,
This should be pushed to drm-misc by you, right?
Thanks,
Archit
On 09/06/2017 06:43 PM, Arnd Bergmann wrote:
gcc-7 complains about multiplying within a condition being
suspicious:
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c: In function 'dsi_pll_get_clkout_khz':
Hi Benjamin,
This should be pushed to drm-misc by you, right?
Thanks,
Archit
On 09/06/2017 06:43 PM, Arnd Bergmann wrote:
gcc-7 complains about multiplying within a condition being
suspicious:
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c: In function 'dsi_pll_get_clkout_khz':
On 09/01/2017 07:15 PM, Andrzej Hajda wrote:
On 01.08.2017 15:23, Philippe CORNU wrote:
Based on patch "Convert drivers to explicit reset API" from Philipp Zabel
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control
On 09/01/2017 07:15 PM, Andrzej Hajda wrote:
On 01.08.2017 15:23, Philippe CORNU wrote:
Based on patch "Convert drivers to explicit reset API" from Philipp Zabel
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control
On 09/01/2017 06:59 PM, Andrzej Hajda wrote:
On 01.08.2017 15:23, Philippe CORNU wrote:
This patch cleans up the Synopsys mipi dsi register list:
- rename registers according to the Synopsys documentation
(1.30 & 1.31)
- fix typos
- re-order registers for a better coherency
Signed-off-by:
On 09/01/2017 06:59 PM, Andrzej Hajda wrote:
On 01.08.2017 15:23, Philippe CORNU wrote:
This patch cleans up the Synopsys mipi dsi register list:
- rename registers according to the Synopsys documentation
(1.30 & 1.31)
- fix typos
- re-order registers for a better coherency
Signed-off-by:
/attach into the component bind process.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Eric Anholt <e...@anholt.net>
---
drivers/gpu/drm/vc4/vc4_dsi.c | 97 +--
1 file changed, 57 insertions(+), 40 deletions(-)
diff --g
/attach into the component bind process.
Reviewed-by: Archit Taneja
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_dsi.c | 97 +--
1 file changed, 57 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ4019 QPIC NAND controller
version 1.4.0 which uses BAM DMA.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
driv
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ4019 QPIC NAND controller
version 1.4.0 which uses BAM DMA.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 10 ++
1 file changed, 10
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ8074 QPIC NAND controller
version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers
starting offset is 0x7000.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Ab
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
Add the compatible string for IPQ8074 QPIC NAND controller
version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers
starting offset is 0x7000.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 108 +++---
1 file changed, 92 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/qc
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 108 +++---
1 file changed, 92 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index d17c466
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codea
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 19
th NAND_FLASH_DEV_* in the registers
defined above, it might get confusing for someone who doesn't have access
to the HW docs. Could you explicitly mention in this comment all the register
names that are required to go through this translation, it should make things
more readable. With that:
Reviewed
he registers
defined above, it might get confusing for someone who doesn't have access
to the HW docs. Could you explicitly mention in this comment all the register
names that are required to go through this translation, it should make things
more readable. With that:
Reviewed-by: Archit Taneja
Th
descriptor formation function.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/driv
descriptor formation function.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
be required later if we want the controller to support multiple NAND chips?
If not,
then we could consider dropping this. Anyway, that can be posted as a separate
patch
later.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
e want the controller to support multiple NAND chips?
If not,
then we could consider dropping this. Anyway, that can be posted as a separate
patch
later.
Reviewed-by: Archit Taneja
Thanks,
Archit
nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NE
codeword/page detection controller. This register should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
driv
codeword/page detection controller. This register should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 21 +
1 file
_set_readl(nandc, 0, 0, size, 1);
The READ_LOC reg should already be set up in update_rw_regs, right? If so, we
could
drop this line.
With that,
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
config_nand_single_cw_page_read(nandc);
@@ -1502,6 +1551,7 @@ stat
);
The READ_LOC reg should already be set up in update_rw_regs, right? If so, we
could
drop this line.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
config_nand_single_cw_page_read(nandc);
@@ -1502,6 +1551,7 @@ static int qcom_nandc_read_page_raw(struct mtd_info *mtd,
y used only for controllers using
BAM.
With that,
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
*/
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsign
BAM.
With that,
Reviewed-by: Archit Taneja
Thanks,
Archit
*/
static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs)
+ int num_regs, unsigned int flags)
{
bool flow_control = false;
void *vaddr
.
- The size of the buffer used for BAM transactions
is calculated based on the NAND device with the maximum page size,
among all the devices connected to the
controller.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codea
.
- The size of the buffer used for BAM transactions
is calculated based on the NAND device with the maximum page size,
among all the devices connected to the
controller.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 94
. Before starting of any operation, this buffer will
be synced for device operation and after operation
completion, it will be synced again for CPU.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Thanks,
Archit
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
driv
. Before starting of any operation, this buffer will
be synced for device operation and after operation
completion, it will be synced again for CPU.
Reviewed-by: Archit Taneja
Thanks,
Archit
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 40
On 08/09/2017 02:08 PM, Laurent Pinchart wrote:
Hi Arvind,
Thank you for the patch.
On Wednesday 09 Aug 2017 13:08:37 Arvind Yadav wrote:
snd_pcm_ops are not supposed to change at runtime. All functions
working with snd_pcm_ops provided by work with
const snd_pcm_ops. So mark the non-const
On 08/09/2017 02:08 PM, Laurent Pinchart wrote:
Hi Arvind,
Thank you for the patch.
On Wednesday 09 Aug 2017 13:08:37 Arvind Yadav wrote:
snd_pcm_ops are not supposed to change at runtime. All functions
working with snd_pcm_ops provided by work with
const snd_pcm_ops. So mark the non-const
On 08/08/2017 09:33 PM, Laurent Pinchart wrote:
Hi Bhumika,
Thank you for the patch.
On Tuesday 08 Aug 2017 21:24:10 Bhumika Goyal wrote:
Make these structures const as they are only stored in the funcs field
of drm_bridge structure, which is of type const.
Done using Coccinelle.
On 08/08/2017 09:33 PM, Laurent Pinchart wrote:
Hi Bhumika,
Thank you for the patch.
On Tuesday 08 Aug 2017 21:24:10 Bhumika Goyal wrote:
Make these structures const as they are only stored in the funcs field
of drm_bridge structure, which is of type const.
Done using Coccinelle.
On 08/08/2017 04:58 PM, Bhumika Goyal wrote:
Declare drm_connector_funcs structures as const.
Could you rebase this series over the latest drm-misc-next? The
recently merged patch "drm: Nuke drm_atomic_helper_connector_dpms"
causes conflicts with these.
drm-misc-next:
On 08/08/2017 04:58 PM, Bhumika Goyal wrote:
Declare drm_connector_funcs structures as const.
Could you rebase this series over the latest drm-misc-next? The
recently merged patch "drm: Nuke drm_atomic_helper_connector_dpms"
causes conflicts with these.
drm-misc-next:
: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Cc: Archit Taneja <arch...@codeaurora.org>
Cc: Andrzej Hajda <a.ha...@samsung.com>
Cc: Mark Yao <mark@rock-chips.com>
Cc: Carlos Palminha <palmi...@synopsys.com>
Cc: Heiko Stübner <he...@sntech.de>
Ch
drm-misc-next branch.
Signed-off-by: Jose Abreu
Tested-by: Mark Yao
This is needed for RK3399 support. Can you please apply it?
Best regards,
Jose Miguel Abreu
Cc: Kieran Bingham
Cc: Laurent Pinchart
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Mark Yao
Cc: Carlos Palminha
Cc: Heiko Stübner
On 08/07/2017 09:39 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp.
This patch updates the year, because this driver was moved
into synopsys folder in 2017.
Thanks. Queued to drm-misc-next.
On 08/07/2017 09:39 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp.
This patch updates the year, because this driver was moved
into synopsys folder in 2017.
Thanks. Queued to drm-misc-next.
Archit
Signed-off-by: Kuninori
On 08/07/2017 09:25 AM, Kuninori Morimoto wrote:
Hi Archit
Thank you for your feedback
On 08/07/2017 07:41 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp
Can we update the year to 2017
On 08/07/2017 09:25 AM, Kuninori Morimoto wrote:
Hi Archit
Thank you for your feedback
On 08/07/2017 07:41 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp
Can we update the year to 2017 while we're at it?
The original
On 08/07/2017 07:41 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp
Can we update the year to 2017 while we're at it?
Archit
Signed-off-by: Kuninori Morimoto
On 08/07/2017 07:41 AM, Kuninori Morimoto wrote:
From: Kuninori Morimoto
This driver's Copyright is under Renesas Solutions Corp
Can we update the year to 2017 while we're at it?
Archit
Signed-off-by: Kuninori Morimoto
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 3 ++-
On 08/03/2017 05:20 PM, Arnd Bergmann wrote:
When CONFIG_PM is disabled, we get harmless warnings about unused
functions:
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1025:12: error: 'mdp5_runtime_resume'
defined but not used [-Werror=unused-function]
static int mdp5_runtime_resume(struct
On 08/03/2017 05:20 PM, Arnd Bergmann wrote:
When CONFIG_PM is disabled, we get harmless warnings about unused
functions:
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c:1025:12: error: 'mdp5_runtime_resume'
defined but not used [-Werror=unused-function]
static int mdp5_runtime_resume(struct
(for write) or rx channel
(for read) and all the registers read/write descriptors in
command channel.
Reviewed-by: Archit Taneja <arch...@codeaurora.org>
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_n
(for write) or rx channel
(for read) and all the registers read/write descriptors in
command channel.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 143 ++
1 file changed, 130 insertions(+), 13
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