[RFC v2 1/5] drm/dsi: Refactor device creation

as a standalone way to create a dsi device not available via DT. The new device creation process tries to closely follow what's been done in i2c_new_device in i2c-core. Signed-off-by: Archit Taneja --- drivers/gpu/drm/drm_mipi_dsi.c | 61 +- include/drm

[RFC v2 2/5] drm/dsi: Try to match non-DT dsi devices

m a non-DT match by comparing the device name and entries in the driver's id_table. The id_table structs for different buses are defined in "include/linux/mod_devicetable.h", I didn't want to touch that for now. Signed-off-by: Archit Taneja --- drivers/gpu/drm

[RFC v2 5/5] drm/dsi: Get DSI host by DT device node

of all the hosts DSI that are currently registered. This list will be used to find the mipi_dsi_host corresponding to the device_node passed in of_find_mipi_dsi_host_by_node. Signed-off-by: Archit Taneja --- drivers/gpu/drm/drm_mipi_dsi.c | 30 ++ include/drm

[RFC v2 4/5] drm/dsi: Add routine to unregister dsi device

. This does leave the possibility of the host removing the dsi device without the peripheral driver being aware of it. I don't know a good way to solve this. Some suggestions here would be of help too. Signed-off-by: Archit Taneja --- drivers/gpu/drm/drm_mipi_dsi.c | 7 +++ include/drm

[RFC v2 0/5] drm/dsi: DSI for devices with different control bus

driver might have an unregistered device pointer without being aware of it. Some comments on these would help. [1]: https://lkml.org/lkml/2015/6/30/42 Archit Taneja (5): drm/dsi: Refactor device creation drm/dsi: Try to match non-DT dsi devices drm/dsi: Check for used channels drm/dsi: Add

Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

Hi, On 10/06/2015 02:47 PM, Brian Norris wrote: Hi Archit, On Mon, Oct 05, 2015 at 12:21:54PM +0530, Archit Taneja wrote: On 10/02/2015 08:35 AM, Brian Norris wrote: On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x

[RFC v2 4/5] drm/dsi: Add routine to unregister dsi device

. This does leave the possibility of the host removing the dsi device without the peripheral driver being aware of it. I don't know a good way to solve this. Some suggestions here would be of help too. Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/gpu/drm/drm_mipi_dsi

[RFC v2 5/5] drm/dsi: Get DSI host by DT device node

of all the hosts DSI that are currently registered. This list will be used to find the mipi_dsi_host corresponding to the device_node passed in of_find_mipi_dsi_host_by_node. Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/gpu/drm/drm_mipi_dsi.

[RFC v2 0/5] drm/dsi: DSI for devices with different control bus

driver might have an unregistered device pointer without being aware of it. Some comments on these would help. [1]: https://lkml.org/lkml/2015/6/30/42 Archit Taneja (5): drm/dsi: Refactor device creation drm/dsi: Try to match non-DT dsi devices drm/dsi: Check for used channels drm/dsi: Add

[RFC v2 3/5] drm/dsi: Check for used channels

DT. Now that we also support creating devices manually, we could end up in a situation where a driver tries to create a device with a virtual channel already taken by a device populated in DT. Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/gpu/drm/drm_mipi_dsi.

[RFC v2 1/5] drm/dsi: Refactor device creation

as a standalone way to create a dsi device not available via DT. The new device creation process tries to closely follow what's been done in i2c_new_device in i2c-core. Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/gpu/drm/drm_mipi_dsi.

[RFC v2 2/5] drm/dsi: Try to match non-DT dsi devices

m a non-DT match by comparing the device name and entries in the driver's id_table. The id_table structs for different buses are defined in "include/linux/mod_devicetable.h", I didn't want to touch that for now. Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/g

Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

Hi Brian, Thanks for the review. On 10/02/2015 08:35 AM, Brian Norris wrote: Hi Archit, On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External

Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

Hi Brian, Thanks for the review. On 10/02/2015 08:35 AM, Brian Norris wrote: Hi Archit, On Wed, Aug 19, 2015 at 10:19:03AM +0530, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External

Re: [PATCH RFC 5/8] drm: hisilicon: fill interface function of encoder\connector part

On 9/15/2015 3:07 PM, Xinwei Kong wrote: This patch enables the adv7533 module which is connecting hisilicon SOC by dsi module. while using DSI module and adv7533 module to implement the encoder/connector interface of DRM\KMS. Signed-off-by: Xinliang Liu Signed-off-by: Xinwei Kong

Re: [PATCH RFC 2/8] drm: hisilicon: Add new DRM driver for hisilicon Soc

Hi, On 9/15/2015 3:07 PM, Xinwei Kong wrote: This patch creates this driver itself and register all the sub-components which is from DTS inode, this driver uses components framework mechanism to bind all the sub-components. This patch also introduces a memory manager for hisilison drm. As cma

[PATCH 1/2] drm/mgag200: Fix error handling paths in fbdev driver

Cc: Daniel Vetter Cc: Dave Airlie Cc: David Airlie Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Sudip Mukherjee Cc: Thomas Gleixner Cc: dri-devel Signed-off-by: Archit Taneja --- drivers/gpu/drm/mgag200/mgag200_fb.c | 31 +++ 1 file changed, 23 insertions(+), 8

[PATCH 2/2] drm/mgag200: Fix driver_load error handling

://lkml.kernel.org/r/55f6e68d.8070...@codeaurora.org Reported-by: Ingo Molnar Cc: Daniel Vetter Cc: Dave Airlie Cc: David Airlie Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Sudip Mukherjee Cc: Thomas Gleixner Cc: dri-devel Signed-off-by: Archit Taneja --- drivers/gpu/drm/mgag200/mgag200_main.c | 36

Re: [PATCH] drm/mgag200: Fix calling drm_fb_helper_fini() twice

On 9/17/2015 2:04 PM, Ingo Molnar wrote: * Ingo Molnar wrote: So this patch was whitespace damaged - I applied it by hand and made the commit below. This has solved the crash, thanks Archit! Spoke too soon - the attached (allyesconfig-ish) config still crashes, first there are

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

On 9/15/2015 9:13 PM, Rob Herring wrote: On 09/15/2015 05:32 AM, Archit Taneja wrote: Hi Rob, Mark, We've been trying to figure out the right way to represent a class of display encoder devices in DT. I've been meaning to reply on this. These devices have registers that are generally

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

On 9/15/2015 9:13 PM, Rob Herring wrote: On 09/15/2015 05:32 AM, Archit Taneja wrote: Hi Rob, Mark, We've been trying to figure out the right way to represent a class of display encoder devices in DT. I've been meaning to reply on this. These devices have registers that are generally

Re: [PATCH RFC 5/8] drm: hisilicon: fill interface function of encoder\connector part

On 9/15/2015 3:07 PM, Xinwei Kong wrote: This patch enables the adv7533 module which is connecting hisilicon SOC by dsi module. while using DSI module and adv7533 module to implement the encoder/connector interface of DRM\KMS. Signed-off-by: Xinliang Liu

Re: [PATCH] drm/mgag200: Fix calling drm_fb_helper_fini() twice

On 9/17/2015 2:04 PM, Ingo Molnar wrote: * Ingo Molnar wrote: So this patch was whitespace damaged - I applied it by hand and made the commit below. This has solved the crash, thanks Archit! Spoke too soon - the attached (allyesconfig-ish) config still crashes,

[PATCH 2/2] drm/mgag200: Fix driver_load error handling

t;pet...@infradead.org> Cc: Sudip Mukherjee <sudipm.mukher...@gmail.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: dri-devel <dri-de...@lists.freedesktop.org> Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/gpu/drm/mgag200/mgag200_main.c | 36 +

[PATCH 1/2] drm/mgag200: Fix error handling paths in fbdev driver

org> Cc: Sudip Mukherjee <sudipm.mukher...@gmail.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: dri-devel <dri-de...@lists.freedesktop.org> Signed-off-by: Archit Taneja <arch...@codeaurora.org> --- drivers/gpu/drm/mgag200/mgag200_fb.c | 31 +++ 1 fi

Re: [PATCH RFC 2/8] drm: hisilicon: Add new DRM driver for hisilicon Soc

Hi, On 9/15/2015 3:07 PM, Xinwei Kong wrote: This patch creates this driver itself and register all the sub-components which is from DTS inode, this driver uses components framework mechanism to bind all the sub-components. This patch also introduces a memory manager for hisilison drm. As cma

Re: [PATCH RFC 1/8] dt-bindings: Document the hi6220 bindings for DRM driver

Hi, On 09/16/2015 02:04 PM, Xinwei Kong wrote: hi architt On 2015/9/16 2:11, Rob Herring wrote: On 09/15/2015 04:37 AM, Xinwei Kong wrote: This adds documentation of device tree bindings for the Graphics Processing Unit of hi6220 SOC. Signed-off-by: Xinliang Liu Signed-off-by: Xinwei Kong

Re: [PATCH RFC 1/8] dt-bindings: Document the hi6220 bindings for DRM driver

Hi, On 09/16/2015 02:04 PM, Xinwei Kong wrote: hi architt On 2015/9/16 2:11, Rob Herring wrote: On 09/15/2015 04:37 AM, Xinwei Kong wrote: This adds documentation of device tree bindings for the Graphics Processing Unit of hi6220 SOC. Signed-off-by: Xinliang Liu

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

more nitty gritties discussed in this thread before. Thierry, Andrzej, Lucas, Please feel free to add your comments if I have missed out on something. Thanks, Archit On 09/10/2015 01:02 PM, Thierry Reding wrote: On Thu, Sep 10, 2015 at 11:45:35AM +0530, Archit Taneja wrote: On 09/08/2015 03:57 P

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

more nitty gritties discussed in this thread before. Thierry, Andrzej, Lucas, Please feel free to add your comments if I have missed out on something. Thanks, Archit On 09/10/2015 01:02 PM, Thierry Reding wrote: On Thu, Sep 10, 2015 at 11:45:35AM +0530, Archit Taneja wrote: On 09/08/2015 03:57 P

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

more nitty gritties discussed in this thread before. Thierry, Andrzej, Lucas, Please feel free to add your comments if I have missed out on something. Thanks, Archit On 09/10/2015 01:02 PM, Thierry Reding wrote: On Thu, Sep 10, 2015 at 11:45:35AM +0530, Archit Taneja wrote: On 09/08/2015 03:57 P

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

more nitty gritties discussed in this thread before. Thierry, Andrzej, Lucas, Please feel free to add your comments if I have missed out on something. Thanks, Archit On 09/10/2015 01:02 PM, Thierry Reding wrote: On Thu, Sep 10, 2015 at 11:45:35AM +0530, Archit Taneja wrote: On 09/08/2015 03:57 P

Re: [PATCH] drm/mgag200: fix memory leak

possible that we never tried running this driver before with Big Endian set? The patch below fixes the problem with the error path mentioned above. Could we try this? From: Archit Taneja Date: Mon, 14 Sep 2015 20:11:43 +0530 Subject: [PATCH] drm/mgag200: Prevent calling drm_fb_helper_fini twice

Re: [PATCH] drm/mgag200: fix memory leak

first place. It looks like it's failing at register_framebuffer. Is it possible that we never tried running this driver before with Big Endian set? The patch below fixes the problem with the error path mentioned above. Could we try this? From: Archit Taneja <arch...@codeaurora.org> Date: Mon, 14 Sep 2015 20:11:

Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

On 8/27/2015 5:07 AM, Stephen Boyd wrote: On 08/19, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and QPIC (Qualcomm Parallel Interface Controller). These IPs

Re: [PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

On 8/27/2015 5:07 AM, Stephen Boyd wrote: On 08/19, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) and QPIC (Qualcomm Parallel Interface Controller). These IPs

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

On 09/08/2015 03:57 PM, Andrzej Hajda wrote: On 09/07/2015 01:46 PM, Archit Taneja wrote: Thierry, On 08/21/2015 11:39 AM, Archit Taneja wrote: On 08/20/2015 05:18 PM, Thierry Reding wrote: On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote: Hi Thierry, Lucas, On 08/19/2015

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

On 09/08/2015 03:57 PM, Andrzej Hajda wrote: On 09/07/2015 01:46 PM, Archit Taneja wrote: Thierry, On 08/21/2015 11:39 AM, Archit Taneja wrote: On 08/20/2015 05:18 PM, Thierry Reding wrote: On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote: Hi Thierry, Lucas, On 08/19/2015

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

Thierry, On 08/21/2015 11:39 AM, Archit Taneja wrote: On 08/20/2015 05:18 PM, Thierry Reding wrote: On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote: Hi Thierry, Lucas, On 08/19/2015 08:32 PM, Thierry Reding wrote: On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

Thierry, On 08/21/2015 11:39 AM, Archit Taneja wrote: On 08/20/2015 05:18 PM, Thierry Reding wrote: On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote: Hi Thierry, Lucas, On 08/19/2015 08:32 PM, Thierry Reding wrote: On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote

Re: [PATCH] drm/msm/dsi: Parse lane swap information from DT

Hi, On 9/4/2015 12:00 AM, Hai Li wrote: Lane swap configuration is based on the board design. This change allows the DSI host to get this information from device tree, instead of hardcoding in driver. Signed-off-by: Hai Li --- Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++

Re: [PATCH] drm/msm/dsi: Parse lane swap information from DT

Hi, On 9/4/2015 12:00 AM, Hai Li wrote: Lane swap configuration is based on the board design. This change allows the DSI host to get this information from device tree, instead of hardcoding in driver. Signed-off-by: Hai Li ---

[PATCH] regulator: core: use debug level print in regulator_check_drms

the underlying regulator doesn't support DRMS. Signed-off-by: Archit Taneja --- drivers/regulator/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 3c3137a..f2262fa 100644 --- a/drivers/regulator/core.c +++ b

Re: [PATCH] drm: msm: dsi: Don't attempt changing voltage of switches

if (ret < 0) { Looks good to me. Reviewed-by: Archit Taneja Archit -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majo

Re: [PATCH] clk: qcom: Allow clk_set_parent() to work on display clocks

-by: Archit Taneja Cc: Archit Taneja Cc: Hai Li Signed-off-by: Stephen Boyd --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 91 + drivers/clk/qcom/gcc-msm8916.c | 14 +-- drivers/clk/qcom/mmcc-apq8084.c | 18

Re: [PATCH] clk: qcom: Allow clk_set_parent() to work on display clocks

-by: Archit Taneja arch...@codeaurora.org Cc: Archit Taneja arch...@codeaurora.org Cc: Hai Li h...@codeaurora.org Signed-off-by: Stephen Boyd sb...@codeaurora.org --- drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 91 + drivers/clk

Re: [PATCH] drm: msm: dsi: Don't attempt changing voltage of switches

good to me. Reviewed-by: Archit Taneja arch...@codeaurora.org Archit -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord

[PATCH] regulator: core: use debug level print in regulator_check_drms

the underlying regulator doesn't support DRMS. Signed-off-by: Archit Taneja arch...@codeaurora.org --- drivers/regulator/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 3c3137a..f2262fa 100644 --- a/drivers

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

On 08/20/2015 05:18 PM, Thierry Reding wrote: On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote: Hi Thierry, Lucas, On 08/19/2015 08:32 PM, Thierry Reding wrote: On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote: Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

On 08/20/2015 05:18 PM, Thierry Reding wrote: On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote: Hi Thierry, Lucas, On 08/19/2015 08:32 PM, Thierry Reding wrote: On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote: Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb

Re: [PATCH v3 0/14] Add Analogix Core Display Port Driver

Hi, On 08/19/2015 08:18 PM, Yakir Yang wrote: Hi all, The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller share the same IP, so a lot of parts can be re-used. I split the common code into bridge directory, then rk3288 and exynos only need to keep some platform code. Cause

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

Hi Thierry, Lucas, On 08/19/2015 08:32 PM, Thierry Reding wrote: On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote: Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb Thierry Reding: On Wed, Aug 19, 2015 at 04:17:08PM +0200, Lucas Stach wrote: Hi Thierry, Archit, [...] Perhaps a

Re: [RFC 1/2] drm/dsi: Create dummy DSI devices

Hi, On 08/19/2015 01:40 PM, Andrzej Hajda wrote: On 06/30/2015 07:24 AM, Archit Taneja wrote: We can have devices where the data bus is MIPI DSI, but the control bus is something else (i2c, spi etc). A typical example is i2c controlled encoder bridge chips. Such devices too require passing

Re: [RFC 1/2] drm/dsi: Create dummy DSI devices

Hi, On 08/19/2015 01:40 PM, Andrzej Hajda wrote: On 06/30/2015 07:24 AM, Archit Taneja wrote: We can have devices where the data bus is MIPI DSI, but the control bus is something else (i2c, spi etc). A typical example is i2c controlled encoder bridge chips. Such devices too require passing

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

Hi Thierry, Lucas, On 08/19/2015 08:32 PM, Thierry Reding wrote: On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote: Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb Thierry Reding: On Wed, Aug 19, 2015 at 04:17:08PM +0200, Lucas Stach wrote: Hi Thierry, Archit, [...] Perhaps a

Re: [PATCH v3 0/14] Add Analogix Core Display Port Driver

Hi, On 08/19/2015 08:18 PM, Yakir Yang wrote: Hi all, The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller share the same IP, so a lot of parts can be re-used. I split the common code into bridge directory, then rk3288 and exynos only need to keep some platform code. Cause

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

Hi, On 06/30/2015 10:54 AM, Archit Taneja wrote: We are currently restricted when it comes to supporting DSI on devices that have a non-DSI control bus. For example, DSI encoder chips are available in the market that are configured via i2c. Configuring their registers via DSI bus is either

[PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

and clean ups v2: - Use new BBT flag that allows us to read BBM in raw mode - reduce memcpy-s in the driver - some refactor and clean ups because of above changes Reviewed-by: Andy Gross Signed-off-by: Archit Taneja --- drivers/mtd/nand/Kconfig |7 + drivers/mtd/nand/Makefile |1

[PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings

Add DT bindings document for the Qualcomm NAND controller driver. Cc: devicet...@vger.kernel.org v4: - No changes v3: - Don't use '0x' when specifying nand controller address space - Add optional property for on-flash bbt usage Acked-by: Andy Gross Signed-off-by: Archit Taneja

[PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 7f9ea50..648994c 100644 --- a/arch/arm/boot/dts/qcom

[PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x

The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding compatible string. Cc: devicet...@vger.kernel.org Reviewed-by: Andy Gross Signed-off-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch

[PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode

oss Signed-off-by: Archit Taneja --- drivers/mtd/nand/nand_base.c | 6 +- drivers/mtd/nand/nand_bbt.c | 6 +- include/linux/mtd/bbm.h | 7 +++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ceb68ca..0a0c

[PATCH v4 0/5] mtd: Qualcomm NAND controller driver

ngelog. v3: - Various fixes and clean ups suggested by Stephen Boyd. v2: - Added a new BBT flag that allows us to read BBM in raw mode - reduce memcpy-s in the driver - some refactor and clean ups because of above changes v1: - original series: https://lkml.org/lkml/2015/1/16/317 Archit Tan

[PATCH v4 2/5] mtd: nand: Qualcomm NAND controller driver

in Kconfig - Misc fixes and clean ups v2: - Use new BBT flag that allows us to read BBM in raw mode - reduce memcpy-s in the driver - some refactor and clean ups because of above changes Reviewed-by: Andy Gross agr...@codeaurora.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- drivers/mtd

[PATCH v4 3/5] dt/bindings: qcom_nandc: Add DT bindings

Add DT bindings document for the Qualcomm NAND controller driver. Cc: devicet...@vger.kernel.org v4: - No changes v3: - Don't use '0x' when specifying nand controller address space - Add optional property for on-flash bbt usage Acked-by: Andy Gross agr...@codeaurora.org Signed-off-by: Archit

[PATCH v4 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

-by: Archit Taneja arch...@codeaurora.org --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 7f9ea50..648994c 100644 --- a/arch

[PATCH v4 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode

...@codeaurora.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- drivers/mtd/nand/nand_base.c | 6 +- drivers/mtd/nand/nand_bbt.c | 6 +- include/linux/mtd/bbm.h | 7 +++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers

[PATCH v4 0/5] mtd: Qualcomm NAND controller driver

: - Various fixes and clean ups suggested by Stephen Boyd. v2: - Added a new BBT flag that allows us to read BBM in raw mode - reduce memcpy-s in the driver - some refactor and clean ups because of above changes v1: - original series: https://lkml.org/lkml/2015/1/16/317 Archit Taneja (5): mtd

[PATCH v4 4/5] arm: qcom: dts: Add NAND controller node for ipq806x

The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding compatible string. Cc: devicet...@vger.kernel.org Reviewed-by: Andy Gross agr...@codeaurora.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++ 1 file

Re: [RFC 0/2] drm/dsi: DSI for devices with different control bus

Hi, On 06/30/2015 10:54 AM, Archit Taneja wrote: We are currently restricted when it comes to supporting DSI on devices that have a non-DSI control bus. For example, DSI encoder chips are available in the market that are configured via i2c. Configuring their registers via DSI bus is either

Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

On 8/4/2015 2:28 AM, Stephen Boyd wrote: On 08/03, Archit Taneja wrote: @@ -93,5 +115,19 @@ sata@2900 { status = "ok"; }; + + nand@1ac0 { + status = "ok"; + +

Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

On 8/4/2015 1:05 AM, Andy Gross wrote: On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote: Enable the NAND controller node on the AP148 platform. Provide pinmux information. Cc: devicet...@vger.kernel.org Signed-off-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064-ap148

Re: [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver

On 8/4/2015 5:08 AM, Stephen Boyd wrote: On 08/03, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. There are some checker errors and le32 usage is not correct: drivers/mtd/nand/qcom_nandc.c:383:13: warning: mixing different enum types

Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

On 8/4/2015 1:05 AM, Andy Gross wrote: On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote: Enable the NAND controller node on the AP148 platform. Provide pinmux information. Cc: devicet...@vger.kernel.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- arch/arm/boot/dts

Re: [PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver

On 8/4/2015 5:08 AM, Stephen Boyd wrote: On 08/03, Archit Taneja wrote: The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, MDM9x15 series. There are some checker errors and le32 usage is not correct: drivers/mtd/nand/qcom_nandc.c:383:13: warning: mixing different enum types

Re: [PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

On 8/4/2015 2:28 AM, Stephen Boyd wrote: On 08/03, Archit Taneja wrote: @@ -93,5 +115,19 @@ sata@2900 { status = ok; }; + + nand@1ac0 { + status = ok; + + pinctrl-0

[PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x

The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding compatible string. Cc: devicet...@vger.kernel.org Reviewed-by: Andy Gross Signed-off-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch

[PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

Enable the NAND controller node on the AP148 platform. Provide pinmux information. Cc: devicet...@vger.kernel.org Signed-off-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings

Add DT bindings document for the Qualcomm NAND controller driver. Cc: devicet...@vger.kernel.org v3: - Don't use '0x' when specifying nand controller address space - Add optional property for on-flash bbt usage Acked-by: Andy Gross Signed-off-by: Archit Taneja --- .../devicetree/bindings/mtd

[PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver

because of above changes Reviewed-by: Andy Gross Signed-off-by: Archit Taneja --- drivers/mtd/nand/Kconfig |7 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/qcom_nandc.c | 1913 + 3 files changed, 1921 insertions(+) create mode

[PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode

oss Signed-off-by: Archit Taneja --- drivers/mtd/nand/nand_base.c | 6 +- drivers/mtd/nand/nand_bbt.c | 6 +- include/linux/mtd/bbm.h | 7 +++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ceb68ca..0a0c

[PATCH v3 0/5] mtd: Qualcomm NAND controller driver

tephen Boyd. v2: - Added a new BBT flag that allows us to read BBM in raw mode - reduce memcpy-s in the driver - some refactor and clean ups because of above changes v1: - original series: https://lkml.org/lkml/2015/1/16/317 Archit Taneja (5): mtd: nand: Create a BBT flag to access bad block m

[PATCH v3 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode

...@codeaurora.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- drivers/mtd/nand/nand_base.c | 6 +- drivers/mtd/nand/nand_bbt.c | 6 +- include/linux/mtd/bbm.h | 7 +++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers

[PATCH v3 0/5] mtd: Qualcomm NAND controller driver

. v2: - Added a new BBT flag that allows us to read BBM in raw mode - reduce memcpy-s in the driver - some refactor and clean ups because of above changes v1: - original series: https://lkml.org/lkml/2015/1/16/317 Archit Taneja (5): mtd: nand: Create a BBT flag to access bad block markers

[PATCH v3 5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform

Enable the NAND controller node on the AP148 platform. Provide pinmux information. Cc: devicet...@vger.kernel.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 1 file changed, 36 insertions(+) diff --git

[PATCH v3 3/5] dt/bindings: qcom_nandc: Add DT bindings

Add DT bindings document for the Qualcomm NAND controller driver. Cc: devicet...@vger.kernel.org v3: - Don't use '0x' when specifying nand controller address space - Add optional property for on-flash bbt usage Acked-by: Andy Gross agr...@codeaurora.org Signed-off-by: Archit Taneja arch

[PATCH v3 2/5] mtd: nand: Qualcomm NAND controller driver

because of above changes Reviewed-by: Andy Gross agr...@codeaurora.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- drivers/mtd/nand/Kconfig |7 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/qcom_nandc.c | 1913 + 3 files

[PATCH v3 4/5] arm: qcom: dts: Add NAND controller node for ipq806x

The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding compatible string. Cc: devicet...@vger.kernel.org Reviewed-by: Andy Gross agr...@codeaurora.org Signed-off-by: Archit Taneja arch...@codeaurora.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++ 1 file

Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

On 7/30/2015 12:03 AM, Stephen Boyd wrote: On 07/29, Archit Taneja wrote: On 07/29/2015 07:18 AM, Stephen Boyd wrote: On 07/27/2015 09:34 PM, Archit Taneja wrote: Hi, On 07/25/2015 06:21 AM, Stephen Boyd wrote: On 07/21/2015 03:34 AM, Archit Taneja wrote: + int size

Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

On 7/30/2015 12:03 AM, Stephen Boyd wrote: On 07/29, Archit Taneja wrote: On 07/29/2015 07:18 AM, Stephen Boyd wrote: On 07/27/2015 09:34 PM, Archit Taneja wrote: Hi, On 07/25/2015 06:21 AM, Stephen Boyd wrote: On 07/21/2015 03:34 AM, Archit Taneja wrote: + int size

Re: [PATCH v1 7/7] ARM: dts: ifc6410: add inforce LVDS panel support

Hi Srini, On 07/28/2015 06:24 PM, Srinivas Kandagatla wrote: This patch adds LVDS panel for IFC6410. Signed-off-by: Rob Clark [Rob Clark: WIP patch] Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 66 ++ 1 file changed, 66

Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

On 07/29/2015 07:18 AM, Stephen Boyd wrote: On 07/27/2015 09:34 PM, Archit Taneja wrote: Hi, On 07/25/2015 06:21 AM, Stephen Boyd wrote: On 07/21/2015 03:34 AM, Archit Taneja wrote: + int size) +{Looks like a +struct desc_info *desc; +struct dma_async_tx_descriptor

Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

On 07/29/2015 07:18 AM, Stephen Boyd wrote: On 07/27/2015 09:34 PM, Archit Taneja wrote: Hi, On 07/25/2015 06:21 AM, Stephen Boyd wrote: On 07/21/2015 03:34 AM, Archit Taneja wrote: + int size) +{Looks like a +struct desc_info *desc; +struct dma_async_tx_descriptor

Re: [PATCH v1 7/7] ARM: dts: ifc6410: add inforce LVDS panel support

Hi Srini, On 07/28/2015 06:24 PM, Srinivas Kandagatla wrote: This patch adds LVDS panel for IFC6410. Signed-off-by: Rob Clark robdcl...@gmail.com [Rob Clark: WIP patch] Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 66

Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

Hi, On 07/25/2015 06:21 AM, Stephen Boyd wrote: On 07/21/2015 03:34 AM, Archit Taneja wrote: diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 5b2806a..31951fc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -538,4 +538,11 @@ config MTD_NAND_HISI504

Re: [PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

Hi, On 07/25/2015 06:21 AM, Stephen Boyd wrote: On 07/21/2015 03:34 AM, Archit Taneja wrote: diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 5b2806a..31951fc 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -538,4 +538,11 @@ config MTD_NAND_HISI504

[PATCH v2 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw mode

. This results in the nand driver's ecc->read_oob() op to be called, which works with ECC enabled. Create a new BBT option flag that tells nand_bbt to force the mode to MTD_OPS_RAW. This would result in the correct op being called for the underlying nand controller driver. Signed-off-by: Archit Tan

[PATCH v2 4/5] arm: qcom: dts: Add NAND controller node for ipq806x

The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding compatible string. Cc: devicet...@vger.kernel.org Signed-off-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064

[PATCH v2 5/5] arm: qcom: dts: Enale NAND node on IPQ8064 AP148 platform

Enable the NAND controller node on the AP148 platform. Provide pinmux information. Cc: devicet...@vger.kernel.org Signed-off-by: Archit Taneja --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v2 2/5] mtd: nand: Qualcomm NAND controller driver

NAND_BBT_ACCESS_BBM_RAW to read the factory provided bad block markers. Signed-off-by: Archit Taneja --- drivers/mtd/nand/Kconfig |7 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/qcom_nandc.c | 2019 + 3 files changed, 2027 insertions

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