Hi Rafael
On 02-Aug-19 4:03 PM, Rafael J. Wysocki wrote:
Hi All,
On top of the "Simplify the suspend-to-idle control flow" patch series
posted previously:
https://lore.kernel.org/lkml/71085220.z6FKkvYQPX@kreacher/
sanitize the suspend-to-idle flow even further.
First off, decouple EC wakeup
Hi Rafael
On 28-Jun-19 3:32 AM, Rafael J. Wysocki wrote:
On Friday, June 14, 2019 10:05:23 AM CEST Rajneesh Bhardwaj wrote:
Enables support for ICL-NNPI, which is a neural network processor for deep
learning inference. From RAPL point of view it is same as Ice Lake Mobile
processor.
Cc: "Rafae
Hi Andy
On 29-Jun-19 6:48 PM, Andy Shevchenko wrote:
On Fri, Jun 14, 2019 at 11:14 AM Rajneesh Bhardwaj
wrote:
Ice Lake Neural Network Processor for deep learning inference a.k.a.
ICL-NNPI can re-use Ice Lake Mobile regmap to enable Intel PMC Core
driver on it.
This will be postponed till ne
Hi Rafael,
On 05-Jul-19 3:43 PM, Rafael J. Wysocki wrote:
On Friday, June 28, 2019 10:21:41 AM CEST Bhardwaj, Rajneesh wrote:
On 28-Jun-19 3:32 AM, Rafael J. Wysocki wrote:
On Friday, June 14, 2019 10:05:23 AM CEST Rajneesh Bhardwaj wrote:
Enables support for ICL-NNPI, which is a neural
On 28-Jun-19 3:32 AM, Rafael J. Wysocki wrote:
On Friday, June 14, 2019 10:05:23 AM CEST Rajneesh Bhardwaj wrote:
Enables support for ICL-NNPI, which is a neural network processor for deep
learning inference. From RAPL point of view it is same as Ice Lake Mobile
processor.
Cc: "Rafael J. Wyso
Hi Rafael
On 14-Jun-19 1:09 PM, Rajneesh Bhardwaj wrote:
Enables support for ICL-NNPI, neural network processor for deep learning
inference. From RAPL point of view it is same as Ice Lake Mobile
processor.
Cc: "Rafael J. Wysocki"
Cc: linux...@vger.kernel.org
Link: https://lkml.org/lkml/2019/6/
On 12-Jun-19 10:38 PM, Andy Shevchenko wrote:
On Wed, Jun 12, 2019 at 09:33:30AM -0700, Dave Hansen wrote:
On 6/12/19 9:29 AM, Andy Shevchenko wrote:
What I'm talking is a consistency among suffixes. If there is a real
abbreviation (NNPI) which anybody can google,
There is and you can. :)
G
Hi Andy
On 04-Jun-19 9:39 PM, Andy Shevchenko wrote:
On Thu, May 30, 2019 at 06:08:27PM +0530, Rajneesh Bhardwaj wrote:
Add the CPUID model number of Icelake Neural Network Processor for Deep
I believe we spell "Ice Lake".
I referred to https://patchwork.kernel.org/patch/10812551/ ,
https:/
Sending again as i got delivery failure notification from the mailing
list for some reason.
On 05-Apr-19 8:15 PM, Andy Shevchenko wrote:
On Wed, Mar 27, 2019 at 2:47 PM Bhardwaj, Rajneesh
wrote:
On 27-Mar-19 1:59 AM, Guenter Roeck wrote:
0day reports:
drivers/platform/x86/intel_pmc_core.c
On 27-Mar-19 1:59 AM, Guenter Roeck wrote:
0day reports:
drivers/platform/x86/intel_pmc_core.c:833:5: sparse:
symbol 'quirk_xtal_ignore' was not declared. Should it be static?
Looks good to me.
Mark the function static since it is indeed only called locally.
Cc: Rajneesh Bhardwaj
Hi Rajat
On 23-Mar-19 6:00 AM, Rajat Jain wrote:
Hi Rajneesh,
On Fri, Mar 22, 2019 at 12:56 PM Bhardwaj, Rajneesh
wrote:
Some suggestions below
On 18-Mar-19 8:36 PM, Rajat Jain wrote:
On Sat, Mar 16, 2019 at 1:30 AM Rajneesh Bhardwaj
wrote:
On Wed, Mar 13, 2019 at 03:21:23PM -0700
On 21-Feb-19 7:55 PM, Andy Shevchenko wrote:
On Thu, Feb 14, 2019 at 1:56 PM Rajneesh Bhardwaj
wrote:
Changes in v3:
* Dropped reference to coreboot project as suggested by Thomas and Boris.
* Rebased onto "for-next" branch of pdx86 tree and dropped previously
accepted five patches fr
On 16-Feb-19 5:49 AM, Rajat Jain wrote:
The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register.
The pmc_core_adjust_slp_s0_step() could overflow the u32 value while
returning it after adjusting the step. Thus change to u64, this is
already accounted for in debugfs attribute (tha
On 13-Feb-19 10:58 PM, Andy Shevchenko wrote:
On Wed, Feb 13, 2019 at 5:50 PM Bhardwaj, Rajneesh
wrote:
On 13-Feb-19 9:03 PM, Andy Shevchenko wrote:
On Wed, Feb 13, 2019 at 5:08 PM Rajneesh Bhardwaj
wrote:
This patch series provides Icelake support for PMC Core driver and while
doing so
On 13-Feb-19 10:10 PM, Dave Hansen wrote:
On 2/13/19 8:35 AM, Bhardwaj, Rajneesh wrote:
I sure did, perhaps it wasn't clear in my response. I can remove
coreboot link in next version but please clarify whether i should keep
other link that i mentioned or just keep the commit without any
+0530, Bhardwaj, Rajneesh wrote:
Icelake related information is available here
https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html
but it may require a login either with Intel or a Partner ID.
The CPUID mentioned in this docume
On 13-Feb-19 9:03 PM, Andy Shevchenko wrote:
On Wed, Feb 13, 2019 at 5:08 PM Rajneesh Bhardwaj
wrote:
This patch series provides Icelake support for PMC Core driver and while
doing so it introduces the Icelake Mobile to intel-family.h as per the
CPUID from below Coreboot link
https://github.c
On 13-Feb-19 8:53 PM, Borislav Petkov wrote:
On Wed, Feb 13, 2019 at 08:38:06PM +0530, Rajneesh Bhardwaj wrote:
Add CPUID of Icelake (ICL) mobile processors to Intel family list. The
information related to ICL CPUID is referenced from below Coreboot
project link.
https://github.com/coreboot/c
On 13-Feb-19 8:51 PM, mario.limoncie...@dell.com wrote:
-Original Message-
From: platform-driver-x86-ow...@vger.kernel.org On Behalf Of Rajneesh Bhardwaj
Sent: Wednesday, February 13, 2019 9:08 AM
To: platform-driver-...@vger.kernel.org
Cc: dvh...@infradead.org; a...@infradead.org; l
On 12-Feb-19 3:48 PM, Andy Shevchenko wrote:
On Tue, Feb 12, 2019 at 11:46 AM Anshuman Gupta
wrote:
On Fri, Feb 01, 2019 at 01:02:32PM +0530, Rajneesh Bhardwaj wrote:
Icelake can resue most of the CNL PCH IPs as they are mostly similar.
This patch enables the PMC Core driver for ICL family.
On 07-Feb-19 9:25 PM, Andy Shevchenko wrote:
On Thu, Feb 7, 2019 at 4:06 AM Bhardwaj, Rajneesh
wrote:
On 07-Feb-19 4:27 AM, Stephen Rothwell wrote:
Hi all,
In commit
4284dc008f43 ("platform/x86: intel_pmc_core: Fix file permissions for
ltr_show")
Fixes tag
Fixes: 63
On 12-Feb-19 3:55 PM, Andy Shevchenko wrote:
On Mon, Feb 11, 2019 at 8:32 PM Bhardwaj, Rajneesh
wrote:
On 11-Feb-19 10:11 PM, Anshuman Gupta wrote:
On Fri, Feb 01, 2019 at 01:02:33PM +0530, Rajneesh Bhardwaj wrote:
This patch introduces a new debugfs entry to read current Package
cstate
On 11-Feb-19 10:11 PM, Anshuman Gupta wrote:
On Fri, Feb 01, 2019 at 01:02:33PM +0530, Rajneesh Bhardwaj wrote:
This patch introduces a new debugfs entry to read current Package
cstate residency counters. A similar variant of this patch was discussed
earlier "https://patchwork.kernel.org/patch/9
On 05-Feb-19 11:36 PM, Andy Shevchenko wrote:
On Fri, Feb 1, 2019 at 9:32 AM Rajneesh Bhardwaj
wrote:
This patch series provides Icelake support for PMC Core driver and while
doing so it introduces the Icelake Mobile to intel-family.h as per the
CPUID from below Coreboot link
https://github.c
On 04-Feb-19 11:04 PM, Thomas Gleixner wrote:
On Fri, 1 Feb 2019, Rajneesh Bhardwaj wrote:
Add CPUID of Icelake (ICL) mobile processors to Intel family list. The
Information related to ICL CPUID is referenced from below Coreboot
project link.
https://github.com/coreboot/coreboot/blob/5ebcea3
On 03-Nov-18 12:02 AM, Andy Shevchenko wrote:
On Fri, Nov 2, 2018 at 12:37 PM Rajneesh Bhardwaj
wrote:
The LTR values follow PCIE LTR encoding format and can be decoded as per
https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf
This adds suppo
Thanks again for your time. My response inline.
On 02-Nov-18 11:57 PM, Andy Shevchenko wrote:
On Fri, Nov 2, 2018 at 12:29 PM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
Hi Andy,
Thanks for your review. My comments below.
If you agree then i can quickly send v3 addressing all suggestions so we
can make it in time for 4.20 merge window.
On 19-Oct-18 6:04 PM, Andy Shevchenko wrote:
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
wrote:
The LTR values follo
On 19-Oct-18 6:09 PM, Andy Shevchenko wrote:
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
wrote:
On some Goldmont based systems such as ASRock J3455M the BIOS may not
enable the IPC1 device that provides access to the PMC and PUNIT. In
such scenarios, the IOSS and PSS resources from the
+ Srinivas
On 19-Oct-18 5:42 PM, Andy Shevchenko wrote:
On Sat, Oct 6, 2018 at 9:54 AM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as
On 09-Oct-18 5:07 PM, Andy Shevchenko wrote:
On Mon, Oct 8, 2018 at 5:44 PM Rajneesh Bhardwaj
wrote:
Add myself and David as the new maintainers for Intel Telemetry driver.
There is no explanation why.
(Like previous one left the company, and / or you are doing set of the
drivers related t
Thank you.
On 26-Sep-18 7:27 PM, Andy Shevchenko wrote:
On Mon, Sep 3, 2018 at 9:05 PM Rajneesh Bhardwaj
wrote:
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint
PCH so make the LTR ignore platform specific.
This looks fine to me.
Signed-off-by: Rajneesh Bhardwaj
---
On 26-Sep-18 7:26 PM, Andy Shevchenko wrote:
On Mon, Sep 3, 2018 at 9:05 PM Rajneesh Bhardwaj
wrote:
On some Goldmont based systems such as ASRock J3455M the BIOS may not
enable the IPC1 device that provides access to the PMC and PUNIT. In
such scenarios, the ioss and pss resources from the
On 26-Sep-18 7:23 PM, Andy Shevchenko wrote:
On Mon, Sep 3, 2018 at 9:05 PM Rajneesh Bhardwaj
wrote:
The LTR values follow PCIE LTR encoding format and can be decoded as per
https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf
This adds support
On 26-Sep-18 7:18 PM, Andy Shevchenko wrote:
On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as per the P
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