/microchip/microchip-mpfs.dtsi| 329 ++
> 4 files changed, 404 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> create mode 100644
> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>
Reviewed-by: Bin Meng
Hi Vitaly,
On Tue, Dec 22, 2020 at 4:39 AM Vitaly Wool wrote:
>
> Introduce XIP (eXecute In Place) support for RISC-V platforms.
> It allows code to be executed directly from non-volatile storage
> directly addressable by the CPU, such as QSPI NOR flash which can
> be found on many RISC-V
Hi Atish,
On Thu, Dec 17, 2020 at 4:43 PM Atish Patra wrote:
>
> On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
> >
> > Hi Atish,
> >
> > On Thu, Dec 17, 2020 at 3:49 PM Atish Patra wrote:
> > >
> > > memblock_enforce_memory_limit accepts th
ots, but 32-bit 'sifive_u' still does not boot, which
should be another issue because reverting the original 1bd14a66ee52 it
still does not help 'sifive_u'.
Tested-by: Bin Meng
I believe the following tag should also be added and patch cc'ed to
stable-kernel:
Reported-by: Bin Meng
Cc: # 5.10
Regards,
Bin
Hi Yash,
On Wed, Dec 16, 2020 at 1:24 PM Yash Shah wrote:
>
> > -Original Message-
> > From: Bin Meng
> > Sent: 10 December 2020 19:05
> > To: Yash Shah
> > Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> > p...@vger.kerne
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah wrote:
>
> Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
FU740-C000 Soc
> around the SiFIve U7 Core Complex and a TileLink interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
>
h/riscv/boot/dts/sifive/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb
> +dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \
> + hifive-unmatched-a00.dtb
Otherwise LGTM:
Reviewed-by: Bin Meng
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
Reviewed-by: Bin Meng
| 6 ++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Bin Meng
On Fri, Dec 4, 2020 at 5:07 PM Atish Patra wrote:
>
> From: Conor Dooley
>
> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
> directory
>
> Signed-off-by: Conor Dooley
> ---
> MAINTAINERS | 8
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Bin Meng
On Fri, Dec 4, 2020 at 5:05 PM Atish Patra wrote:
>
> Add initial DTS for Microchip ICICLE board having only
> essential devices (clocks, sdhci, ethernet, serial, etc).
> The device tree is based on the U-Boot patch.
>
>
On Sat, Nov 14, 2020 at 4:29 AM Atish Patra wrote:
>
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
typo: devices
> The device tree is based on the U-Boot patch.
>
>
> different as both of those behaviors were allowed by specifications at some
> > point. IIRC there were also some TLB shootdown issues floating
> >
> > The best I can come up with is to add both some sort of "minimum support
> > specification version" Kconfi
On Thu, Oct 29, 2020 at 6:42 PM Ben Dooks wrote:
>
> On 28/10/2020 23:27, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra
> > ---
> > arch/riscv/boot/dts/Makefile
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Bin Meng
On Fri, Oct 30, 2020 at 5:08 PM Anup Patel wrote:
>
> On Thu, Oct 29, 2020 at 4:58 AM Atish Patra wrote:
> >
> > Add initial DTS for Microchip ICICLE board having only
> > essential devcies (clocks, sdhci, ethernet, serial, etc).
> >
> > Signed-off-by: Atish Patra
> > ---
> >
ire SoC platforms.
> +
> config SOC_KENDRYTE
> bool "Kendryte K210 SoC"
> depends on !MMU
> --
Otherwise LGTM
Reviewed-by: Bin Meng
On Fri, Jul 17, 2020 at 12:39 AM Alistair Francis
wrote:
>
> On Wed, 2020-07-15 at 21:39 -0700, Bin Meng wrote:
> > From: Bin Meng
> >
> > This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> > 64-bit config. This is useful when testing 32-bit kern
From: Bin Meng
This adds SiFive drivers to rv32_defconfig, to keep in sync with the
64-bit config. This is useful when testing 32-bit kernel with QEMU
'sifive_u' 32-bit machine.
Signed-off-by: Bin Meng
---
arch/riscv/configs/rv32_defconfig | 5 +
1 file changed, 5 insertions(+)
diff
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
Changes in v2:
- add CONFIG_MTD_SPI_NOR=y in axm55xx_defconfig
arch/arm/configs/axm55xx_defconfig | 2 +-
arch/a
On Sat, May 2, 2020 at 12:45 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Drop CONFIG_MTD_M25P80 that was removed in
> commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - corr
Hi Nicolas,
On Wed, May 6, 2020 at 12:26 AM Nicolas Saenz Julienne
wrote:
>
> On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
> may either be loaded directly from an EEPROM or, if not present, by the
> SoC's VideCore (the SoC's co-processor). Introduce the function that
Hi Geert,
On Sat, May 2, 2020 at 6:09 PM Geert Uytterhoeven wrote:
>
> Hi Bin,
>
> On Sat, May 2, 2020 at 6:27 AM Bin Meng wrote:
> > From: Bin Meng
> >
> > Drop CONFIG_MTD_M25P80 that was removed in
> > commit b35b9a10362d ("mtd: spi-nor: Move m25p
From: Bin Meng
CONFIG_MTD_M25P80 was removed and replaced by CONFIG_MTD_SPI_NOR in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
Changes in v2:
- add CONFIG_MTD_SPI_NOR=y
arch/sh/configs/sh7757lcr_defconfig | 2 +-
1 file
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
Changes in v2:
- add CONFIG_MTD_SPI_NOR=y in axm55xx_defconfig
arch/arm/configs/axm55xx_defconfig | 2 +-
arch/a
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
Changes in v2:
- correct the typo (5xx => 85xx) in the commit title
arch/powerpc/configs/85xx-hw.config | 1 -
1 fi
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
arch/m68k/configs/stmark2_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/m68k/configs/stmark2_defconfig
b
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
arch/powerpc/configs/85xx-hw.config | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/configs/85xx-hw.config
b/ar
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
arch/sh/configs/sh7757lcr_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/sh/configs/sh7757lcr_defconfig
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
arch/mips/configs/ath79_defconfig | 1 -
arch/mips/configs/db1xxx_defconfig| 1 -
arch/mips/configs/gen
From: Bin Meng
Drop CONFIG_MTD_M25P80 that was removed in
commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
Signed-off-by: Bin Meng
---
arch/arm/configs/axm55xx_defconfig | 1 -
arch/arm/configs/davinci_all_defconfig | 1 -
arch/arm/configs/dove_defconfig
ked at people's instructions of booting
Linux kernel, and they seem to have such:
=> cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x1
=> bootm ${kernel_addr_r} - ${fdt_addr_r}
where ${fdt_addr_r} is 0x8800, and "bootm 8400 - 8800"
can make the kernel boot.
Thanks for the patch
Hi,
On Tue, Sep 10, 2019 at 2:14 PM Christoph Hellwig wrote:
>
> On Thu, Sep 05, 2019 at 05:45:53AM -0700, Bin Meng wrote:
> > The "clock-frequency" property of cpu nodes isn't required. Drop it.
> >
> > Signed-off-by: Bin Meng
>
> Looks good:
>
Hi,
On Tue, Sep 10, 2019 at 2:14 PM Christoph Hellwig wrote:
>
> On Thu, Sep 05, 2019 at 05:46:14AM -0700, Bin Meng wrote:
> > U-Boot expects this alias to be in place in order to fix up the mac
> > address of the ethernet node.
> >
> > Signed-off-by: Bin Meng
Hi,
On Wed, Oct 17, 2018 at 9:01 AM Atish Patra wrote:
>
> On 10/10/18 5:35 AM, Linus Walleij wrote:
> > Hi Atish,
> >
> > thanks for your patch!
> >
> > On Tue, Oct 9, 2018 at 8:51 PM Atish Patra wrote:
> >
> >> From: "Wesley W. Terpstra"
> >>
> >> Adds the GPIO driver for SiFive RISC-V SoCs.
U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.
Signed-off-by: Bin Meng
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive
The "clock-frequency" property of cpu nodes isn't required. Drop it.
Signed-off-by: Bin Meng
---
Changes in v2:
- drop "clock-frequency" property of cpu nodes
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/riscv/b
On Tue, Aug 13, 2019 at 11:00 PM Paul Walmsley wrote:
>
> On Tue, 6 Aug 2019, Bin Meng wrote:
>
> > Add the missing "clock-frequency" property to the cpu0/cpu1 nodes
> > for consistency with other cpu nodes.
> >
> > Signed-off-by: Bin Meng
>
> I
On Tue, Aug 13, 2019 at 8:40 PM Sagar Shrikant Kadam
wrote:
>
> Update spi_nor_id table for is25wp256 (32MB) device from ISSI,
> present on HiFive Unleashed dev board (Rev: A00).
>
> Set method to enable quad mode for ISSI device in flash parameters
> table.
>
> Based on code originally written
On Wed, Aug 7, 2019 at 2:22 PM Bin Meng wrote:
>
> Add the missing "clock-frequency" property to the cpu0/cpu1 nodes
> for consistency with other cpu nodes.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
ping
On Thu, Aug 1, 2019 at 5:53 PM Bin Meng wrote:
>
> On Sun, Jul 28, 2019 at 5:30 PM Bin Meng wrote:
> >
> > The base address of msi-controller@c should be set to c.
> >
> > Signed-off-by: Bin Meng
> > ---
> >
> > Documentation/devicetree/bindings
On Thu, Aug 1, 2019 at 5:53 PM Bin Meng wrote:
>
> On Sun, Jul 28, 2019 at 5:30 PM Bin Meng wrote:
> >
> > The unit-address must match the first address specified in the
> > reg property of the node.
> >
> > Signed-off-by: Bin Meng
> > ---
> >
Since commit a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers"),
we should prefer accessing CSRs using their CSR numbers, but there
are several leftovers like sstatus / sptbr we missed.
Signed-off-by: Bin Meng
Reviewed-by: Anup Patel
---
Changes in v3:
- remove the SoB tag p
Since commit a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers"),
we should prefer accessing CSRs using their CSR numbers, but there
are several leftovers like sstatus / sptbr we missed.
Signed-off-by: Bin Meng
Signed-off-by: Christoph Hellwig
Signed-off-by: Andreas Schwab
Reviewe
ey
> Cc: Atish Patra
>
> ---
> arch/riscv/Kconfig | 10 --
> arch/riscv/Makefile | 2 +-
> 2 files changed, 1 insertion(+), 11 deletions(-)
>
Reviewed-by: Bin Meng
Add the missing "clock-frequency" property to the cpu0/cpu1 nodes
for consistency with other cpu nodes.
Signed-off-by: Bin Meng
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/risc
On Sun, Jul 28, 2019 at 5:30 PM Bin Meng wrote:
>
> The unit-address must match the first address specified in the
> reg property of the node.
>
> Signed-off-by: Bin Meng
> ---
>
> Documentation/devicetree/bindings/pci/pci-msi.txt | 2 +-
> 1 file changed, 1 insertion
On Sun, Jul 28, 2019 at 5:30 PM Bin Meng wrote:
>
> The base address of msi-controller@c should be set to c.
>
> Signed-off-by: Bin Meng
> ---
>
> Documentation/devicetree/bindings/interrupt-controller/msi.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 de
On Thu, Aug 1, 2019 at 3:37 AM Paul Walmsley wrote:
>
> On Sun, 28 Jul 2019, Bin Meng wrote:
>
> > The spec does not mention 40-bit physical addresses, but 56-bit.
>
> Thanks, agreed. Updated patch below
>
>
> - Paul
>
> From: Paul Walmsley
> Date: Fr
M || ARM64 || X86 || RISCV
> depends on PCI_MSI
> select GENERIC_MSI_IRQ_DOMAIN
>
> --
Reviewed-by: Bin Meng
C, not the SoC itself. Drop the superfluous
> timebase-frequency property from the SoC DT data. (It's already
> present in the board DT data.)
>
> Signed-off-by: Paul Walmsley
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Bin Meng
On Sat, Jul 27, 2019 at 4:00 AM Paul Walmsley wrote:
>
>
> The RISC-V specifications currently define three virtual memory
> translation systems: Sv32, Sv39, and Sv48. Sv32 is currently specific
> to 32-bit systems; Sv39 and Sv48 are currently specific to 64-bit
> systems. The current kernel
l Walmsley
> ---
> arch/riscv/configs/defconfig | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
Reviewed-by: Bin Meng
The unit-address must match the first address specified in the
reg property of the node.
Signed-off-by: Bin Meng
---
Documentation/devicetree/bindings/pci/pci-msi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/pci-msi.txt
b
The base address of msi-controller@c should be set to c.
Signed-off-by: Bin Meng
---
Documentation/devicetree/bindings/interrupt-controller/msi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi.txt
b
ummary, this patch reduces
> Linux-4.20-rc4 flat kernel Image size by 809 KB.
>
> Signed-off-by: Anup Patel
> ---
>
> Changes since v1:
> - Introduce MAX_BYTES_PER_LONG define and use it in-place of
>0x10 magic value
>
> arch/riscv/kernel/vmlinux.lds.S | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng
sing GCC 8.2.0. In summary,
> this patch reduces Linux-4.20-rc4 flat kernel Image size by 809 KB.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/kernel/vmlinux.lds.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
sing GCC 8.2.0. In summary,
> this patch reduces Linux-4.20-rc4 flat kernel Image size by 809 KB.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/kernel/vmlinux.lds.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng
Tested-by: Bin Meng
.lds.S | 2 +-
> >> 6 files changed, 120 insertions(+), 2 deletions(-)
> >> create mode 100644 arch/riscv/boot/.gitignore
> >> create mode 100644 arch/riscv/boot/Makefile
> >> create mode 100644 arch/riscv/boot/install.sh
> >>
> >
> > Reviewed-by: Bin Meng
> >
> > Tested with U-Boot s-mode on QEMU virt, using bootm to boot the kernel
> > Tested-by: Bin Meng
>
> I also won't include the tags unless I rewrite the tags.
>
> Thanks for the review!
Thanks. Let's go with this as it's a minor nits.
Regards,
Bin
.lds.S | 2 +-
> >> 6 files changed, 120 insertions(+), 2 deletions(-)
> >> create mode 100644 arch/riscv/boot/.gitignore
> >> create mode 100644 arch/riscv/boot/Makefile
> >> create mode 100644 arch/riscv/boot/install.sh
> >>
> >
> > Reviewed-by: Bin Meng
> >
> > Tested with U-Boot s-mode on QEMU virt, using bootm to boot the kernel
> > Tested-by: Bin Meng
>
> I also won't include the tags unless I rewrite the tags.
>
> Thanks for the review!
Thanks. Let's go with this as it's a minor nits.
Regards,
Bin
| 60 +
> arch/riscv/kernel/head.S| 10 ++
> arch/riscv/kernel/vmlinux.lds.S | 2 +-
> 6 files changed, 120 insertions(+), 2 deletions(-)
> create mode 100644 arch/riscv/boot/.gitignore
> create mode 100644 arch/riscv/boot/Makefile
&
| 60 +
> arch/riscv/kernel/head.S| 10 ++
> arch/riscv/kernel/vmlinux.lds.S | 2 +-
> 6 files changed, 120 insertions(+), 2 deletions(-)
> create mode 100644 arch/riscv/boot/.gitignore
> create mode 100644 arch/riscv/boot/Makefile
&
Hi Bjorn,
On Wed, Oct 10, 2018 at 1:02 AM Bjorn Helgaas wrote:
>
> On Mon, Oct 08, 2018 at 05:44:08PM +0800, Bin Meng wrote:
> > On Thu, Oct 4, 2018 at 4:12 AM Bjorn Helgaas wrote:
> > > On Thu, Sep 27, 2018 at 10:10:07AM +0800, Bin Meng wrote:
> > > > On Th
Hi Bjorn,
On Wed, Oct 10, 2018 at 1:02 AM Bjorn Helgaas wrote:
>
> On Mon, Oct 08, 2018 at 05:44:08PM +0800, Bin Meng wrote:
> > On Thu, Oct 4, 2018 at 4:12 AM Bjorn Helgaas wrote:
> > > On Thu, Sep 27, 2018 at 10:10:07AM +0800, Bin Meng wrote:
> > > > On Th
Signed-off-by: Bin Meng <bmeng...@gmail.com>
---
drivers/mtd/spi-nor/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index abf453a..be7cfb9 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi
The idea to have the intel-spi driver dependent on EXPERT was exactly
because we did not want ordinary users playing with the device and
inadvertently overwrite their BIOSes (if it is not protected). This
seems to be superfluous hence remove it.
Suggested-by: Arnd Bergmann
Signed-off-by: Bin
Hi Mika,
On Mon, Oct 23, 2017 at 8:12 PM, Mika Westerberg
<mika.westerb...@linux.intel.com> wrote:
> On Sun, Oct 15, 2017 at 09:38:57PM +0800, Bin Meng wrote:
>> > Also, the 'depends on EXPERT' statement looks misplaced,
>> > enabling EXPERT should only be there to a
Hi Mika,
On Mon, Oct 23, 2017 at 8:12 PM, Mika Westerberg
wrote:
> On Sun, Oct 15, 2017 at 09:38:57PM +0800, Bin Meng wrote:
>> > Also, the 'depends on EXPERT' statement looks misplaced,
>> > enabling EXPERT should only be there to allow you to turn
>> > extra th
The Intel SPI-NOR driver is dependent on LPC_ICH to get the platform
data. Select it in the Kconfig.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
---
Changes in v2:
- Enforce dependency on PCI
drivers/mtd/spi-nor/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
The Intel SPI-NOR driver is dependent on LPC_ICH to get the platform
data. Select it in the Kconfig.
Signed-off-by: Bin Meng
---
Changes in v2:
- Enforce dependency on PCI
drivers/mtd/spi-nor/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor
Hi Arnd,
On Fri, Oct 13, 2017 at 7:15 PM, Arnd Bergmann <a...@arndb.de> wrote:
> On Wed, Oct 11, 2017 at 10:03 AM, Cyrille Pitchen
> <cyrille.pitc...@wedev4u.fr> wrote:
>> Le 25/08/2017 à 10:12, Bin Meng a écrit :
>>> The Intel SPI-NOR driver is dependent on LPC
Hi Arnd,
On Fri, Oct 13, 2017 at 7:15 PM, Arnd Bergmann wrote:
> On Wed, Oct 11, 2017 at 10:03 AM, Cyrille Pitchen
> wrote:
>> Le 25/08/2017 à 10:12, Bin Meng a écrit :
>>> The Intel SPI-NOR driver is dependent on LPC_ICH to get the platform
>>> data. Select it
Hi Joakim,
On Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund
<joakim.tjernl...@infinera.com> wrote:
> On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:
>> This series does several bug fixes and clean ups against the intel-spi
>> spi-nor driver, as well as enhancemen
Hi Joakim,
On Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund
wrote:
> On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:
>> This series does several bug fixes and clean ups against the intel-spi
>> spi-nor driver, as well as enhancements to make the driver independent
>> o
intel_spi_hw_cycle() and intel_spi_sw_cycle() don't use the parameter
'buf' at all. Remove it.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 14 ++
1 fil
intel_spi_hw_cycle() and intel_spi_sw_cycle() don't use the parameter
'buf' at all. Remove it.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers
Intel SPI controller only has a 64 bytes FIFO. This adds a sanity
check before triggering any HW/SW sequencer work.
Additionally for the SW sequencer, if given data length is zero,
we should not mark the 'Data Cycle' bit.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika West
Intel SPI controller only has a 64 bytes FIFO. This adds a sanity
check before triggering any HW/SW sequencer work.
Additionally for the SW sequencer, if given data length is zero,
we should not mark the 'Data Cycle' bit.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2
up
the flash opcode every time.
While we are here, the missing 'Atomic Cycle Sequence' handling in the
SW sequencer codes is also added.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in v2: None
drivers/mtd/s
So far intel_spi_write() uses the HW sequencer to do the write. But
the HW sequencer register HSFSTS_CTL does not have such a field for
'Atomic Cycle Sequence', remove it.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
C
up
the flash opcode every time.
While we are here, the missing 'Atomic Cycle Sequence' handling in the
SW sequencer codes is also added.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 91 +
1
So far intel_spi_write() uses the HW sequencer to do the write. But
the HW sequencer register HSFSTS_CTL does not have such a field for
'Atomic Cycle Sequence', remove it.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 5 -
1
unprogrammed by some bootloaders.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a
unprogrammed by some bootloaders.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel
the erase operation does not report
any error, the flash remains not erased.
If such register setting is detected, let's fall back to use the SW
sequencer to erase instead.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
C
There are two bugs in current intel_spi_sw_cycle():
- The 'data byte count' field should be the number of bytes
transferred minus 1
- SSFSTS_CTL is the offset from ispi->sregs, not ispi->base
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Cc: <sta...@vger.kernel.org> # v4.
the erase operation does not report
any error, the flash remains not erased.
If such register setting is detected, let's fall back to use the SW
sequencer to erase instead.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2:
- Fix typo of 'operatoin'
drivers/mtd/spi-nor
There are two bugs in current intel_spi_sw_cycle():
- The 'data byte count' field should be the number of bytes
transferred minus 1
- SSFSTS_CTL is the offset from ispi->sregs, not ispi->base
Signed-off-by: Bin Meng
Cc: # v4.11+
Acked-by: Mika Westerberg
---
Changes in v2:
- Add
There is no code that alters the HSFSTS register content in between
in intel_spi_write(). Remove the unnecessary RW to save some cycles.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in v2: None
drivers/mtd/s
There is no code that alters the HSFSTS register content in between
in intel_spi_write(). Remove the unnecessary RW to save some cycles.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 5 ++---
1 file changed, 2 insertions(+), 3
The ispi->swseq is used for register access. Let's rename it to
swseq_reg to better describe its usage.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 16 -
The ispi->swseq is used for register access. Let's rename it to
swseq_reg to better describe its usage.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --
of 'operatoin' (patch [10/10])
- Add Mika Westerberg's 'Acked-by' tag
Bin Meng (10):
spi-nor: intel-spi: Fix number of protected range registers for
BYT/LPT
spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycle
spi-nor: intel-spi: Fix broken software sequencing codes
spi
The number of protected range registers is not the same on BYT/LPT/
BXT. GPR0 only exists on Apollo Lake and its offset is reserved on
other platforms.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
Acked-by: Mika Westerberg <mika.westerb...@linux.intel.com>
---
Changes in v2: None
of 'operatoin' (patch [10/10])
- Add Mika Westerberg's 'Acked-by' tag
Bin Meng (10):
spi-nor: intel-spi: Fix number of protected range registers for
BYT/LPT
spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycle
spi-nor: intel-spi: Fix broken software sequencing codes
spi
The number of protected range registers is not the same on BYT/LPT/
BXT. GPR0 only exists on Apollo Lake and its offset is reserved on
other platforms.
Signed-off-by: Bin Meng
Acked-by: Mika Westerberg
---
Changes in v2: None
drivers/mtd/spi-nor/intel-spi.c | 16 +++-
1 file
Hi Marek,
On Fri, Sep 1, 2017 at 5:52 PM, Marek Vasut <marek.va...@gmail.com> wrote:
> On 09/01/2017 10:00 AM, Bin Meng wrote:
>> The number of protected range registers is not the same on BYT/LPT/
>> BXT. GPR0 only exists on Apollo Lake and its offset is reserved
Hi Marek,
On Fri, Sep 1, 2017 at 5:52 PM, Marek Vasut wrote:
> On 09/01/2017 10:00 AM, Bin Meng wrote:
>> The number of protected range registers is not the same on BYT/LPT/
>> BXT. GPR0 only exists on Apollo Lake and its offset is reserved on
>> other platforms.
>>
booting from
Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP
does not set up some SPI controller settings to make the driver happy.
Now such limitation has been removed with this series.
Bin Meng (10):
spi-nor: intel-spi: Fix number of protected range registers for
BYT
The number of protected range registers is not the same on BYT/LPT/
BXT. GPR0 only exists on Apollo Lake and its offset is reserved on
other platforms.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
---
drivers/mtd/spi-nor/intel-spi.c | 16 +++-
1 file changed, 11 insertions
1 - 100 of 124 matches
Mail list logo
