On Wed, 30 Jan 2019 15:08:29 +
wrote:
> From: Tudor Ambarus
>
> Set the QSPI controller in Serial Memory Mode at init and not
> at each exec_op() call.
If you ever want to support regular SPI you'll have to put it back to
atmel_qspi_exec_op(), so I'm not sure this is a good move. Another
Hi Greg,
On Wed, 30 Jan 2019 15:50:54 +0100
Greg Kroah-Hartman wrote:
> On Tue, Jan 29, 2019 at 08:02:37PM +0100, Geert Uytterhoeven wrote:
> > Hi Boris,
> >
> > On Fri, Jan 18, 2019 at 11:07 PM Boris Brezillon
> > wrote:
> > > Did you consider converti
On Tue, 29 Jan 2019 20:02:37 +0100
Geert Uytterhoeven wrote:
> Hi Boris,
>
> On Fri, Jan 18, 2019 at 11:07 PM Boris Brezillon
> wrote:
> > Did you consider converting this driver to spimem? Looks like the
> > protocol used to communicate with the memory resembles the o
the logic to actually handle both flags separately.
>
> Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_amd.c | 2 +-
> drivers/mtd/nand/raw/nand_base.c | 6 --
> drivers/mtd/nand/raw/nand_bbt.c | 3 ++-
> dri
On Wed, 30 Jan 2019 13:01:44 +
Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> The information about where the manufacturer puts the bad block
> markers inside the bad block and in the OOB data is stored in
> different places. Let's move this information to nand_chip.options
> and
On Wed, 30 Jan 2019 08:15:25 +0100
Marek Vasut wrote:
> >> > So far as I know that HF is provided by Cypress only and
> >> > any mass production product use the component which is provided by only
> >> > one provider
> >> > will be a big risk.
> >> >
> >> > Compare to HF, there are more provider
The #mtd channel (on OFTC servers) is being used to discuss MTD related
topics. Add it to the MTD entry.
Signed-off-by: Boris Brezillon
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 51029a425dbe..7b39ba46384a 100644
--- a/MAINTAINERS
+++ b
On Tue, 29 Jan 2019 16:07:43 +
Piotr Sroka wrote:
> This patch adds driver for Cadence HPNFC NAND controller.
>
> Signed-off-by: Piotr Sroka
> ---
> drivers/mtd/nand/raw/Kconfig|8 +
> drivers/mtd/nand/raw/Makefile |1 +
> drivers/mtd/nand/raw/cadence_nand.c | 2655
Hi Piotr,
On Tue, 29 Jan 2019 16:10:40 +
Piotr Sroka wrote:
> Signed-off-by: Piotr Sroka
> ---
> .../devicetree/bindings/mtd/cadence-nand.txt | 35
> ++
> 1 file changed, 35 insertions(+)
> create mode 100644
On Tue, 29 Jan 2019 11:17:00 +1100
Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the mtd tree got a conflict in:
>
> drivers/mtd/mtdpart.c
>
> between commit:
>
> 2b6f0090a333 ("mtd: Check add_mtd_device() ret code")
>
> from Linus' tree and commit:
>
>
On Tue, 29 Jan 2019 08:31:19 +
Yogesh Narayan Gaur wrote:
> Add MODULE_LICENSE info to fix below warning:
> WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
>
You miss Fixes and Reported-by tags here.
> Signed-off-by: Yogesh Narayan Gaur
> ---
>
d/nand/raw/nand_bbt.c:173: warning: Function parameter or member
> 'this' not described in 'read_bbt'
> ../drivers/mtd/nand/raw/nand_bbt.c:173: warning: Excess function parameter
> 'chip' description in 'read_bbt'
>
> Signed-off-by: Randy Dunlap
> Cc: Boris Brezillon
> C
On Fri, 2019-01-25 at 02:12:42 UTC, YueHaibing wrote:
> In case DOC_CHIPID_G3, mtd->name is not freed in err handling path,
> which is alloced by kasprintf(). Fix this by using devm_kasprintf().
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
On Wed, 2019-01-23 at 06:58:27 UTC, YueHaibing wrote:
> Fix a static code checker warning:
> drivers/mtd/devices/docg3.c:1875
> doc_probe_device() warn: passing zero to 'ERR_PTR'
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
> Acked-by: Robert
On Thu, 10 Jan 2019 15:10:28 +
Peter Rosin wrote:
> Hi!
>
> I found an unfortunate issue while recoding plane handling to use
> drm_atomic_helper_check_plane_state(). The driver rotates clockwise,
> which is not correct. I simply fixed it (patch 1/4), but maybe that
> will cause regressions
On Sat, 26 Jan 2019 07:48:50 -0600
"Gustavo A. R. Silva" wrote:
> Hey Boris,
>
> On 1/26/19 3:52 AM, Boris Brezillon wrote:
> > On Fri, 25 Jan 2019 15:09:50 -0600
> > "Gustavo A. R. Silva" wrote:
> >
> >> diff --git a/drivers/mtd/n
ot; are now the same type, and can be merged into a
> single variable.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Boris Brezillon
> ---
> v2:
> - Merge "off" and "offset" into a single variable instead of just
> killing the cast, as suggested
On Fri, 18 Jan 2019 15:05:25 +0100
Geert Uytterhoeven wrote:
> Reduce code duplication in at25_ee_read() by using the
> spi_message_init_with_transfers() helper.
>
> Signed-off-by: Geert Uytterhoeven
> Acked-by: Arnd Bergmann
Reviewed-by: Boris Brezillon
> ---
>
On Fri, 25 Jan 2019 15:09:50 -0600
"Gustavo A. R. Silva" wrote:
> diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
> index 933d1a629c51..d33e15dc4cdc 100644
> --- a/drivers/mtd/nand/raw/nandsim.c
> +++ b/drivers/mtd/nand/raw/nandsim.c
> @@ -2251,9 +2251,10 @@ static
On Wed, 23 Jan 2019 17:28:19 +0800
YueHaibing wrote:
> In case DOC_CHIPID_G3, mtd->name is not freed in err handling path,
> which is alloced by kasprintf(). Fix this by using devm_kasprintf().
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
> ---
On Wed, 23 Jan 2019 17:43:58 +0800
YueHaibing wrote:
> On 2019/1/23 17:12, Boris Brezillon wrote:
> > On Wed, 23 Jan 2019 14:58:27 +0800
> > YueHaibing wrote:
> >
> >> Fix a static code checker warning:
> >> drivers/mtd/devices/docg3.c:1875
>
On Wed, 23 Jan 2019 14:58:27 +0800
YueHaibing wrote:
> Fix a static code checker warning:
> drivers/mtd/devices/docg3.c:1875
> doc_probe_device() warn: passing zero to 'ERR_PTR'
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
> ---
>
On Wed, 23 Jan 2019 14:59:43 +0800
YueHaibing wrote:
> In case DOC_CHIPID_G3, mtd->name should be freed in the
> err handling path, which is alloced by kasprintf.
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
> ---
> drivers/mtd/devices/docg3.c
On Tue, 22 Jan 2019 12:11:37 +0530
Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current
-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_amd.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/nand_amd.c b/drivers/mtd/nand/raw/nand_amd.c
> index 6202cbf7ee8d..2ffcddff3
e safe side, let's check all three locations.
>
> Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_esmt.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/nand_esmt.c
>
we make it possible to set NAND_BBM_FIRSTPAGE,
> NAND_BBM_SECONDPAGE and NAND_BBM_LASTPAGE independently in any
> combination.
>
> To simplify the code, the logic to evaluate the flags is moved to a
> a new function nand_bbm_get_next_page().
>
> Signed-off-by: Frieder Schrempf
Reviewed-by
On Tue, 22 Jan 2019 11:23:29 +
Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> The information about where the manufacturer puts the bad block
> markers inside the bad block and in the OOB data is stored in
> different places. Let's move this information to nand_chip.options
> and
On Tue, 22 Jan 2019 09:00:14 +
Yogesh Narayan Gaur wrote:
> Hi Rob / Shawn,
>
> Can you please apply patches [1] [2].
No, DT bindings should go through Mark's tree. Just wait a bit please.
initialization for '(anonymous)[1].')
> > > error: unknown field 'data' specified in initializer
> > > error: unknown field 'addr' specified in initializer
> > >
> > > Work around the situation by naming these unions.
> > >
> > &
On Tue, 22 Jan 2019 00:57:43 +0900
Masahiro Yamada wrote:
>
> Maybe, is the following better?
Sounds good, even if the original commit message was fine too. I was
just pointing out that nand_scan() should, when possible, be passed
the real number of CS lines connected to the chip instead of
() should be checked as well. If it fails, probably
> id[0] and id[1] are undefined values.
>
> Just for consistency, it should be sensible to check the return
> code in nand_do_write_oob() as well.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
) is the number of bit shifts.
>
> The status/ret conversion in nand_erase_nand() is unneeded since
> commit eb94555e9e97 ("mtd: nand: use usual return values for the
> ->erase() hook"). Cleaned it up now.
Yeah! One less field in nand_legacy :-).
>
> Signed-off-by:
c_op conversion.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Boris Brezillon
> ---
>
> drivers/mtd/nand/raw/denali.c | 21 -
> 1 file changed, 21 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
> inde
On Tue, 2019-01-15 at 10:05:10 UTC, Yogesh Narayan Gaur wrote:
> - Add opcodes for octal I/O commands
> * Read : 1-1-8 and 1-8-8 protocol
> * Write : 1-1-8 and 1-8-8 protocol
> * opcodes for 4-byte address mode command
>
> - Entry of macros in _convert_3to4_xxx function
>
> - Add flag
On Wed, 2019-01-16 at 02:12:03 UTC, Ryder Lee wrote:
> This updates bindings for the MT7629 SPI-NOR controller.
>
> Signed-off-by: Ryder Lee
> Reviewed-by: Rob Herring
Applied to http://git.infradead.org/linux-mtd.git spi-nor/next, thanks.
Boris
On Wed, 2019-01-16 at 02:12:04 UTC, Ryder Lee wrote:
> From: Guochun Mao
>
> SNOR_HWCAPS_READ should be supported by this controller, so add this
> flag to spi_nor_hwcaps mask.
>
> Signed-off-by: Guochun Mao
> Signed-off-by: Ryder Lee
> Reviewed-by: Tudor Ambarus
Applied to
On Wed, 2019-01-16 at 02:12:05 UTC, Ryder Lee wrote:
> The quadspi is a generic communication interface which could be shared
> with other MediaTek SoCs. Hence rename it to a common one.
>
> Signed-off-by: Ryder Lee
> Reviewed-by: Tudor Ambarus
Applied to http://git.infradead.org/linux-mtd.git
On Tue, 2019-01-15 at 10:05:22 UTC, Yogesh Narayan Gaur wrote:
> Add support for octal mode I/O data transfer based on the controller (spi)
> mode.
> Assign hw-capability mask bits for octal transfer.
>
> Signed-off-by: Yogesh Narayan Gaur
> Reviewed-by: Tudor Ambarus
Applied to
On Tue, 2019-01-15 at 10:05:16 UTC, Yogesh Narayan Gaur wrote:
> Add octal read flag for flash mt35xu512aba.
> This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
> not seem to support newer JESD216C standard that provides auto
> detection of Octal mode capabilities and opcodes.
Hi Geert,
On Fri, 18 Jan 2019 15:05:23 +0100
Geert Uytterhoeven wrote:
> Hi all,
>
> This patch series contains two improvements for the AT25 SPI EEPROM
> driver, related to SPI transfers.
>
> Changes compared to v1:
> - Merge "off" and "offset" into a single variable instead of just
Hello Linus,
Here is the I3C fixes PR for 5.0-rc3.
Regards,
Boris
The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c:
Linux 5.0-rc1 (2019-01-06 17:08:20 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git
On Fri, 2019-01-18 at 05:30:38 UTC, Masahiro Yamada wrote:
> Commit 7a08dbaedd36 ("mtd: rawnand: Move ->setup_data_interface() to
> nand_controller_ops") missed to invert the if-conditonal for denali.
> Since then, the Denali NAND driver cannnot invoke setup_data_interface.
>
> Fixes:
On Thu, 17 Jan 2019 22:06:33 -0300
Paul Cercueil wrote:
> The jz4780-nand driver uses an API provided by the jz4780-bch driver.
> This makes it difficult to support other SoCs in the jz4780-bch driver.
> To work around this, we separate the API functions from the SoC-specific
> code, so that
On Thu, 17 Jan 2019 22:06:32 -0300
Paul Cercueil wrote:
> This should be done in devicetree. Besides, it prevents us from
> supporting other SoCs which don't use the same clock frequency for the
> BCH hardware.
As I said earlier, I disagree with this statement, plus, you're
breaking backward
On Thu, 17 Jan 2019 22:06:31 -0300
Paul Cercueil wrote:
> The boot ROM of the JZ4725B SoC expects a specific OOB layout on the
> NAND, so it makes sense to use this OOB layout unconditionally on this
> SoC.
>
> Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
>
On Thu, 17 Jan 2019 22:06:30 -0300
Paul Cercueil wrote:
> Add support for probing the jz4780-nand driver on the JZ4725B SoC from
> Ingenic.
>
> Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
BTW, if you have some time, maybe you could convert this driver
On Thu, 17 Jan 2019 22:06:29 -0300
Paul Cercueil wrote:
> Use SPDX license notifiers instead of GPLv2 license text in the headers.
>
> Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/jz4780_bch.c | 5 +
> drivers/mtd/nand/raw
On Thu, 17 Jan 2019 22:06:28 -0300
Paul Cercueil wrote:
> Add compatible strings to probe the jz4780-nand and jz4780-bch drivers
> from devicetree on the JZ4725B SoC from Ingenic.
>
> Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
> ---
> Documentation/devic
On Thu, 17 Jan 2019 19:45:50 -0300
Paul Cercueil wrote:
> Add support for the JZ4725B SoC from Ingenic.
>
> Signed-off-by: Paul Cercueil
I don't know anything about the JZ4725B constraints but the code looks
good, so
Reviewed-by: Boris Brezillon
> ---
> drivers/memory/jz4
On Thu, 17 Jan 2019 19:45:49 -0300
Paul Cercueil wrote:
> The maximum value found in that array is 15, there's no need to store
> these values as uint32_t, a uint8_t is enough.
Is it really worth the additional cast you add in the code?
>
> Signed-off-by: Paul Cercueil
> ---
>
On Thu, 17 Jan 2019 19:45:48 -0300
Paul Cercueil wrote:
> Depending on MACH_JZ4780 prevent us from creating a generic kernel that
> works on more than one MIPS board. Instead, we just depend on MIPS being
> set.
>
> Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
&
On Thu, 17 Jan 2019 19:45:47 -0300
Paul Cercueil wrote:
> Add a compatible string to support the memory controller built into the
> JZ4725B SoC from Ingenic.
>
> Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
> ---
> .../devicetree/bindings/memory-controll
Hi Paul,
On Thu, 17 Jan 2019 22:06:27 -0300
Paul Cercueil wrote:
> This is currently done inside the jz4780-bch driver, but it really
> should be done here instead.
>
I disagree with that statement. If it's a per-SoC constraint then you
can select the appropriate rate based on the compatible
On Fri, 18 Jan 2019 14:30:38 +0900
Masahiro Yamada wrote:
> Commit 7a08dbaedd36 ("mtd: rawnand: Move ->setup_data_interface() to
> nand_controller_ops") missed to invert the if-conditonal for denali.
> Since then, the Denali NAND driver cannnot invoke setup_data_interface.
>
> Fixes:
On Fri, 11 Jan 2019 14:29:28 +
Peter Rosin wrote:
> On 2019-01-10 20:25, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 18:51:21 +
> > Peter Rosin wrote:
> >
> >> On 2019-01-10 18:29, Boris Brezillon wrote:
> >>> On Thu, 10 Jan 20
From: Boris Brezillon
On Tue, 2019-01-15 at 16:57:52 UTC, wrote:
> From: Tudor Ambarus
>
> I have been reviewing and contributing to the SPI NOR subsystem
> for the last few months and I'm willing to continue doing so.
> Volunteer as a maintainer for the SPI NOR part of th
From: Boris Brezillon
On Tue, 2019-01-08 at 15:52:44 UTC, "Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elem
From: Boris Brezillon
On Tue, 2019-01-08 at 15:36:01 UTC, "Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elem
From: Boris Brezillon
On Tue, 2019-01-08 at 21:09:46 UTC, "Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding the
> size of a structure that has a zero-sized array at the end, along with memory
> for some number of elem
Hi Tudor,
On Tue, 15 Jan 2019 16:57:52 +
wrote:
> From: Tudor Ambarus
>
> I have been reviewing and contributing to the SPI NOR subsystem
> for the last few months and I'm willing to continue doing so.
> Volunteer as a maintainer for the SPI NOR part of the MTD subsystem.
I'll wait a bit
tmp_size -= 4, j++, buf += 4) {
>
> What about: for (j = 0; j < (wm_size / 4); j++, buf += 4) {
>
> > + tmp = fspi_readl(f, base + FSPI_RFDR + j * 4);
> > + memcpy(buf, , 4);
> > + }
> > + /* move the FIFO pointer */
> > + fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
> > + len -= wm_size;
> > + }
> > +
> > + size = len % wm_size;
> > + if (size) {
> > + /* Wait for RXFIFO available */
> > + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
> > + FSPI_INTR_IPRXWA, 0,
> > + POLL_TOUT, true);
> > + WARN_ON(ret);
> > +
> > + for (j = 0; len > 0; len -= size, j++, buf += size) {
> > + tmp = fspi_readl(f, base + FSPI_RFDR + j * 4);
> > + size = len < 4 ? len : 4;
>
> What about: size = min(len, 4);
>
> > + memcpy(buf, , size);
> > + }
> > + }
> > +
> > + /* invalid the RXFIFO */
> > + fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
> > + /* move the FIFO pointer */
> > + fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
> > + }
> > +}
>
Once you've addressed all of Frieder's comments you can add
Reviewed-by: Boris Brezillon
Regards,
Boris
On Thu, 10 Jan 2019 18:51:21 +
Peter Rosin wrote:
> On 2019-01-10 18:29, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 15:10:48 +
> > Peter Rosin wrote:
> >
> >> The A2Q and UPDATE bits have no effect in the channel disable registers.
> >>
On Thu, 10 Jan 2019 15:10:39 +
Peter Rosin wrote:
> The destination crtc rectangle is independent of source plane rotation.
>
> Signed-off-by: Peter Rosin
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git
On Thu, 10 Jan 2019 15:10:28 +
Peter Rosin wrote:
> Hi!
>
> I found an unfortunate issue while recoding plane handling to use
> drm_atomic_helper_check_plane_state(). The driver rotates clockwise,
> which is not correct. I simply fixed it (patch 1/4), but maybe that
> will cause regressions
On Thu, 10 Jan 2019 15:10:48 +
Peter Rosin wrote:
> The A2Q and UPDATE bits have no effect in the channel disable registers.
> However, since they are present, assume that the intention is to disable
> planes, not immediately as indicated by the RST bit, but on the next
> frame shift since
On Thu, 10 Jan 2019 09:16:12 -0800
Linus Torvalds wrote:
> On Thu, Jan 10, 2019 at 12:25 AM Boris Brezillon
> wrote:
> >
> > MTD Fixes:
> > - Fix a bug introduced when exposing MTD devs as NVMEM providers and
> > check for add_mtd_device() return code everywhe
On Wed, 9 Jan 2019 21:47:48 +0300
Sergei Shtylyov wrote:
> On 01/08/2019 07:16 AM, Mason Yang wrote:
>
> > Add a driver for Renesas R-Car Gen3 RPC-IF SPI controller.
> >
> > Signed-off-by: Mason Yang
>
>You now need to add:
>
> Signed-off-by: Sergei Shtylyov
May I ask why?
as NVMEM providers and
check for add_mtd_device() return code everywhere
raw NAND fixes:
- Fix a memory corruption in the QCOM driver
Boris Brezillon (2):
mtd: Fix the check on nvmem_register() ret code
mtd: Check
On Wed, 9 Jan 2019 11:37:19 +
Peter Rosin wrote:
> On 2019-01-09 11:12, Daniel Vetter wrote:
> > On Tue, Jan 08, 2019 at 12:31:36PM +, Peter Rosin wrote:
> >> While trying to temporarily hide a plane, one thing that was attempted
> >> was to call (from libdrm)
> >>
> >>
On Wed, 9 Jan 2019 11:12:24 +0100
Daniel Vetter wrote:
> On Tue, Jan 08, 2019 at 12:31:36PM +, Peter Rosin wrote:
> > While trying to temporarily hide a plane, one thing that was attempted
> > was to call (from libdrm)
> >
> > drmModeSetPlane(fd, plane_id, crtc_id, fb_id, 0,
> >
r.
>
> The new driver is already in use and this code is not compiled anymore,
> so let's remove it.
>
> Signed-off-by: Frieder Schrempf
> Acked-by: Han Xu
> Tested-by: Han Xu
Acked-by: Boris Brezillon
hrempf
> Acked-by: Han Xu
> Reviewed-by: Yogesh Gaur
> Tested-by: Yogesh Gaur
> Tested-by: Han Xu
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/spi-nor/Kconfig | 9 -
> drivers/mtd/spi-nor/Makefile | 1 -
> drivers/spi/Kconfig | 11 +
>
Hello Linus,
On Wed, 2 Jan 2019 11:53:34 -0800
Linus Torvalds wrote:
> Hmm..
>
> Adding a few more mtd people to the cc.
Sorry for the late reply, I don't have access to my @bootlin.com
address anymore and it took me some time to realize you had replied to
this bug report.
>
> On Tue, Jan
Hi Gustavo,
On Fri, 4 Jan 2019 11:26:37 -0600
"Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
Hi Frieder,
On Thu, 20 Dec 2018 14:35:05 +
Schrempf Frieder wrote:
> On 20.12.18 14:59, Boris Brezillon wrote:
> > On Mon, 17 Dec 2018 15:49:07 +
> > Schrempf Frieder wrote:
> >
> >> From: Frieder Schrempf
> >>
> >> Currently suppo
On Thu, 20 Dec 2018 14:59:54 +0100
Boris Brezillon wrote:
> >
> > /**
> > + * nand_bbm_page_offset - Get the page offsets for bad block markers
> > + * @chip: NAND chip object
> > + * @index: Index for the page offset
>
> Hm, the meaning of index is
On Mon, 17 Dec 2018 15:49:07 +
Schrempf Frieder wrote:
> From: Frieder Schrempf
>
> Currently supported bad block marker positions within the block are:
> * in first page only
> * in last page only
> * in first or second page
>
> Some ESMT NANDs are known to have been shipped by the
On Fri, 14 Dec 2018 10:58:08 +0100
Christophe Kerello wrote:
> This patch adds the polling mode, a basic mode that do not need
> any DMA channels. This mode is also useful for debug purpose.
>
> Signed-off-by: Christophe Kerello
Reviewed-by: Boris Brezillon
2> (Extended ECC
>based on Hamming)
>
> This patch has been tested on Micron MT29F8G08ABACAH4 and
> MT29F8G16ABACAH4
>
> Signed-off-by: Christophe Kerello
Reviewed-by: Boris Brezillon
On Fri, 14 Dec 2018 10:58:06 +0100
Christophe Kerello wrote:
> This patch adds the documentation of the device tree bindings for the STM32
> FMC2 NAND controller.
>
> Signed-off-by: Christophe Kerello
Reviewed-by: Boris Brezillon
> ---
> .../devicetree/bindings/mtd/s
regulator: Implement PM
> functionalities")
> Signed-off-by: Wei Yongjun
Reviewed-by: Boris Brezillon
> ---
> drivers/regulator/act8945a-regulator.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/regulator/act8945a-regulator.c
> b/dr
On Thu, 20 Dec 2018 08:23:07 +
Yogesh Narayan Gaur wrote:
> Octal mode support patch series has dependency over these patches.
> Should I send these two patches again or specifies them as dependency patches
> in the cover letter.
No, you should either base your work on the master branch of
td: spi-nor: Add support for mx25u12835f
Boris Brezillon (61):
mtd: maps: physmap: Add SPDX header
mtd: maps: physmap: Rename ->map and ->mtd into ->maps and ->mtds
mtd: maps: physmap: Use platform_get_resource() to retrieve iomem
resources
mtd: maps: physmap:
transfers in Cadence I3C master driver (2018-12-12
17:08:32 +0100)
Add initial support for I3C along with 2 I3C master controller drivers.
Boris Brezillon (7):
i3c: Add
On Mon, 2018-12-03 at 10:23:15 UTC, Boris Brezillon wrote:
> Use my korg address instead of the bootlin one.
>
> Signed-off-by: Boris Brezillon
Applied to http://git.infradead.org/linux-mtd.git mtd/next.
Boris
On Mon, 10 Dec 2018 17:15:29 +
wrote:
> From: Cyrille Pitchen
>
> This patch configures the QSPI0 controller pin muxing and declares
> a jedec,spi-nor memory.
>
> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> memory which advertises a maximum frequency of 80MHz for
On Fri, 7 Dec 2018 14:47:57 +0100
Paul Kocialkowski wrote:
> diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
> index f3fd34faa812..e80b1ad5c938 100644
> --- a/drivers/gpu/drm/vc4/vc4_kms.c
> +++ b/drivers/gpu/drm/vc4/vc4_kms.c
> @@ -479,6 +479,7 @@ static const
On Tue, 11 Dec 2018 09:56:25 +0800
Liang Yang wrote:
> Hi Miquel,
>
> On 2018/12/10 22:50, Miquel Raynal wrote:
> > Hi Liang,
> >
> > Liang Yang wrote on Mon, 10 Dec 2018 20:12:39
> > +0800:
> >
> >> On 2018/12/10 19:38, Boris Brezillon w
QSPI
> controller")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Arnd Bergmann
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>
On Mon, 10 Dec 2018 11:25:55 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:39 PM
> > To: Yogesh Narayan Gaur
> >
On Mon, 10 Dec 2018 19:23:46 +0800
Liang Yang wrote:
> >> + mtd->ecc_stats.failed++;
> >> + continue;
> >> + }
> >> + mtd->ecc_stats.corrected += ECC_ERR_CNT(*info);
> >> + bitflips = max_t(u32, bitflips, ECC_ERR_CNT(*info));
> >> + }
On Mon, 10 Dec 2018 16:49:29 +0530
Vignesh R wrote:
> On 10/12/18 2:15 PM, Boris Brezillon wrote:
> > On Wed, 3 Oct 2018 22:26:03 +0530
> > Vignesh R wrote:
> >
> >> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> >> It also has an int
On Mon, 10 Dec 2018 11:17:20 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:27 PM
> > To: Yogesh Narayan Gaur
> > Cc:
On Mon, 10 Dec 2018 10:59:54 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:20 PM
> > To: Yogesh Narayan Gaur
> >
On Mon, 10 Dec 2018 10:59:54 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, December 10, 2018 4:20 PM
> > To: Yogesh Narayan Gaur
> >
On Mon, 3 Dec 2018 08:39:18 +
Yogesh Narayan Gaur wrote:
> - Add opcodes for octal I/O commands
> * Read : 1-1-8 and 1-8-8 protocol
> * Write : 1-1-8 and 1-8-8 protocol
> * opcodes for 4-byte address mode command
>
> - Entry of macros in _convert_3to4_xxx function
>
> - Add flag
On Mon, 10 Dec 2018 10:43:56 +
Yogesh Narayan Gaur wrote:
> > > Thus, in LUT preparation we have assigned only the base address.
> > > Now if I have assigned ahb_buf_size to FSPI_FLSHXXCR0 register then for
> > read/write data beyond limit of ahb_buf_size offset I get data corruption.
> >
On Mon, 10 Dec 2018 10:35:35 +
Schrempf Frieder wrote:
> >>> +
> >>> +static int nxp_fspi_exec_op(struct spi_mem *mem, const struct
> >>> +spi_mem_op *op) {
> >>> + struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master);
> >>> + int err = 0;
> >>> +
> >>> + mutex_lock(>lock);
>
On Mon, 10 Dec 2018 10:31:57 +
Schrempf Frieder wrote:
> >> Yes, I need to validate op->addr.nbytes else LUT would going to be
> >> programmed for 0 addrlen.
> >> I have checked this on the target.
> >
> > Also agree there. Some operations have 0 address bytes. We could also
> > test
401 - 500 of 10969 matches
Mail list logo
