On Mon, Nov 12, 2018 at 11:56:58AM +, Julien Thierry wrote:
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 039144e..eb8120e 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -249,6 +249,12 @@ alternative_else_nop_endif
> msr
On Mon, Nov 12, 2018 at 11:56:56AM +, Julien Thierry wrote:
> Mask the IRQ priority through PMR and re-enable IRQs at CPU level,
> allowing only higher priority interrupts to be received during interrupt
> handling.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
On Mon, Nov 12, 2018 at 11:56:56AM +, Julien Thierry wrote:
> Mask the IRQ priority through PMR and re-enable IRQs at CPU level,
> allowing only higher priority interrupts to be received during interrupt
> handling.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
to enable syscall events on arm64
- Fix uninitialised pointer in iort_get_platform_device_domain()
Catalin Marinas (1):
arm64: Add workaround for Cortex-A76 erratum 1286807
Lorenzo Pieralisi (1):
ACPI/IORT: Fix
to enable syscall events on arm64
- Fix uninitialised pointer in iort_get_platform_device_domain()
Catalin Marinas (1):
arm64: Add workaround for Cortex-A76 erratum 1286807
Lorenzo Pieralisi (1):
ACPI/IORT: Fix
On Mon, Nov 12, 2018 at 11:56:55AM +, Julien Thierry wrote:
> Add helper functions to access system registers related to interrupt
> priorities: PMR and RPR.
>
> Signed-off-by: Julien Thierry
> Cc: Russell King
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Marc Zyn
On Mon, Nov 12, 2018 at 11:56:55AM +, Julien Thierry wrote:
> Add helper functions to access system registers related to interrupt
> priorities: PMR and RPR.
>
> Signed-off-by: Julien Thierry
> Cc: Russell King
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Marc Zyn
On Mon, Nov 12, 2018 at 11:56:54AM +, Julien Thierry wrote:
> Add a cpufeature indicating whether a cpu supports masking interrupts
> by priority.
>
> The feature will be properly enabled in a later patch.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc:
On Mon, Nov 12, 2018 at 11:56:54AM +, Julien Thierry wrote:
> Add a cpufeature indicating whether a cpu supports masking interrupts
> by priority.
>
> The feature will be properly enabled in a later patch.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc:
ICC_SRE_EL1.SRE, it cannot be
> turned off if found on a CPU.
>
> Set the feature as STRICT_BOOT, if boot CPU has it, all other CPUs are
> required to have it.
>
> Signed-off-by: Julien Thierry
> Suggested-by: Daniel Thompson
> Cc: Catalin Marinas
> Cc: Will Deacon
ICC_SRE_EL1.SRE, it cannot be
> turned off if found on a CPU.
>
> Set the feature as STRICT_BOOT, if boot CPU has it, all other CPUs are
> required to have it.
>
> Signed-off-by: Julien Thierry
> Suggested-by: Daniel Thompson
> Cc: Catalin Marinas
> Cc: Will Deacon
Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: James Morse
Acked-by: Catalin Marinas
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify
Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: James Morse
Acked-by: Catalin Marinas
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify
addr != end)
> [3] while (pudp++, addr = next, addr != end && pud_none(READ_ONCE(*pudp)))
> [4] while (pmdp++, addr = next, addr != end && pmd_none(READ_ONCE(*pmdp)))
> [5] while (ptep++, addr = next, addr != end && pte_none(READ_ONCE(*ptep)))
>
> Signed-off-by: Qian Cai
Acked-by: Catalin Marinas
(for both the kmemleak and arm64 changes)
addr != end)
> [3] while (pudp++, addr = next, addr != end && pud_none(READ_ONCE(*pudp)))
> [4] while (pmdp++, addr = next, addr != end && pmd_none(READ_ONCE(*pmdp)))
> [5] while (ptep++, addr = next, addr != end && pte_none(READ_ONCE(*ptep)))
>
> Signed-off-by: Qian Cai
Acked-by: Catalin Marinas
(for both the kmemleak and arm64 changes)
On Thu, Nov 29, 2018 at 02:39:33PM +0900, Masami Hiramatsu wrote:
> Since commit 4378a7d4be30 ("arm64: implement syscall wrappers")
> introduced "__arm64_" prefix to all syscall wrapper symbols in
> sys_call_table, syscall tracer can not find corresponding
> metadata from syscall name. In the
On Thu, Nov 29, 2018 at 02:39:33PM +0900, Masami Hiramatsu wrote:
> Since commit 4378a7d4be30 ("arm64: implement syscall wrappers")
> introduced "__arm64_" prefix to all syscall wrapper symbols in
> sys_call_table, syscall tracer can not find corresponding
> metadata from syscall name. In the
On Wed, Nov 28, 2018 at 12:40:33PM -0500, Qian Cai wrote:
> Kmemleak does not play well with KASAN (tested on both HPE Apollo 70 and
> Huawei TaiShan 2280 aarch64 servers).
>
> After calling start_kernel()->setup_arch()->kasan_init(), kmemleak early
> log buffer went from something like 280 to
On Wed, Nov 28, 2018 at 12:40:33PM -0500, Qian Cai wrote:
> Kmemleak does not play well with KASAN (tested on both HPE Apollo 70 and
> Huawei TaiShan 2280 aarch64 servers).
>
> After calling start_kernel()->setup_arch()->kasan_init(), kmemleak early
> log buffer went from something like 280 to
_cache_create() to not register a
> newly allocated debug objects at all.
>
> Suggested-by: Catalin Marinas
> Signed-off-by: Qian Cai
Acked-by: Catalin Marinas
_cache_create() to not register a
> newly allocated debug objects at all.
>
> Suggested-by: Catalin Marinas
> Signed-off-by: Qian Cai
Acked-by: Catalin Marinas
On Mon, Nov 26, 2018 at 04:45:54AM -0500, Qian Cai wrote:
> On 11/25/18 11:52 PM, Qian Cai wrote:
> > BTW, calling debug_objects_mem_init() before kmemleak_init() actually
> > could trigger a loop on machines with 160+ CPUs until the pool is filled
> > up,
> >
> > debug_objects_pool_min_level +=
On Mon, Nov 26, 2018 at 04:45:54AM -0500, Qian Cai wrote:
> On 11/25/18 11:52 PM, Qian Cai wrote:
> > BTW, calling debug_objects_mem_init() before kmemleak_init() actually
> > could trigger a loop on machines with 160+ CPUs until the pool is filled
> > up,
> >
> > debug_objects_pool_min_level +=
Hi Linus,
Please pull the arm64 fixes below. Thanks.
The following changes since commit 9ff01193a20d391e8dbce4403dd5ef87c7eaaca6:
Linux 4.20-rc3 (2018-11-18 13:33:44 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes
Hi Linus,
Please pull the arm64 fixes below. Thanks.
The following changes since commit 9ff01193a20d391e8dbce4403dd5ef87c7eaaca6:
Linux 4.20-rc3 (2018-11-18 13:33:44 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes
2M32M 1G
> 16K:2M 32M 1G
> 64K:2M512M16G
>
> Reviewed-by: Naoya Horiguchi
> Signed-off-by: Anshuman Khandual
Acked-by: Catalin Marinas
2M32M 1G
> 16K:2M 32M 1G
> 64K:2M512M16G
>
> Reviewed-by: Naoya Horiguchi
> Signed-off-by: Anshuman Khandual
Acked-by: Catalin Marinas
CONT PTEPMDCONT PMDPUD
>------
> 4K: NA 2M NA 1G
> 16K:NA32M NA
> 64K:NA 512M NA
>
> Reviewed-by: Naoya Horiguchi
> Signed-off-by: Anshuman Khandual
Acked-by: Catalin Marinas
CONT PTEPMDCONT PMDPUD
>------
> 4K: NA 2M NA 1G
> 16K:NA32M NA
> 64K:NA 512M NA
>
> Reviewed-by: Naoya Horiguchi
> Signed-off-by: Anshuman Khandual
Acked-by: Catalin Marinas
On Fri, Nov 23, 2018 at 12:06:11PM +0100, Sebastian Andrzej Siewior wrote:
> On 2018-11-23 12:02:55 [+0100], Andrea Parri wrote:
> > > is this an RT-only problem? Because mainline should not allow read->read
> > > locking or read->write locking for reader-writer locks. If this only
> > > happens
On Fri, Nov 23, 2018 at 12:06:11PM +0100, Sebastian Andrzej Siewior wrote:
> On 2018-11-23 12:02:55 [+0100], Andrea Parri wrote:
> > > is this an RT-only problem? Because mainline should not allow read->read
> > > locking or read->write locking for reader-writer locks. If this only
> > > happens
On Sat, Nov 10, 2018 at 10:08:10AM -0500, Qian Cai wrote:
> On Nov 8, 2018, at 4:23 PM, Qian Cai wrote:
> > The maximum value for DEBUG_KMEMLEAK_EARLY_LOG_SIZE is only 4, so it
> > disables kmemleak every time on this aarch64 server running the latest
> > mainline
> > (b00d209).
> >
> > #
On Sat, Nov 10, 2018 at 10:08:10AM -0500, Qian Cai wrote:
> On Nov 8, 2018, at 4:23 PM, Qian Cai wrote:
> > The maximum value for DEBUG_KMEMLEAK_EARLY_LOG_SIZE is only 4, so it
> > disables kmemleak every time on this aarch64 server running the latest
> > mainline
> > (b00d209).
> >
> > #
Hi Linus,
Please pull the arm64 fixes below. Thanks.
The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes
Hi Linus,
Please pull the arm64 fixes below. Thanks.
The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-fixes
nstead of
> set and checked with a build bug. This also allows us to use the same
> define for riscv.
>
> Signed-off-by: Logan Gunthorpe
> Acked-by: Will Deacon
> Acked-by: Andrew Morton
> Cc: Catalin Marinas
> Cc: Arnd Bergmann
> Cc: Christoph Hellwig
Acked-by: Catalin Marinas
nstead of
> set and checked with a build bug. This also allows us to use the same
> define for riscv.
>
> Signed-off-by: Logan Gunthorpe
> Acked-by: Will Deacon
> Acked-by: Andrew Morton
> Cc: Catalin Marinas
> Cc: Arnd Bergmann
> Cc: Christoph Hellwig
Acked-by: Catalin Marinas
On Wed, Nov 07, 2018 at 11:39:11PM +0800, Peng Hao wrote:
> Use git commit description style 'commit <12+ chars of sha1>
> ("")' in the comments.
>
> Signed-off-by: Peng Hao
> ---
> arch/arm64/kernel/sys32.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Wed, Nov 07, 2018 at 11:39:11PM +0800, Peng Hao wrote:
> Use git commit description style 'commit <12+ chars of sha1>
> ("")' in the comments.
>
> Signed-off-by: Peng Hao
> ---
> arch/arm64/kernel/sys32.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
On Tue, Nov 06, 2018 at 09:16:04AM +0100, Ard Biesheuvel wrote:
> (+ Catalin, Will)
>
> On 6 November 2018 at 01:14, Jeremy Linton wrote:
> > The lib/raid6/test fails to build the neon objects
> > on arm64 because the correct machine type is 'aarch64'.
> >
> > Once this is correctly enabled, the
On Tue, Nov 06, 2018 at 09:16:04AM +0100, Ard Biesheuvel wrote:
> (+ Catalin, Will)
>
> On 6 November 2018 at 01:14, Jeremy Linton wrote:
> > The lib/raid6/test fails to build the neon objects
> > on arm64 because the correct machine type is 'aarch64'.
> >
> > Once this is correctly enabled, the
On Fri, Nov 02, 2018 at 04:57:52PM +, Punit Agrawal wrote:
> As I'll no longer be working with Arm, add a mailmap entry so any mail
> directed towards me reaches the appropriate mailbox.
>
> Signed-off-by: Punit Agrawal
I'll pick this up for 4.20-rc2 (unless Linus applies it directly).
On Fri, Nov 02, 2018 at 04:57:52PM +, Punit Agrawal wrote:
> As I'll no longer be working with Arm, add a mailmap entry so any mail
> directed towards me reaches the appropriate mailbox.
>
> Signed-off-by: Punit Agrawal
I'll pick this up for 4.20-rc2 (unless Linus applies it directly).
Hi Linus,
Please pull the arm64 updates below. Thank you.
The following changes since commit 4debef5510071032c6d5dace31ca1cc42a120073:
arm64: KVM: Guests can skip __install_bp_hardening_cb()s HYP work (2018-10-19
15:37:25 +0100)
are available in the git repository at:
Hi Linus,
Please pull the arm64 updates below. Thank you.
The following changes since commit 4debef5510071032c6d5dace31ca1cc42a120073:
arm64: KVM: Guests can skip __install_bp_hardening_cb()s HYP work (2018-10-19
15:37:25 +0100)
are available in the git repository at:
On Fri, Nov 02, 2018 at 04:26:07PM +0100, Arnd Bergmann wrote:
> After a good chunk of the swiotlb code has been replaced with the generic
> version, two functions are only used from inside of an #ifdef:
>
> arch/arm64/mm/dma-mapping.c:174:12: error: '__swiotlb_mmap_pfn' defined but
> not used
On Fri, Nov 02, 2018 at 04:26:07PM +0100, Arnd Bergmann wrote:
> After a good chunk of the swiotlb code has been replaced with the generic
> version, two functions are only used from inside of an #ifdef:
>
> arch/arm64/mm/dma-mapping.c:174:12: error: '__swiotlb_mmap_pfn' defined but
> not used
d+0x12c/0x238
> >> [3.253417] ptdump_check_wx+0x68/0xf8
> >> [3.253637] mark_rodata_ro+0x68/0x98
> >> [3.253847] kernel_init+0x38/0x160
> >> [3.254103] ret_from_fork+0x10/0x18
> >>
> >> kprobes allocates a writable executa
d+0x12c/0x238
> >> [3.253417] ptdump_check_wx+0x68/0xf8
> >> [3.253637] mark_rodata_ro+0x68/0x98
> >> [3.253847] kernel_init+0x38/0x160
> >> [3.254103] ret_from_fork+0x10/0x18
> >>
> >> kprobes allocates a writable executa
0
> [3.254103] ret_from_fork+0x10/0x18
>
> kprobes allocates a writable executable page with module_alloc() in
> order to store executable code.
> Reworked to that when allocate a page it sets mode RO. Inspired by
> commit 63fef14fc98a ("kprobes/x86: Make insn buffer alw
0
> [3.254103] ret_from_fork+0x10/0x18
>
> kprobes allocates a writable executable page with module_alloc() in
> order to store executable code.
> Reworked to that when allocate a page it sets mode RO. Inspired by
> commit 63fef14fc98a ("kprobes/x86: Make insn buffer alw
On Fri, Nov 02, 2018 at 08:36:19AM -0400, Yangtao Li wrote:
> This brings the kernel doc in line with the function signature.
>
> Signed-off-by: Yangtao Li
Queued for 4.20. Thanks.
--
Catalin
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be
On Fri, Nov 02, 2018 at 08:36:19AM -0400, Yangtao Li wrote:
> This brings the kernel doc in line with the function signature.
>
> Signed-off-by: Yangtao Li
Queued for 4.20. Thanks.
--
Catalin
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be
protect first_run with DEBUG_KMEMLEAK_AUTO_SCAN as this is meant
> for only first automatic scan.
>
> Signed-off-by: Sri Krishna chowdary
> Signed-off-by: Sachin Nikam
> Signed-off-by: Prateek
Looks fine to me.
Reviewed-by: Catalin Marinas
protect first_run with DEBUG_KMEMLEAK_AUTO_SCAN as this is meant
> for only first automatic scan.
>
> Signed-off-by: Sri Krishna chowdary
> Signed-off-by: Sachin Nikam
> Signed-off-by: Prateek
Looks fine to me.
Reviewed-by: Catalin Marinas
Hi Linus, Greg,
I'm sending the pull request for 4.20 slightly earlier as I'm on holiday
next week (not in Edinburgh). Apart from some new arm64 features and
clean-ups, this request also contains the core mmu_gather changes for
tracking the levels of the page table being cleared and a minor
Hi Linus, Greg,
I'm sending the pull request for 4.20 slightly earlier as I'm on holiday
next week (not in Edinburgh). Apart from some new arm64 features and
clean-ups, this request also contains the core mmu_gather changes for
tracking the levels of the page table being cleared and a minor
On Fri, Oct 05, 2018 at 09:47:49AM +0100, Kristina Martsenko wrote:
> From: Mark Rutland
>
> To use pointer authentication in the kernel, we'll need to switch keys
> in the entry assembly. This patch moves the pointer auth keys into
> thread_info to make this possible.
>
> There should be no
On Fri, Oct 05, 2018 at 09:47:49AM +0100, Kristina Martsenko wrote:
> From: Mark Rutland
>
> To use pointer authentication in the kernel, we'll need to switch keys
> in the entry assembly. This patch moves the pointer auth keys into
> thread_info to make this possible.
>
> There should be no
On Wed, Oct 17, 2018 at 01:33:28PM +0530, Prateek Patel wrote:
> diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> index e5e7c03..9542852 100644
> --- a/lib/Kconfig.debug
> +++ b/lib/Kconfig.debug
> @@ -593,6 +593,17 @@ config DEBUG_KMEMLEAK_DEFAULT_OFF
> Say Y here to disable kmemleak
On Wed, Oct 17, 2018 at 01:33:28PM +0530, Prateek Patel wrote:
> diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> index e5e7c03..9542852 100644
> --- a/lib/Kconfig.debug
> +++ b/lib/Kconfig.debug
> @@ -593,6 +593,17 @@ config DEBUG_KMEMLEAK_DEFAULT_OFF
> Say Y here to disable kmemleak
On Tue, Oct 09, 2018 at 02:47:03PM +0100, Suzuki K. Poulose wrote:
> This series makes sure that we handle the CTR_EL0 field mismatches
> properly, especially for the IDC field. Also, skip trapping CTR
> accesses on a CPU if it matches the safe value.
>
> Applies on arm64 for-next/core.
>
>
On Tue, Oct 09, 2018 at 02:47:03PM +0100, Suzuki K. Poulose wrote:
> This series makes sure that we handle the CTR_EL0 field mismatches
> properly, especially for the IDC field. Also, skip trapping CTR
> accesses on a CPU if it matches the safe value.
>
> Applies on arm64 for-next/core.
>
>
(dev, size, vaddr, dma_handle, attrs);
> + if (!__free_from_pool(vaddr, PAGE_ALIGN(size)))
> + void *kaddr = phys_to_virt(dma_to_phys(dev, dma_handle));
> +
> + vunmap(vaddr);
> + dma_direct_free_pages(dev, size, kaddr, dma_handle, attrs);
> + }
> }
>
> long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
With this fix:
Acked-by: Catalin Marinas
(dev, size, vaddr, dma_handle, attrs);
> + if (!__free_from_pool(vaddr, PAGE_ALIGN(size)))
> + void *kaddr = phys_to_virt(dma_to_phys(dev, dma_handle));
> +
> + vunmap(vaddr);
> + dma_direct_free_pages(dev, size, kaddr, dma_handle, attrs);
> + }
> }
>
> long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
With this fix:
Acked-by: Catalin Marinas
t; arch/arm64/mm/init.c | 20 +---
> 1 file changed, 1 insertion(+), 19 deletions(-)
Acked-by: Catalin Marinas
t; arch/arm64/mm/init.c | 20 +---
> 1 file changed, 1 insertion(+), 19 deletions(-)
Acked-by: Catalin Marinas
Stefano Stabellini
> Cc: Catalin Marinas
> Cc: Will Deacon
Queued for 4.20. Thanks.
--
Catalin
Stefano Stabellini
> Cc: Catalin Marinas
> Cc: Will Deacon
Queued for 4.20. Thanks.
--
Catalin
ions, daifflags should be properly restored
> to a state where IRQs are enabled.
>
> Enable IRQs by restoring DAIF_PROCCTX state after bp hardening.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Mark Rutland
> Cc: James Morse
Queued for 4.20. Thanks.
--
Catalin
ions, daifflags should be properly restored
> to a state where IRQs are enabled.
>
> Enable IRQs by restoring DAIF_PROCCTX state after bp hardening.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Mark Rutland
> Cc: James Morse
Queued for 4.20. Thanks.
--
Catalin
gt; irqflags should alter the behaviour of daifflags.
>
> Use irqflags_save/restore functions for the corresponding daifflags
> operation.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: James Morse
Queued for 4.20. Thanks.
--
Catalin
gt; irqflags should alter the behaviour of daifflags.
>
> Use irqflags_save/restore functions for the corresponding daifflags
> operation.
>
> Signed-off-by: Julien Thierry
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: James Morse
Queued for 4.20. Thanks.
--
Catalin
On Tue, Oct 02, 2018 at 11:11:44PM +0200, Arnd Bergmann wrote:
> arm64_1188873_read_cntvct_el0() is protected by the correct
> CONFIG_ARM64_ERRATUM_1188873 #ifdef, but the only reference to it is
> also inside of an CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND section,
> and causes a warning if that is
On Tue, Oct 02, 2018 at 11:11:44PM +0200, Arnd Bergmann wrote:
> arm64_1188873_read_cntvct_el0() is protected by the correct
> CONFIG_ARM64_ERRATUM_1188873 #ifdef, but the only reference to it is
> also inside of an CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND section,
> and causes a warning if that is
On Fri, 21 Sep 2018 at 13:22, Peter Zijlstra wrote:
> On Fri, Sep 21, 2018 at 02:02:26PM +0200, Sebastian Andrzej Siewior wrote:
> > We reproducibly observe cache line starvation on a Core2Duo E6850 (2
> > cores), a i5-6400 SKL (4 cores) and on a NXP LS2044A ARM Cortex-A72 (4
> > cores).
> >
> >
On Fri, 21 Sep 2018 at 13:22, Peter Zijlstra wrote:
> On Fri, Sep 21, 2018 at 02:02:26PM +0200, Sebastian Andrzej Siewior wrote:
> > We reproducibly observe cache line starvation on a Core2Duo E6850 (2
> > cores), a i5-6400 SKL (4 cores) and on a NXP LS2044A ARM Cortex-A72 (4
> > cores).
> >
> >
On Mon, Oct 01, 2018 at 01:44:52PM -0700, Mark Salyzyn wrote:
> On 10/01/2018 11:49 AM, John Stultz wrote:
> > On Mon, Oct 1, 2018 at 10:58 AM, Mark Salyzyn wrote:
> > > Last sent 23 Nov 2016.
> > >
> > > The following 23 patches are rebased and resent, and represent a
> > > rewrite of the arm
On Mon, Oct 01, 2018 at 01:44:52PM -0700, Mark Salyzyn wrote:
> On 10/01/2018 11:49 AM, John Stultz wrote:
> > On Mon, Oct 1, 2018 at 10:58 AM, Mark Salyzyn wrote:
> > > Last sent 23 Nov 2016.
> > >
> > > The following 23 patches are rebased and resent, and represent a
> > > rewrite of the arm
On Mon, Sep 03, 2018 at 05:59:35PM +0100, Will Deacon wrote:
> On Thu, Aug 09, 2018 at 10:20:39PM +0800, zhong jiang wrote:
> > There are some extra semicolon in arm64 architecture. Just remove them.
>
> These are trivial but certainly not urgent, so I guess Catalin can pick
> them up for 4.20.
>
On Mon, Sep 03, 2018 at 05:59:35PM +0100, Will Deacon wrote:
> On Thu, Aug 09, 2018 at 10:20:39PM +0800, zhong jiang wrote:
> > There are some extra semicolon in arm64 architecture. Just remove them.
>
> These are trivial but certainly not urgent, so I guess Catalin can pick
> them up for 4.20.
>
On Fri, Sep 28, 2018 at 02:18:11PM +0100, Steve McIntyre wrote:
> On Wed, Sep 05, 2018 at 03:34:41PM +0100, Will Deacon wrote:
> >Hi all,
> >
> >This is a resend of:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2018-July/593559.html
> >
> >now based on 4.19-rc2.
> >
> >The Debian
On Fri, Sep 28, 2018 at 02:18:11PM +0100, Steve McIntyre wrote:
> On Wed, Sep 05, 2018 at 03:34:41PM +0100, Will Deacon wrote:
> >Hi all,
> >
> >This is a resend of:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2018-July/593559.html
> >
> >now based on 4.19-rc2.
> >
> >The Debian
On Fri, Sep 28, 2018 at 01:49:29PM +1000, Stephen Rothwell wrote:
> diff --cc arch/arm64/kernel/traps.c
> index 21689c6a985f,856b32aa03d8..
> --- a/arch/arm64/kernel/traps.c
> +++ b/arch/arm64/kernel/traps.c
> @@@ -353,12 -366,6 +368,9 @@@ void force_signal_inject(int signal, in
>
On Fri, Sep 28, 2018 at 01:49:29PM +1000, Stephen Rothwell wrote:
> diff --cc arch/arm64/kernel/traps.c
> index 21689c6a985f,856b32aa03d8..
> --- a/arch/arm64/kernel/traps.c
> +++ b/arch/arm64/kernel/traps.c
> @@@ -353,12 -366,6 +368,9 @@@ void force_signal_inject(int signal, in
>
On Thu, Sep 27, 2018 at 11:39:35AM +0200, Eric W. Biederman wrote:
> Catalin Marinas writes:
> > On Mon, Sep 24, 2018 at 11:07:05AM +0200, Eric W. Biederman wrote:
> >> After these patches have had a chance to be reviewed I plan to merge
> >> them by my siginfo tree
On Thu, Sep 27, 2018 at 11:39:35AM +0200, Eric W. Biederman wrote:
> Catalin Marinas writes:
> > On Mon, Sep 24, 2018 at 11:07:05AM +0200, Eric W. Biederman wrote:
> >> After these patches have had a chance to be reviewed I plan to merge
> >> them by my siginfo tree
Hi Eric,
On Mon, Sep 24, 2018 at 11:07:05AM +0200, Eric W. Biederman wrote:
> This is the continuation of my work to sort out signaling of exceptions
> with siginfo. The old signal sending functions by taking a siginfo
> argument resulted in their callers having to deal with the fiddly nature
>
Hi Eric,
On Mon, Sep 24, 2018 at 11:07:05AM +0200, Eric W. Biederman wrote:
> This is the continuation of my work to sort out signaling of exceptions
> with siginfo. The old signal sending functions by taking a siginfo
> argument resulted in their callers having to deal with the fiddly nature
>
On Tue, Sep 25, 2018 at 03:06:25PM +0100, Mark Rutland wrote:
> On Tue, Sep 25, 2018 at 05:53:16PM +0800, Jun Yao wrote:
> > On Mon, Sep 24, 2018 at 06:19:36PM +0100, Mark Rutland wrote:
> > > I've pushed a branch with the cleanups I requested [1] folded in.
> > >
> > > I'm still a bit worried
On Tue, Sep 25, 2018 at 03:06:25PM +0100, Mark Rutland wrote:
> On Tue, Sep 25, 2018 at 05:53:16PM +0800, Jun Yao wrote:
> > On Mon, Sep 24, 2018 at 06:19:36PM +0100, Mark Rutland wrote:
> > > I've pushed a branch with the cleanups I requested [1] folded in.
> > >
> > > I'm still a bit worried
On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote:
> To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
> It seems we don't need 4 bits for the memory type with ARMv6+.
> If it's true, let's reorder bits to make bit 5 free.
>
> We will use the bit for L_PTE_SPECIAL in
On Mon, Sep 17, 2018 at 09:44:49AM +0900, Minchan Kim wrote:
> To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
> It seems we don't need 4 bits for the memory type with ARMv6+.
> If it's true, let's reorder bits to make bit 5 free.
>
> We will use the bit for L_PTE_SPECIAL in
Hi Stephen,
On Mon, Sep 24, 2018 at 02:38:53PM +1000, Stephen Rothwell wrote:
> diff --cc arch/arm64/Kconfig
> index da5e6f085561,f8a618a292f4..
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@@ -785,7 -786,8 +785,8 @@@ config ARCH_FLATMEM_ENABL
> def_bool !NUMA
>
>
Hi Stephen,
On Mon, Sep 24, 2018 at 02:38:53PM +1000, Stephen Rothwell wrote:
> diff --cc arch/arm64/Kconfig
> index da5e6f085561,f8a618a292f4..
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@@ -785,7 -786,8 +785,8 @@@ config ARCH_FLATMEM_ENABL
> def_bool !NUMA
>
>
On Thu, Sep 20, 2018 at 06:25:29PM +0100, Catalin Marinas wrote:
> On Wed, Jun 06, 2018 at 12:31:21PM +0530, Chintan Pandya wrote:
> > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> > index 8ae5d7a..65f8627 100644
> > --- a/arch/arm64/mm/mmu.c
> > +++ b/arch/
On Thu, Sep 20, 2018 at 06:25:29PM +0100, Catalin Marinas wrote:
> On Wed, Jun 06, 2018 at 12:31:21PM +0530, Chintan Pandya wrote:
> > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> > index 8ae5d7a..65f8627 100644
> > --- a/arch/arm64/mm/mmu.c
> > +++ b/arch/
Hi Chintan,
On Wed, Jun 06, 2018 at 12:31:21PM +0530, Chintan Pandya wrote:
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index 8ae5d7a..65f8627 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -45,6 +45,7 @@
> #include
> #include
> #include
> +#include
>
Hi Chintan,
On Wed, Jun 06, 2018 at 12:31:21PM +0530, Chintan Pandya wrote:
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index 8ae5d7a..65f8627 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -45,6 +45,7 @@
> #include
> #include
> #include
> +#include
>
On Thu, Sep 06, 2018 at 07:22:10PM +0900, Minchan Kim wrote:
> diff --git a/arch/arm/include/asm/pgtable-2level.h
> b/arch/arm/include/asm/pgtable-2level.h
> index 92fd2c8a9af0..91b99fadcba1 100644
> --- a/arch/arm/include/asm/pgtable-2level.h
> +++ b/arch/arm/include/asm/pgtable-2level.h
> @@
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