[tip: x86/cpu] x86/kvm: Expose TSX Suspend Load Tracking feature

The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 61aa9a0a5eae2100c171698bffabde8d5e9f694d Gitweb: https://git.kernel.org/tip/61aa9a0a5eae2100c171698bffabde8d5e9f694d Author:Cathy Zhang AuthorDate:Tue, 25 Aug 2020 08:47:58 +08:00 Committer

[PATCH v4 0/2] Expose new feature for Intel processor

definition from TSX_LDTRK to TSXLDTRK for TSX new feature. * Change kernel patches Author to the owner. * Remove SERIALIZE enumeration patch. Reference: [1]. https://software.intel.com/content/dam/develop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf C

[PATCH v4 2/2] x86/kvm: Expose TSX Suspend Load Tracking feature

feature in KVM CPUID, so KVM could pass this information to guests and they can make use of this feature accordingly. Signed-off-by: Cathy Zhang Reviewed-by: Tony Luck --- Changes since v3: * Remove SERIALIZE part and refactor commit message.. Changes since v2: * Merge two patches

[PATCH v4 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Kyung Min Park Signed-off-by: Cathy Zhang Reviewed-by: Tony Luck --- Changes since v3: * N/A Changes since v2: * Shorten documentation names for readability. Links to documentation can be found in the cover lette

[PATCH v3 0/2] Expose new features for Intel processor

lop/public/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf Cathy Zhang (1): x86/kvm: Expose new features for supported cpuid Kyung Min Park (1): x86/cpufeatures: Enumerate TSX suspend load address tracking instructions arch/x86/include/asm/cpufeat

[PATCH v3 2/2] x86/kvm: Expose new features for supported cpuid

as CPUID.(EAX=7,ECX=0):EDX[bit 16]. Those instructions are currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Cathy Zhang Reviewed-by: Tony Luck --- Changes since v2: * Merge two patches into

[PATCH v3 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Kyung Min Park Signed-off-by: Cathy Zhang Reviewed-by: Tony Luck --- Changes since v2: * Shorten documentation names for readability. Links to documentation can be found in the cover letter. (Dave Hansen) --- arch

[PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking

TSX Suspend Load Address Tracking is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid. Signed-off-by: Cathy Zhang --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index

[PATCH v2 0/4] Expose new features for intel processor

to choose which memory accesses do not need to be tracked in the TSX read set. Changelog: v2 Add kernel feature enumeration patch to fix build error Cathy Zhang (2): x86: Expose SERIALIZE for supported cpuid x86: Expose TSX Suspend Load Address Tracking Ricardo Neri (1): x86/cpufeatures

[PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction

structions and CPUID feature flag SERIALIZE can be found in the latest Intel Architecture Instruction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual. Signed-off-by: Ricardo Neri Signed-off-by: Cathy Zhang --- arch/x86/i

[PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

uction Set Extensions and Future Features Programming Reference and Intel 64 and IA-32 Architectures Software Developer's Manual. Signed-off-by: Kyung Min Park Signed-off-by: Cathy Zhang --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/i

[PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid. Signed-off-by: Cathy Zhang --- arch/x86/kvm/cpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 8a294f9

[PATCH 1/2] x86: Expose SERIALIZE for supported cpuid

SERIALIZE instruction is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid. The SERIALIZE enumeration kernel patch link is as follows: https://lore.kernel.org/patchwork/patch/1254757/ Signed-off-by: Cathy Zhang --- arch/x86/kvm/cpuid.c | 3 ++- 1 file

[PATCH 2/2] x86: Expose TSX Suspend Load Address Tracking

TSX Suspend Load Address Tracking is supported by intel processors, like Sapphire Rapids. Expose it in KVM supported cpuid. The associated kernel enumeration patches link is as follows: https://lore.kernel.org/patchwork/patch/1254756/ Signed-off-by: Cathy Zhang --- arch/x86/kvm/cpuid.c | 2

[PATCH 0/2] Expose new features for intel processor

to choose which memory accesses do not need to be tracked in the TSX read set. Cathy Zhang (2): x86: Expose SERIALIZE for supported cpuid x86: Expose TSX Suspend Load Address Tracking arch/x86/kvm/cpuid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 1.8.3.1