before the Signed-off-by.
1.
https://gerrit.googlesource.com/gerrit/+/master/gerrit-server/src/main/resources/com/google/gerrit/server/tools/root/hooks/commit-msg
Signed-off-by: Christopher Covington c...@codeaurora.org
---
scripts/checkpatch.pl | 6 ++
1 file changed, 6 insertions(+)
diff
Hi Catalin,
On 03/21/2014 12:27 PM, Catalin Marinas wrote:
On Wed, Mar 19, 2014 at 05:35:19PM +, Christopher Covington wrote:
On an LPAE system, the physical addresses used by VirtIO-MMIO may
be larger than 32 bits, even if the header and configuration space
addresses fit into 32 bits
.
Signed-off-by: Christopher Covington
---
scripts/checkpatch.pl | 6 ++
1 file changed, 6 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 464dcef..afd6dde 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -1891,6 +1891,12 @@ sub process
device.
EXT2-fs (vda): error: ext2_check_page: bad entry in directory #2: : unaligned
directory entry - offset=0, inode=3755990991, rec_len=57311, name_len=223
To fix this, select ARCH_DMA_ADDR_T_64BIT when both LPAE and
VIRTIO_MMIO are selected.
Signed-off-by: Christopher Covington
---
arch/arm
On 02/14/2014 01:38 PM, Christopher Covington wrote:
> The kcmp system call was ported to ARM in
> commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458
> "ARM: 7665/1: Wire up kcmp syscall".
>
> Signed-off-by: Christopher Covington
> ---
> arch/arm/include/asm/unis
-off-by: Christopher Covington
---
arch/arm64/include/asm/uaccess.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 7ecc2b2..5974459 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64
-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm64/include/asm/uaccess.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 7ecc2b2..5974459 100644
--- a/arch/arm64/include/asm/uaccess.h
On 02/14/2014 01:38 PM, Christopher Covington wrote:
The kcmp system call was ported to ARM in
commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458
ARM: 7665/1: Wire up kcmp syscall.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm/include/asm/unistd.h | 1 -
1 file
device.
EXT2-fs (vda): error: ext2_check_page: bad entry in directory #2: : unaligned
directory entry - offset=0, inode=3755990991, rec_len=57311, name_len=223
To fix this, select ARCH_DMA_ADDR_T_64BIT when both LPAE and
VIRTIO_MMIO are selected.
Signed-off-by: Christopher Covington c
.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
scripts/checkpatch.pl | 6 ++
1 file changed, 6 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 464dcef..afd6dde 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -1891,6 +1891,12 @@ sub
Hi Kumar,
On 03/17/2014 01:33 PM, Kumar Gala wrote:
>
> On Mar 17, 2014, at 12:31 PM, Christopher Covington
> wrote:
>
>> Hi Stephen,
>>
>> On 03/11/2014 05:24 PM, Stephen Boyd wrote:
>>> The architected timer is not a register addressable piece of
>
Hi Stephen,
On 03/11/2014 05:24 PM, Stephen Boyd wrote:
> The architected timer is not a register addressable piece of
> hardware. Instead it's accessed through cp15 accessors. Move it
> to the root of the devicetree to reflect this.
I find this confusing, perhaps due to overloading of the word
Hi Stephen,
On 03/11/2014 05:24 PM, Stephen Boyd wrote:
The architected timer is not a register addressable piece of
hardware. Instead it's accessed through cp15 accessors. Move it
to the root of the devicetree to reflect this.
I find this confusing, perhaps due to overloading of the word
Hi Kumar,
On 03/17/2014 01:33 PM, Kumar Gala wrote:
On Mar 17, 2014, at 12:31 PM, Christopher Covington c...@codeaurora.org
wrote:
Hi Stephen,
On 03/11/2014 05:24 PM, Stephen Boyd wrote:
The architected timer is not a register addressable piece of
hardware. Instead it's accessed
Hi Catalin, Will,
Thanks for your feedback. I must admit I'm out of my depth here, so I just
posted what I had, hoping to solicit comments like what you all have kindly
provided.
On 03/13/2014 07:20 AM, Catalin Marinas wrote:
> On Wed, Mar 05, 2014 at 10:41:28PM +0000, Christopher Coving
Hi Catalin, Will,
Thanks for your feedback. I must admit I'm out of my depth here, so I just
posted what I had, hoping to solicit comments like what you all have kindly
provided.
On 03/13/2014 07:20 AM, Catalin Marinas wrote:
On Wed, Mar 05, 2014 at 10:41:28PM +, Christopher Covington wrote
Hi Michael,
Thanks for the comments.
On 03/06/2014 03:20 AM, Michael S. Tsirkin wrote:
> On Wed, Mar 05, 2014 at 05:41:28PM -0500, Christopher Covington wrote:
>> Without this, the following scenario is incorrectly determined
>> to be invalid.
>>
>> addr 0x7f_ff
Hi Michael,
Thanks for the comments.
On 03/06/2014 03:20 AM, Michael S. Tsirkin wrote:
On Wed, Mar 05, 2014 at 05:41:28PM -0500, Christopher Covington wrote:
Without this, the following scenario is incorrectly determined
to be invalid.
addr 0x7f_e000 size 8192 addr_limit 0x80_
Without this, the following scenario is incorrectly determined
to be invalid.
addr 0x7f_e000 size 8192 addr_limit 0x80_
This behavior was observed while trying to vmsplice the stack
as part of a CRIU dump of a process.
Signed-off-by: Christopher Covington
---
arch/arm64/include
Without this, the following scenario is incorrectly determined
to be invalid.
addr 0x7f_e000 size 8192 addr_limit 0x80_
This behavior was observed while trying to vmsplice the stack
as part of a CRIU dump of a process.
Signed-off-by: Christopher Covington c...@codeaurora.org
On 02/20/2014 11:09 AM, Kumar Gala wrote:
> We've split Qualcomm MSM support into legacy and multiplatform. The RNG
> driver is only relevant on the multiplatform supported SoCs so switch the
> Kconfig depends to ARCH_QCOM.
>
> CC: Herbert Xu
> CC: Stanimir Varbanov
> Signed-off-by: Kumar Gala
On 02/20/2014 11:09 AM, Kumar Gala wrote:
We've split Qualcomm MSM support into legacy and multiplatform. The RNG
driver is only relevant on the multiplatform supported SoCs so switch the
Kconfig depends to ARCH_QCOM.
CC: Herbert Xu herb...@gondor.apana.org.au
CC: Stanimir Varbanov
The kcmp system call was ported to ARM in
commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458
"ARM: 7665/1: Wire up kcmp syscall".
Signed-off-by: Christopher Covington
---
arch/arm/include/asm/unistd.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/include/asm/unistd.h
The kcmp system call was ported to ARM in
commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458
ARM: 7665/1: Wire up kcmp syscall.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm/include/asm/unistd.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/include/asm/unistd.h
Hi Pawel,
On 02/11/2014 11:53 AM, Pawel Moll wrote:
> This patch tries to solve that issue in a generic way,
> adding a "populated" flag which is set in the device_node
> structure when a device is being created in the core.
> Later, of_platform_populate() skips such nodes (and
> its children) in
Hi Pawel,
On 02/11/2014 11:53 AM, Pawel Moll wrote:
This patch tries to solve that issue in a generic way,
adding a populated flag which is set in the device_node
structure when a device is being created in the core.
Later, of_platform_populate() skips such nodes (and
its children) in a
Hi Georgi,
On 01/30/2014 01:45 PM, Georgi Djakov wrote:
> This patchset adds basic support of the Secure Digital Host Controller
> Interface compliant controller found in Qualcomm chipsets.
>
> Tested with eMMC and various micro SD cards on APQ8074 Dragonboard.
[...]
>
Hi Georgi,
On 01/30/2014 01:45 PM, Georgi Djakov wrote:
This patchset adds basic support of the Secure Digital Host Controller
Interface compliant controller found in Qualcomm chipsets.
Tested with eMMC and various micro SD cards on APQ8074 Dragonboard.
[...]
On 01/15/2014 12:55 PM, Stephen Boyd wrote:
> Some CPU PMUs are wired up with one PPI for all the CPUs instead
> of with a different SPI for each CPU. Add support for these
> devices.
>
> Signed-off-by: Stephen Boyd
> ---
> arch/arm/kernel/perf_event.c | 14 --
>
Hi Christoffer,
On 02/02/2014 11:56 PM, Christoffer Dall wrote:
> On Thu, Jan 30, 2014 at 11:54:46AM -0500, Christopher Covington wrote:
>> I think it would be informative to provide pointers here to commonly used
>> paravirtualized devices, especially VirtIO PCI/MMIO.
>
> I
Hi Christoffer,
On 02/02/2014 11:56 PM, Christoffer Dall wrote:
On Thu, Jan 30, 2014 at 11:54:46AM -0500, Christopher Covington wrote:
I think it would be informative to provide pointers here to commonly used
paravirtualized devices, especially VirtIO PCI/MMIO.
I disagree: that would only
On 01/15/2014 12:55 PM, Stephen Boyd wrote:
Some CPU PMUs are wired up with one PPI for all the CPUs instead
of with a different SPI for each CPU. Add support for these
devices.
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
arch/arm/kernel/perf_event.c | 14 --
Hi Ian,
On 01/30/2014 12:15 PM, Ian Campbell wrote:
> On Thu, 2014-01-30 at 11:54 -0500, Christopher Covington wrote:
>>> +++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
>>> @@ -0,0 +1,32 @@
>>> +* Mach-virt "Dummy Virtual Machine" platfor
Hi Ian,
On 01/30/2014 11:11 AM, Ian Campbell wrote:
> mach-virt has existed for a while but it is not written down what it actually
> consists of. Although it seems a bit unusual to document a binding for an
> entire platform since mach-virt is entirely virtual it is helpful to have
> something
Hi Ian,
On 01/30/2014 11:11 AM, Ian Campbell wrote:
mach-virt has existed for a while but it is not written down what it actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt is entirely virtual it is helpful to have
something to
Hi Ian,
On 01/30/2014 12:15 PM, Ian Campbell wrote:
On Thu, 2014-01-30 at 11:54 -0500, Christopher Covington wrote:
+++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
@@ -0,0 +1,32 @@
+* Mach-virt Dummy Virtual Machine platform
+
+mach-virt is the smallest, dumbest platform possible
Hi Will,
On 01/29/2014 05:57 AM, Will Deacon wrote:
> Hi Christopher,
>
> On Tue, Jan 28, 2014 at 06:51:51PM +, Christopher Covington wrote:
>> Add the trivial support necessary to get hardware breakpoints
>> working for GDB on ARMv8 simulators running in AArc
Hi Will,
On 01/29/2014 05:57 AM, Will Deacon wrote:
Hi Christopher,
On Tue, Jan 28, 2014 at 06:51:51PM +, Christopher Covington wrote:
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Acked-by: Will Deacon
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Acked-by: Will Deacon
Signed-off-by: Christopher Covington
---
v3: assume for now that ARMv9 and later will update FSR
v2: modify debug_exception_updates_fsr
arch/arm
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Signed-off-by: Christopher Covington
---
v2: modify debug_exception_updates_fsr
arch/arm/include/asm/hw_breakpoint.h | 1 +
arch/arm/kernel/hw_breakpoint.c | 3
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
v2: modify debug_exception_updates_fsr
arch/arm/include/asm/hw_breakpoint.h | 1 +
arch/arm/kernel
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Acked-by: Will Deacon will.dea...@arm.com
Signed-off-by: Christopher Covington c...@codeaurora.org
---
v3: assume for now that ARMv9 and later will update FSR
v2: modify
On 01/24/2014 12:52 PM, Christopher Covington wrote:
> On 01/24/2014 12:17 PM, Will Deacon wrote:
>> On Fri, Jan 24, 2014 at 05:16:28PM +, Adrien Vergé wrote:
>>> 2014/1/24 Will Deacon :
>>>> Are you sure about this? The value we write is actually task_pid_
On 01/24/2014 06:39 AM, Mark Rutland wrote:
> On Thu, Jan 23, 2014 at 07:20:01PM +, Feng Kan wrote:
>> Add documentation for generic SYSCON reboot driver.
>>
>> Signed-off-by: Feng Kan
>> ---
>> .../bindings/power/reset/syscon-reboot.txt | 16
>> 1 files changed,
On 01/24/2014 12:17 PM, Will Deacon wrote:
> On Fri, Jan 24, 2014 at 05:16:28PM +, Adrien Vergé wrote:
>> 2014/1/24 Will Deacon :
>>> Are you sure about this? The value we write is actually task_pid_nr, which I
>>> believe to be globally unique.
>>
>> You are right: the task_pid_nr is unique
On 01/24/2014 12:17 PM, Will Deacon wrote:
On Fri, Jan 24, 2014 at 05:16:28PM +, Adrien Vergé wrote:
2014/1/24 Will Deacon will.dea...@arm.com:
Are you sure about this? The value we write is actually task_pid_nr, which I
believe to be globally unique.
You are right: the task_pid_nr is
On 01/24/2014 06:39 AM, Mark Rutland wrote:
On Thu, Jan 23, 2014 at 07:20:01PM +, Feng Kan wrote:
Add documentation for generic SYSCON reboot driver.
Signed-off-by: Feng Kan f...@apm.com
---
.../bindings/power/reset/syscon-reboot.txt | 16
1 files changed, 16
On 01/24/2014 12:52 PM, Christopher Covington wrote:
On 01/24/2014 12:17 PM, Will Deacon wrote:
On Fri, Jan 24, 2014 at 05:16:28PM +, Adrien Vergé wrote:
2014/1/24 Will Deacon will.dea...@arm.com:
Are you sure about this? The value we write is actually task_pid_nr, which
I
believe
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Signed-off-by: Christopher Covington
---
arch/arm/include/asm/hw_breakpoint.h | 1 +
arch/arm/kernel/hw_breakpoint.c | 1 +
2 files changed, 2 insertions(+)
diff
Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm/include/asm/hw_breakpoint.h | 1 +
arch/arm/kernel/hw_breakpoint.c | 1 +
2 files changed, 2
On 01/17/2014 01:50 PM, Stephen Boyd wrote:
> On 01/06, Christopher Covington wrote:
>> The pgtbl macro couldn't handle the specific
>> (TEXT_OFFSET - PG_DIR_SIZE) value that the combination of
>> MSM platforms and LPAE created:
>>
>> head.S:163: Error: inva
On 01/17/2014 01:50 PM, Stephen Boyd wrote:
On 01/06, Christopher Covington wrote:
The pgtbl macro couldn't handle the specific
(TEXT_OFFSET - PG_DIR_SIZE) value that the combination of
MSM platforms and LPAE created:
head.S:163: Error: invalid constant (203000) after fixup
Regardless
Hi Josh,
On 01/17/2014 12:26 PM, Josh Cartwright wrote:
[...]
> @@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
> #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
> #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
>
> -#ifdef CONFIG_PM_SLEEP
> +#if
Hi Josh,
On 01/17/2014 12:26 PM, Josh Cartwright wrote:
[...]
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#if defined(CONFIG_PM_SLEEP) ||
db.de
> CC: o...@lixom.net
> CC: catalin.mari...@arm.com
Looks good to me.
Acked-by Christopher Covington
While I don't think it should necessarily gate these changes, I wonder if at
some point the config options could be consolidated across the various
architectures using them.
Regard
: catalin.mari...@arm.com
Looks good to me.
Acked-by Christopher Covington c...@codeaurora.org
While I don't think it should necessarily gate these changes, I wonder if at
some point the config options could be consolidated across the various
architectures using them.
Regards,
Christopher
at run time, make it
at least assemble properly.
Signed-off-by: Christopher Covington
---
arch/arm/kernel/head.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 9cf6063..af30cac 100644
--- a/arch/arm/kernel/head.S
+++ b
at run time, make it
at least assemble properly.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm/kernel/head.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 9cf6063..af30cac 100644
--- a/arch/arm
On 12/05/2013 03:16 PM, Greg Kroah-Hartman wrote:
> On Thu, Dec 05, 2013 at 03:12:50PM -0500, Christopher Covington wrote:
[...]
> And adding new features to code that is "dead" and should probably be
> removed isn't a good idea, as I'm sure you can understand.
I would conside
Hi Greg,
On 12/04/2013 11:01 PM, Greg Kroah-Hartman wrote:
> On Wed, Dec 04, 2013 at 10:49:25PM -0500, Adrien Vergé wrote:
>> 2013/12/4 Greg Kroah-Hartman :
>>> How much overhead does the existing tracing code have on ARM? Is ETM
>>> still even needed? Why not just use ETM for the core tracing
Hi Greg,
On 12/04/2013 11:01 PM, Greg Kroah-Hartman wrote:
On Wed, Dec 04, 2013 at 10:49:25PM -0500, Adrien Vergé wrote:
2013/12/4 Greg Kroah-Hartman gre...@linuxfoundation.org:
How much overhead does the existing tracing code have on ARM? Is ETM
still even needed? Why not just use ETM for
On 12/05/2013 03:16 PM, Greg Kroah-Hartman wrote:
On Thu, Dec 05, 2013 at 03:12:50PM -0500, Christopher Covington wrote:
[...]
And adding new features to code that is dead and should probably be
removed isn't a good idea, as I'm sure you can understand.
I would consider feature additions
Hi Pavel,
On 11/28/2013 12:11 PM, Pavel Machek wrote:
> Hi!
>
> For testing, it would be good to have some real
> userland... unfortunately I can't figure out how to do it.
>
> Ideally, I'd like to put nemo-armv7hl-n900-mmcblk0p.raw on emulated sd
> card, but I get:
>
> [1.566345]
Hi Pavel,
On 11/28/2013 12:11 PM, Pavel Machek wrote:
Hi!
For testing, it would be good to have some real
userland... unfortunately I can't figure out how to do it.
Ideally, I'd like to put nemo-armv7hl-n900-mmcblk0p.raw on emulated sd
card, but I get:
[1.566345] Initializing XFRM
Hi Catalin,
On 11/18/2013 12:30 PM, Catalin Marinas wrote:
[...]
> You can't run legacy AArch32 code at EL3 and have lower levels in AArch64
> mode (architectural constraint).
What prevents AArch32 code from running at EL3 and then requesting a reset to
AArch64 by writing to the Reset Management
Hi Catalin,
On 11/18/2013 12:30 PM, Catalin Marinas wrote:
[...]
You can't run legacy AArch32 code at EL3 and have lower levels in AArch64
mode (architectural constraint).
What prevents AArch32 code from running at EL3 and then requesting a reset to
AArch64 by writing to the Reset Management
Hi Ivan,
On 11/12/2013 09:51 AM, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> This patch fix compilation error when driver is compiled
> in multi-platform builds.
>
> drivers/built-in.o: In function `msm_otg_link_clk_reset':
> ./drivers/usb/phy/phy-msm-usb.c:314: undefined reference to
Hi Ivan,
On 11/12/2013 09:51 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
This patch fix compilation error when driver is compiled
in multi-platform builds.
drivers/built-in.o: In function `msm_otg_link_clk_reset':
./drivers/usb/phy/phy-msm-usb.c:314: undefined
Hi Stephen,
On 11/07/2013 02:20 PM, Stephen Boyd wrote:
> If we're running on a v7 ARM CPU, detect if the CPU supports the
> sdiv/udiv instructions and replace the signed and unsigned
> division library functions with an sdiv/udiv instruction.
[...]
> +++ b/arch/arm/lib/div-v7.c
> @@ -0,0 +1,58
Hi Stephen,
On 11/07/2013 02:20 PM, Stephen Boyd wrote:
If we're running on a v7 ARM CPU, detect if the CPU supports the
sdiv/udiv instructions and replace the signed and unsigned
division library functions with an sdiv/udiv instruction.
[...]
+++ b/arch/arm/lib/div-v7.c
@@ -0,0 +1,58 @@
Put architecture-specific assembly code where it belongs,
allowing for support of additional architectures such as arm64 in
the future.
Signed-off-by: Christopher Covington
---
arch/arm/include/asm/dcc.h | 45 +++
drivers/tty/hvc/hvc_dcc.c | 48
Put architecture-specific assembly code where it belongs,
allowing for support of additional architectures such as arm64 in
the future.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm/include/asm/dcc.h | 45 +++
drivers/tty/hvc
Hi Jiang,
On 09/25/2013 06:44 AM, Jiang Liu wrote:
[...]
> diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
[...]
> +static int aarch64_insn_cls[] = {
> + AARCH64_INSN_CLS_UNKNOWN, /* 0 0 X X */
> + AARCH64_INSN_CLS_UNKNOWN, /* 0 0 X X */
> +
Hi Jiang,
On 09/25/2013 06:44 AM, Jiang Liu wrote:
[...]
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
[...]
+static int aarch64_insn_cls[] = {
+ AARCH64_INSN_CLS_UNKNOWN, /* 0 0 X X */
+ AARCH64_INSN_CLS_UNKNOWN, /* 0 0 X X */
+
On 07/30/2013 06:09 AM, Jean-Francois Moine wrote:
> On Tue, 30 Jul 2013 10:44:57 +0100
> Dave Martin wrote:
>> On Tue, Jul 30, 2013 at 11:38:53AM +0200, Jean-Francois Moine wrote:
>>> On Tue, 30 Jul 2013 10:25:18 +0100
>>> Dave Martin wrote:
The pragmatic route is less contraversial and
On 07/30/2013 06:09 AM, Jean-Francois Moine wrote:
On Tue, 30 Jul 2013 10:44:57 +0100
Dave Martin dave.mar...@arm.com wrote:
On Tue, Jul 30, 2013 at 11:38:53AM +0200, Jean-Francois Moine wrote:
On Tue, 30 Jul 2013 10:25:18 +0100
Dave Martin dave.mar...@arm.com wrote:
The pragmatic route is
insertions(+), 115 deletions(-)
>
I ran 32-bit and 64-bit kernels with these patches on the Versatile Express
software model and things looked fine, so for the applicable patches,
Tested-by: Christopher Covington
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, I
/sched_clock.c | 105
+++---
18 files changed, 116 insertions(+), 115 deletions(-)
I ran 32-bit and 64-bit kernels with these patches on the Versatile Express
software model and things looked fine, so for the applicable patches,
Tested-by: Christopher
On 06/26/2013 01:11 PM, Will Deacon wrote:
> On Mon, Jun 24, 2013 at 04:15:06PM +0100, Christopher Covington wrote:
>> On 06/24/2013 10:53 AM, Will Deacon wrote:
>>> On Mon, Jun 24, 2013 at 03:39:09PM +0100, Christopher Covington wrote:
>>>> Hi Will,
>>>>
On 06/26/2013 01:11 PM, Will Deacon wrote:
On Mon, Jun 24, 2013 at 04:15:06PM +0100, Christopher Covington wrote:
On 06/24/2013 10:53 AM, Will Deacon wrote:
On Mon, Jun 24, 2013 at 03:39:09PM +0100, Christopher Covington wrote:
Hi Will,
On 06/24/2013 10:04 AM, Will Deacon wrote
On 06/25/2013 02:11 PM, Leif Lindholm wrote:
> This patch provides documentation of the [U]EFI runtime services and
> configuration features.
>
> Signed-off-by: Leif Lindholm
> ---
> Documentation/arm/00-INDEX |3 +++
> Documentation/arm/uefi.txt | 39
On 06/25/2013 02:11 PM, Leif Lindholm wrote:
This patch provides documentation of the [U]EFI runtime services and
configuration features.
Signed-off-by: Leif Lindholm leif.lindh...@linaro.org
---
Documentation/arm/00-INDEX |3 +++
Documentation/arm/uefi.txt | 39
On 06/24/2013 10:53 AM, Will Deacon wrote:
> On Mon, Jun 24, 2013 at 03:39:09PM +0100, Christopher Covington wrote:
>> Hi Will,
>>
>> On 06/24/2013 10:04 AM, Will Deacon wrote:
>> [...]
>>
>>> What's the advantage of this approach, other than you get an
Hi Will,
On 06/24/2013 10:04 AM, Will Deacon wrote:
[...]
> What's the advantage of this approach, other than you get an extra byte's
> worth of PID?
In my view, the real advantage is that the the PID is located where people
reading ARM Architecture Reference Manual are told they can find it.
Using the long-descriptor translation table format changes
the layout of the CONTEXTIDR register.
Signed-off-by: Christopher Covington
---
arch/arm/mm/context.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mm/context.c b
Using the long-descriptor translation table format changes
the layout of the CONTEXTIDR register.
Signed-off-by: Christopher Covington c...@codeaurora.org
---
arch/arm/mm/context.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/arch
Hi Will,
On 06/24/2013 10:04 AM, Will Deacon wrote:
[...]
What's the advantage of this approach, other than you get an extra byte's
worth of PID?
In my view, the real advantage is that the the PID is located where people
reading ARM Architecture Reference Manual are told they can find it.
On 06/24/2013 10:53 AM, Will Deacon wrote:
On Mon, Jun 24, 2013 at 03:39:09PM +0100, Christopher Covington wrote:
Hi Will,
On 06/24/2013 10:04 AM, Will Deacon wrote:
[...]
What's the advantage of this approach, other than you get an extra byte's
worth of PID?
In my view, the real
e timestamps when
> the hardware returns a value instead of 0 upon the first read.
Builds and runs for me on software models.
Tested-by: Christopher Covington
Cheers,
Christopher
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Auror
the hardware returns a value instead of 0 upon the first read.
Builds and runs for me on software models.
Tested-by: Christopher Covington c...@codeaurora.org
Cheers,
Christopher
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
Hi Will,
On 06/05/2013 08:50 AM, Will Deacon wrote:
> On Wed, Jun 05, 2013 at 01:44:55PM +0100, Arnd Bergmann wrote:
>> On Wednesday 05 June 2013 13:15:29 Stefano Stabellini wrote:
>>> diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
>>> index c95c5cb..79dd13d 100644
>>> ---
Hi Will,
On 06/05/2013 08:50 AM, Will Deacon wrote:
On Wed, Jun 05, 2013 at 01:44:55PM +0100, Arnd Bergmann wrote:
On Wednesday 05 June 2013 13:15:29 Stefano Stabellini wrote:
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index c95c5cb..79dd13d 100644
--- a/arch/arm64/Makefile
+++
t;
> Changes in v3:
> - improve commit description and Kconfig help text;
> - no need to initialize pv_time_ops;
> - add PARAVIRT_TIME_ACCOUNTING.
Looks good to me.
Acked-by: Christopher Covington
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. i
description and Kconfig help text;
- no need to initialize pv_time_ops;
- add PARAVIRT_TIME_ACCOUNTING.
Looks good to me.
Acked-by: Christopher Covington c...@codeaurora.org
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted
Hi Pranavkumar,
On 05/13/2013 02:56 AM, Pranavkumar Sawargaonkar wrote:
> Hi Rusty,
>
> On 13 May 2013 08:22, Rusty Russell wrote:
>> Pranavkumar Sawargaonkar writes:
>>> Signed-off-by: Pranavkumar Sawargaonkar
>>> Signed-off-by: Anup Patel
>>> ---
>>> Documentation/virtual/virtio-spec.txt
Hi Will,
On 05/08/2013 05:06 AM, Will Deacon wrote:
> Hello Christopher,
>
> On Tue, May 07, 2013 at 04:48:26PM +0100, Christopher Covington wrote:
>> On 05/07/2013 05:08 AM, Will Deacon wrote:
>>> That seems like a lot of effort in order to preserve something that isn't
Hi Will,
On 05/08/2013 05:06 AM, Will Deacon wrote:
Hello Christopher,
On Tue, May 07, 2013 at 04:48:26PM +0100, Christopher Covington wrote:
On 05/07/2013 05:08 AM, Will Deacon wrote:
That seems like a lot of effort in order to preserve something that isn't
even meaningful. We might
Hi Pranavkumar,
On 05/13/2013 02:56 AM, Pranavkumar Sawargaonkar wrote:
Hi Rusty,
On 13 May 2013 08:22, Rusty Russell ru...@rustcorp.com.au wrote:
Pranavkumar Sawargaonkar pranavku...@linaro.org writes:
Signed-off-by: Pranavkumar Sawargaonkar pranavku...@linaro.org
Signed-off-by: Anup
On 05/08/2013 07:19 AM, Stefano Stabellini wrote:
> On Tue, 7 May 2013, Christopher Covington wrote:
>> Hi Konrad,
>>
>> On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
>>>>> e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
>>
On 05/08/2013 07:19 AM, Stefano Stabellini wrote:
On Tue, 7 May 2013, Christopher Covington wrote:
Hi Konrad,
On 05/06/2013 10:35 AM, Konrad Rzeszutek Wilk wrote:
e.g. if a VCPU sets a timer for NOW+5, but 3 are stolen in the middle it
would not make sense (from the guests PoV) for NOW'==NOW
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