are described by the
LPC_LPT_LP descriptor.
See:
http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html
Signed-off-by: Dan Gora
---
drivers/mfd/lpc_ich.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
in
On Feb 15, 2008 10:00 PM, Robert Hancock <[EMAIL PROTECTED]> wrote:
>
> Well, in order for the CPU to batch up more writes you'd have to map the
> BAR as either write-combining or write-back. If it's not listed in
> /proc/mtrr it will be the default setting of uncacheable.
Ok, this is pretty muc
On Fri, Feb 15, 2008 at 5:02 AM, Alan Cox <[EMAIL PROTECTED]> wrote:
> > Is there any way to get PIO to burst over the PCI bus in the read and
> > write direction? My device has 4 BAR registers, but the area where I
>
> I think you are doign about as well as the X folks did when they spent
> ti
On Fri, Feb 15, 2008 at 2:54 AM, Andi Kleen <[EMAIL PROTECTED]> wrote:
> "Dan Gora" <[EMAIL PROTECTED]> writes:
> >
> > Is there any way to get PIO
>
> I assume you really mean MMIO, not PIO. PIO would be port IO.
Sorry, I always saw it referr
Hi,
I am trying to optimize a driver for a slave only PCI device and am
having a lot of trouble getting any kind of PCI burst transactions in
either the read or the write direction. Using bcopy/memcpy or even a
hand-crafted while (len) { *pdst++ = *psrc++} (with pdst and psrc
unsigned long*) I ca
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