eset-controller" devicetree property can easily
enabled by adding this.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-submit with recipients from Rockchip.
v3: - Added devicetree property to enable the PMIC reset seperate from
"rockchip,system-power-controller&qu
Since all three shutdown functions have almost the same code, all logic
from the shutdown functions can be refactored to a new function
"rk808_update_bits", which can update a register by a given address and
bitmask.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-s
Hi Rob,
On 03/18/2018 01:52 PM, Rob Herring wrote:
On Thu, Mar 15, 2018 at 11:58:50AM +0100, Daniel Schultz wrote:
Add documentation about a new rk808 devicetree property, which can
enable resets by the PMIC.
The subject needs to be more specific that this is for Rockchip PMIC.
Signed-off
Add documentation about a new rk808 devicetree property. This can enable
the rk805/rk808/rk818 PMIC reset, instead of using soft resets from the
Control and Reset Module.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Changed commit message
Documentation/devicetree/bindings/mfd/rk808
eset-controller" devicetree property can easily
enabled by adding this.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-submit with recipients from Rockchip.
v3: - Added devicetree property to enable the PMIC reset seperate from
"rockchip,system-power-controller&qu
Since all three shutdown functions have almost the same code, all logic
from the shutdown functions can be refactored to a new function
"rk808_update_bits", which can update a register by a given address and
bitmask.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-s
ked to the software restart by removing the property.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-submit with recipients from Rockchip.
v3: - Added devicetree property to enable the PMIC reset seperate from
"rockchip,system-power-controller".
Add documentation about a new rk808 devicetree property, which can
enable resets by the PMIC.
Signed-off-by: Daniel Schultz
---
Documentation/devicetree/bindings/mfd/rk808.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt
b/Documentation
patches please.
Please provide Reviewed-by/Tested-by tags.
On Wed, 07 Mar 2018, Daniel Schultz wrote:
After running "poweroff", the PMIC restarts the SoC instead of shutting
it down.
It seems like the description for those two register bits is swapped.
After changing from DEV_OFF to DE
:
Rockchip guys,
I'd really appreciate your input on these two patches please.
Please provide Reviewed-by/Tested-by tags.
On Wed, 07 Mar 2018, Daniel Schultz wrote:
When using Rockchip SoCs with rk805/808/818 PMICs, restarts are
realized by
setting the reset registers in the "Clock
This adds the driver for TI's DP83867 ethernet phy.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-submit with more recipients.
Sorry, I only added Russell and vger in v1.
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arc
ked to the software restart by removing the property.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-submit with recipients from Rockchip.
drivers/mfd/rk808.c | 97 ++-
include/linux/mfd/rk808.h | 1 +
2 files changed, 63 insertions(+),
After running "poweroff", the PMIC restarts the SoC instead of shutting
it down.
It seems like the description for those two register bits is swapped.
After changing from DEV_OFF to DEV_OFF_RST, the system can poweroff
correctly.
Signed-off-by: Daniel Schultz
---
Changes:
v2:
Hi,
On 03/05/2018 10:08 PM, Heiko Stübner wrote:
Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner:
Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we
Hi,
On 03/05/2018 03:15 PM, Heiko Stuebner wrote:
Hi Daniel,
Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz:
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Daniel
ked to the software restart by removing the property.
Signed-off-by: Daniel Schultz
---
drivers/mfd/rk808.c | 97 ++-
include/linux/mfd/rk808.h | 1 +
2 files changed, 63 insertions(+), 35 deletions(-)
diff --git a/drivers/mfd/rk808.c b/dri
After running "poweroff", the PMIC restarts the SoC instead of shutting
it down.
It seems like the description for those two register bits is swapped.
After changing from DEV_OFF to DEV_OFF_RST, the system can poweroff
correctly.
Signed-off-by: Daniel Schultz
---
drivers/mfd/rk808.c
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Daniel Schultz
---
The binding will be added with the next merge of net-next:
https://git.kernel.org/pub/scm/linux/kernel/git/davem
: Daniel Schultz
---
include/linux/mfd/rk808.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index d315659..338e0f6 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -443,7 +443,7 @@ enum {
enum
From: Wadim Egorov
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
Changes:
v2:
Added check
From: Wadim Egorov
Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
Changes:
v2:
-
v3:
Fixed indentation.
Documentation/devicetree/bindings/net
On 02/14/2018 09:07 AM, Heiko Stübner wrote:
Am Dienstag, 13. Februar 2018, 10:44:32 CET schrieb Daniel Schultz:
Rockchip recommends to run the CPU cores only with operations points of
1.6 GHz or lower.
Removed the cpu0 node with too high operation points and use the default
values instead
From: Wadim Egorov
Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
Documentation/devicetree/bindings/net/ti,dp83867.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a
From: Wadim Egorov
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
Changes:
Added check if
Rockchip recommends to run the CPU cores only with operations points of
1.6 GHz or lower.
Removed the cpu0 node with too high operation points and use the default
values instead.
Signed-off-by: Daniel Schultz
---
arch/arm/boot/dts/rk3288-phycore-som.dtsi | 20
1 file
igned-off-by: Daniel Schultz
---
arch/arm/boot/dts/rk3288-phycore-rdk.dts | 4
arch/arm/boot/dts/rk3288-phycore-som.dtsi | 5 ++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index ec
From: Wadim Egorov
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
drivers/net/phy/dp83867.c| 14
From: Wadim Egorov
Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
Documentation/devicetree/bindings/net/ti,dp83867.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a
From: Wadim Egorov
The card is powered by the RK818 switch vdd_sd which is supplied
by VCC9 (VDD_3V3_IO).
Signed-off-by: Wadim Egorov
Signed-off-by: Daniel Schultz
---
arch/arm/boot/dts/rk3288-phycore-rdk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot
This adds the driver for TI's DP83867 ethernet phy.
Signed-off-by: Daniel Schultz
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 61509c4..8313fa1 100644
--- a/arc
If the tps65910 driver has no interrupt, the probe of tps65910-rtc will
fail.
This patch adds a check in the probe of the rtc if an interrupt exist.
The check is similar to the check in the function which creates the
interrupt.
Signed-off-by: Daniel Schultz
---
drivers/rtc/rtc-tps65910.c | 5
s 8f276fff instead of
8f277000. Since this adjustment isn't necessary for the LCDC v2, the
origin ceiling address should be used.
Signed-off-by: Daniel Schultz
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tilcd
This error message will be printed when a FIFO underflow irq has
triggered. Since this happens sometimes and the error message will be
displayed on the console, it should have a correct spelling.
Signed-off-by: Daniel Schultz
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
1 file changed, 1
odule will jump to
an error label below.
Signed-off-by: Daniel Schultz
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index d278093..d491610 100644
--- a/d
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