From: Daniele Alessandrelli
In ocs_aes_ccm_write_b0(), 'q' (the octet length of the binary
representation of the octet length of the payload) is set to 'iv[0]',
while it should be set to 'iv[0] & 0x7' (i.e., only the last 3
bits of iv[0] should be used), as documented in NIST Special Publica
From: Daniele Alessandrelli
The length ('len' parameter) passed to crypto_ecdh_decode_key() is never
checked against the length encoded in the passed buffer ('buf'
parameter). This could lead to an out-of-bounds access when the passed
length is less than the encoded length.
Add a check
On Thu, 2021-01-28 at 21:39 +1100, Herbert Xu wrote:
> Once they're distinct algorithms, we can then make sure that only
> the ones that are used in the kernel is added, even if some hardware
> may support more curves.
I like the idea of having different algorithms names (ecdh-nist-
pXXX) for
From: Daniele Alessandrelli
Add dependency for CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 on HAS_IOMEM to
prevent build failures.
Fixes: 88574332451380f4 ("crypto: keembay - Add support for Keem Bay OCS
AES/SM4")
Reported-by: kernel test robot
Signed-off-by: Daniele Alessandrelli
---
driv
On Tue, 2020-12-08 at 20:48 +0100, Greg KH wrote:
> On Tue, Dec 08, 2020 at 06:59:09PM +0000, Daniele Alessandrelli wrote:
> > Hi Greg,
> >
> > Thanks for your feedback.
> >
> > On Wed, 2020-12-02 at 07:19 +0100, Greg KH wrote:
> > > On
Hi Greg,
Thanks for your feedback.
On Wed, 2020-12-02 at 07:19 +0100, Greg KH wrote:
> On Tue, Dec 01, 2020 at 02:34:52PM -0800, mgr...@linux.intel.com wrote:
> > From: Daniele Alessandrelli
> >
> > On the Intel Movidius SoC code named Keem Bay, communication between
Hi Rob,
Thanks for the feedback.
On Mon, 2020-12-07 at 10:01 -0600, Rob Herring wrote:
> On Tue, Dec 01, 2020 at 02:34:51PM -0800, mgr...@linux.intel.com wrote:
> > From: Daniele Alessandrelli
> >
> > Add DT binding documentation for the Intel Keem Bay IPC driv
On Fri, 2020-07-17 at 11:31 +0100, Sudeep Holla wrote:
> On Thu, Jul 16, 2020 at 12:57:23PM -0700, Florian Fainelli wrote:
> >
> > On 7/16/2020 7:13 AM, Daniele Alessandrelli wrote:
> > > Hi Florian,
> > >
> > > Thanks for you feedback.
> > >
On Thu, 2020-07-16 at 12:57 -0700, Florian Fainelli wrote:
>
> On 7/16/2020 7:13 AM, Daniele Alessandrelli wrote:
> > Hi Florian,
> >
> > Thanks for you feedback.
> >
> > On Wed, 2020-07-15 at 15:43 -0700, Florian Fainelli wrote:
> > > On 7
From: Daniele Alessandrelli
Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.
Reviewed-by: Dinh Nguyen
Reviewed-by: Rob Herring
Signed-off-by: Daniele Alessandrelli
---
.../bindings/arm/intel,keembay.yaml | 19 +++
1 file changed
From: Daniele Alessandrelli
Add maintainers for the new Intel Movidius SoC code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b4a43a9e7fbc..3babb333b556
From: Daniele Alessandrelli
Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
arch/arm64/Kconfig.platforms | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64
From: Daniele Alessandrelli
Add initial device tree for Intel Movidius SoC code-named Keem Bay.
This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS| 1
dual license (GPL-2.0-only or BSD-3-Clause) to dt-bindings header
files and DTS files.
Changes from v1 to v2:
* Moved keembay-scmi-mailbox driver to a separate patchset
* Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree
Regards,
Daniele
Daniele Alessandrelli (5
From: Daniele Alessandrelli
Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 1 +
arch/arm64/boot/dts
Hi Florian,
Thanks for you feedback.
On Wed, 2020-07-15 at 15:43 -0700, Florian Fainelli wrote:
>
> On 7/15/2020 9:55 AM, Daniele Alessandrelli wrote:
> > From: Daniele Alessandrelli
> >
> > Currently, when SMC/HVC is used as transport, the base address of
> &
From: Daniele Alessandrelli
Currently, when SMC/HVC is used as transport, the base address of the
shared memory used for communication is not passed to the SMCCC call.
This means that such an address must be hard-coded into the bootloader.
In order to increase flexibility and allow the memory
On Tue, 2020-07-14 at 15:12 -0600, Rob Herring wrote:
> On Tue, Jul 14, 2020 at 05:13:01PM +0100, Daniele Alessandrelli
> wrote:
> > From: Daniele Alessandrelli
> >
> > Add clock dt-bindings for Keem Bay SoC.
>
> Where's the binding schema?
I should have speci
On Tue, 2020-07-14 at 15:11 -0600, Rob Herring wrote:
> On Tue, Jul 14, 2020 at 05:13:00PM +0100, Daniele Alessandrelli
> wrote:
> > From: Daniele Alessandrelli
> >
> > Document Intel Movidius SoC code-named Keem Bay, along with the
> > Keem Bay
> > EVM boar
From: Daniele Alessandrelli
Add clock dt-bindings for Keem Bay SoC.
Signed-off-by: Daniele Alessandrelli
---
include/dt-bindings/clock/keembay-clocks.h | 188 +
1 file changed, 188 insertions(+)
create mode 100644 include/dt-bindings/clock/keembay-clocks.h
diff --git
From: Daniele Alessandrelli
Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
arch/arm64/Kconfig.platforms | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64
From: Daniele Alessandrelli
Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
.../devicetree/bindings/arm/keembay.yaml | 19 +++
1 file changed, 19 insertions(+)
create
From: Daniele Alessandrelli
Add maintainers for the new Intel Movidius SoC code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b4a43a9e7fbc..b151d0fc0588
From: Daniele Alessandrelli
Add power domain dt-bindings for Keem Bay SoC.
Signed-off-by: Daniele Alessandrelli
---
include/dt-bindings/power/keembay-power.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/power/keembay-power.h
diff --git
From: Daniele Alessandrelli
Add initial device tree for Intel Movidius SoC code-named Keem Bay.
This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS| 1
From: Daniele Alessandrelli
Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 1 +
arch/arm64/boot/dts
patchset
* Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree
Regards,
Daniele
Daniele Alessandrelli (7):
arm64: Add config for Keem Bay SoC
dt-bindings: arm: Add Keem Bay bindings
dt-bindings: clock: Add Keem Bay clock IDs
dt-bindings: power: Add Keem Bay power
On Tue, 2020-07-14 at 14:40 +0200, Arnd Bergmann wrote:
> On Wed, Jul 8, 2020 at 7:50 PM Daniele Alessandrelli
> wrote:
> > Hi,
> >
> > This patch-set adds initial support for a new Intel Movidius SoC
> > code-named
> > Keem Bay. The SoC couples an ARM Corte
On Mon, 2020-07-13 at 21:12 -0600, Rob Herring wrote:
> On Wed, Jul 08, 2020 at 06:50:17PM +0100, Daniele Alessandrelli
> wrote:
> > From: Daniele Alessandrelli
> >
> > Document Intel Movidius SoC code-named Keem Bay, along with the
> > Keem Bay
> > EVM boar
Hi Sudeep,
Thanks for your review.
On Wed, 2020-07-08 at 21:34 +0100, Sudeep Holla wrote:
> On Tue, Jun 16, 2020 at 04:56:08PM +0100, Daniele Alessandrelli
> wrote:
> > From: Paul Murphy
> >
> > Keem Bay SoC has a ARM trusted firmware-based secure monitor which
From: Daniele Alessandrelli
Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
.../devicetree/bindings/arm/keembay.yaml | 19 ++
include/dt-bindings/clock/keembay-clocks.h| 188
From: Daniele Alessandrelli
Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 1 +
arch/arm64/boot/dts
v1 to v2:
* Moved keembay-scmi-mailbox driver to a separate patchset
* Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree
Regards,
Daniele
Daniele Alessandrelli (5):
arm64: Add config for Keem Bay SoC
dt-bindings: arm: Add Keem Bay bindings
MAINTAINERS: Add
From: Daniele Alessandrelli
Add maintainers for the new Intel Movidius SoC code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1d4aa7f942de..ceb833fa04dd
From: Daniele Alessandrelli
Add initial device tree for Intel Movidius SoC code-named Keem Bay.
This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS| 1
From: Daniele Alessandrelli
Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
arch/arm64/Kconfig.platforms | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64
On Sun, 2020-07-05 at 23:36 -0500, Jassi Brar wrote:
> On Tue, Jun 16, 2020 at 10:56 AM Daniele Alessandrelli
> wrote:
> > Hi,
> >
> > This patch-set adds initial support for a new Intel Movidius SoC
> > code-named
> > Keem Bay. The SoC couples an ARM Corte
On Tue, 2020-06-16 at 16:56 +0100, Daniele Alessandrelli wrote:
> Hi,
>
> This patch-set adds initial support for a new Intel Movidius SoC
> code-named
> Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel
> Movidius VPU.
>
> This initial patch-set enab
From: Paul Murphy
These are the bindings required for the Intel Keem Bay SCMI mailbox
driver.
Reviewed-by: Dinh Nguyen
Signed-off-by: Paul Murphy
---
.../mailbox/intel,keembay-scmi-mailbox.yaml | 44 +++
1 file changed, 44 insertions(+)
create mode 100644
From: Daniele Alessandrelli
Add maintainers for the new Intel Movidius SoC code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4887e004cd26..3b919aa8b1bd
Daniele Alessandrelli (5):
arm64: Add config for Keem Bay SoC
dt-bindings: arm: Add Keem Bay bindings
MAINTAINERS: Add maintainers for Keem Bay SoC
arm64: dts: keembay: Add device tree for Keem Bay SoC
arm64: dts: keembay: Add device tree for Keem Bay EVM board
Paul Murphy (2):
dt
From: Daniele Alessandrelli
Add initial device tree for Intel Movidius SoC code-named Keem Bay.
This initial DT includes nodes for Cortex-A53 cores, UARTs, timers, GIC,
PSCI, PMU, and Keem Bay SCMI mailbox.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS
From: Daniele Alessandrelli
Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 1 +
arch/arm64/boot/dts
From: Daniele Alessandrelli
Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
arch/arm64/Kconfig.platforms | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64
From: Paul Murphy
Keem Bay SoC has a ARM trusted firmware-based secure monitor which acts
as the SCP for the purposes of power management over SCMI.
This driver implements the transport layer for SCMI to function.
Doclink:
From: Daniele Alessandrelli
Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.
Reviewed-by: Dinh Nguyen
Signed-off-by: Daniele Alessandrelli
---
.../devicetree/bindings/arm/keembay.yaml | 19 ++
include/dt-bindings/clock/keembay-clocks.h| 188
On Thu, 2020-05-28 at 13:22 +0200, Pavel Machek wrote:
> Hi!
>
> > > Agreed, this sounds like an incompatible extension of the boot
> > > protocol
> > > that we should otherwise not merge.
> > >
> > > However, there is also a lot of missing information here, and it
> > > is
> > > always
> > >
On Wed, 2020-05-27 at 20:59 +0200, Arnd Bergmann wrote:
> On Wed, May 27, 2020 at 7:43 PM Daniele Alessandrelli
> wrote:
> > On Wed, 2020-05-27 at 16:33 +0200, Arnd Bergmann wrote:
> > > On Wed, May 27, 2020 at 3:31 PM Alessandrelli, Daniele <
> > > danie
On Wed, 2020-05-27 at 16:33 +0200, Arnd Bergmann wrote:
> On Wed, May 27, 2020 at 3:31 PM Alessandrelli, Daniele
> wrote:
> > > > Alternatively, take that memory off the "memory available"
> > > > maps,
> > > > and only re-add it once
> > > > it is usable.
> > > >
> > > > Anything else is
Thanks for your feedback.
>
> First off, there is a "proper" way to send patches to the kernel
> community that Intel has that I do not think you are
> following. Please
> work with the Intel "Linux group" to do that first, as odds are they
> would have caught all of these issues beforehand
On Fri, 2020-05-01 at 09:09 +0200, gre...@linuxfoundation.org wrote:
> On Thu, Apr 30, 2020 at 07:49:36PM +, Alessandrelli, Daniele
> wrote:
> > This e-mail and any attachments may contain confidential material
> > for the sole
> > use of the intended recipient(s). Any review or distribution
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