The QSPI module can have an optional reset signals that will hold the
module in a reset state.
Signed-off-by: Dinh Nguyen
---
v6: no change
v5: document reset-names
v4: no change
v3: created base on review comments
v2: did not exist
v1: did not exist
---
Documentation/devicetree/bindings/mtd
The fixed dividers for the emac clocks should be 2 not 4.
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-s10.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 8281dfbf38c2..5bed36e12951 100644
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-s10.c | 6
On 6/21/19 6:23 AM, Masahiro Yamada wrote:
> With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller
> and NAND chips"), the Denali NAND controller driver migrated to the
> new controller/chip representation.
>
> Update DT for it.
>
> Signed-off-by: Masahiro Yamada
> ---
>
>
Hi Tudor,
On 6/22/19 5:21 AM, tudor.amba...@microchip.com wrote:
> Hi, Dinh,
>
> On 06/13/2019 02:31 PM, Dinh Nguyen wrote:
>> +struct reset_control *rstc;
>> +struct reset_control *rstc_ocp;
>
> I'll add these on a single line when applying. The patch is
The QSPI module can have an optional reset signals that will hold the
module in a reset state.
Signed-off-by: Dinh Nguyen
---
v6: no change
v5: document reset-names
v4: no change
v3: created base on review comments
v2: did not exist
v1: did not exist
---
Documentation/devicetree/bindings/mtd
-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
v6: no need to check for reset pointer in assert/deassert as the call to
assert/deassert is already doing the checking
v5: remove udelay(not needed) on tested hardware
group reset assert/deassert together
update commit message with reasoning
On 6/12/19 10:07 AM, tudor.amba...@microchip.com wrote:
>
>
> On 06/12/2019 05:37 PM, Dinh Nguyen wrote:
>> External E-Mail
>>
>>
>> Get the reset control properties for the QSPI controller and bring them
>> out of reset. Most will have just one reset
-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
v5: remove udelay(not needed) on tested hardware
group reset assert/deassert together
update commit message with reasoning for patch
v4: fix compile error
v3: return full error by using PTR_ERR(rtsc)
move reset control calls until after
The QSPI module can have an optional reset signals that will hold the
module in a reset state.
Signed-off-by: Dinh Nguyen
---
v5: document reset-names
v4: no change
v3: created base on review comments
v2: did not exist
v1: did not exist
---
Documentation/devicetree/bindings/mtd/cadence
On 6/6/19 3:26 AM, tudor.amba...@microchip.com wrote:
>
>
> On 05/08/2019 04:43 PM, Dinh Nguyen wrote:
>> Get the reset control properties for the QSPI controller and bring them
>> out of reset. Most will have just one reset bit, but there is an additional
>> OCP
onfig
> +++ b/arch/arm/configs/socfpga_defconfig
> @@ -44,7 +44,6 @@ CONFIG_PCI=y
> CONFIG_PCI_MSI=y
> CONFIG_PCIE_ALTERA=y
> CONFIG_PCIE_ALTERA_MSI=y
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> CONFIG_DEVTMPFS=y
> CONFIG_DEVTMPFS_MOUNT=y
> CONFIG_MTD=y
For (socfpga_defconfig):
Acked-by: Dinh Nguyen
/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
v4: fix compile error
v3: return full error by using PTR_ERR(rtsc)
move reset control calls until after the clock enables
use udelay(2) to be safe
Add optional OCP
The QSPI module can have an optional reset signals that will hold the
module in a reset state.
Signed-off-by: Dinh Nguyen
---
v4: no change
v3: created base on review comments
v2: did not exist
v1: did not exist
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4
1 file
On 5/3/19 4:15 AM, Simon Goldschmidt wrote:
> This changes system reboot for socfpga to issue a cold reboot by
> default instead of a warm reboot.
>
> Warm reboot can still be used by setting reboot_mode to
> REBOOT_WARM (e.g. via kernel command line 'reboot='), but this
> patch ensures cold
/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
v3: return full error by using PTR_ERR(rtsc)
move reset control calls until after the clock enables
use udelay(2) to be safe
Add optional OCP(Open Core Protocol
The QSPI module can have an optional reset signals that will hold the
module in a reset state.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/cadence
On 4/17/19 3:48 AM, tudor.amba...@microchip.com wrote:
> Hi, Dinh,
>
> On 04/09/2019 06:38 PM, Dinh Nguyen wrote:
>> Get the reset control for the QSPI controller and bring it out of reset.
>
> Is there a public datasheet where I can check this?
You can look at the re
<>;
> + interrupts = <14 4>,
> + <15 4>;
> + };
> + };
> };
> };
>
>
Acked-by: Dinh Nguyen
> +
> usb0-ecc@ff8c4000 {
> compatible = "altr,socfpga-s10-usb-ecc",
>"altr,socfpga-usb-ecc";
>
Acked-by: Dinh Nguyen
Get the reset control for the QSPI controller and bring it out of reset.
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
v2: use devm_reset_control_get_optional_exclusive
print an error message
return -EPROBE_DEFER
---
drivers/mtd/spi-nor/cadence-quadspi.c | 14
Add arch/arm64/boot/dts/intel/ under Dinh Nguyen.
Signed-off-by: Dinh Nguyen
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e17ebf70b548..8c90df31aaf0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2189,6 +2189,7 @@ F:arch/arm/mach
Get the reset control for the QSPI controller and bring it out of reset.
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
drivers/mtd/spi-nor/cadence-quadspi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi
+---
> 1 file changed, 13 insertions(+), 12 deletions(-)
>
Acked-by: Dinh Nguyen
Hi Richard,
On 2/19/19 9:24 AM, richard.g...@linux.intel.com wrote:
> From: Richard Gong
>
> Enable FPGA framework, Intel Stratix10 SoC FPGA manager, Stratix10
> service layer, and Altera Freeze Bridge drivers.
>
> Intel Stratix10 service layer driver was added with commit 7ca5ce896524
>
On 3/7/19 1:43 AM, Andrey Zhizhikin wrote:
> Hello Dinh,
>
> Just a short ping on this patch - do yo think you can accept this
> patch and have it merged? I'd like to know whether it is planned to be
> integrated, as it might be beneficial for a lot of socfpga users...
>
> Thanks a lot!
>
On 2/25/19 12:55 PM, Andrey Zhizhikin wrote:
> Hello Dinh,
>
> On Mon, Feb 25, 2019 at 5:35 PM Dinh Nguyen wrote:
>>
>> Hi Andrey,
>>
>> On 2/22/19 6:21 AM, Andrey Zhizhikin wrote:
>>> Enable CONFIG_LBDAF, which is required by ext4 fs. This option c
Hi Boris,
On 2/25/19 2:42 PM, Borislav Petkov wrote:
> On Mon, Feb 25, 2019 at 12:56:44PM -0600, thor.tha...@linux.intel.com wrote:
>> From: Thor Thayer
>>
>> Most users want EDAC support so make it the default.
>>
>> SOCFPGA SDRAM EDAC reporting was enabled by the parent EDAC
>> config
Hi Thor,
On 2/19/19 12:59 PM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Enable the different ECC blocks by default on Cyclone5
> and Arria10.
>
> Signed-off-by: Thor Thayer
> ---
> arch/arm/configs/socfpga_defconfig | 36 ++--
> 1 file
Hi Andrey,
On 2/22/19 6:21 AM, Andrey Zhizhikin wrote:
> Enable CONFIG_LBDAF, which is required by ext4 fs. This option could
> hanle both ext3 and ext4, and ex4 requires this option to be enabled,
> otherwise the filesystem is mounted RO mode.
>
> Signed-off-by: Andrey Zhizhikin
> ---
>
On 2/5/19 7:18 AM, Miquel Raynal wrote:
> Hi Dinh,
>
> Boris Brezillon wrote on Thu, 31 Jan 2019
> 18:26:44 +0100:
>
>> Hi Dinh,
>>
>> On Thu, 31 Jan 2019 11:24:16 -0600
>> Dinh Nguyen wrote:
>>
>>> On 1/28/19 4:20 AM, Miquel Raynal w
On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
> + Marek (as I really want to keep the dts in Linux and U-Boot in sync)
So can you wait until your patch in U-Boot is in?
> On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen wrote:
>>
>>
>>
>> On 1/29/19 2:08 PM, Sim
On 1/28/19 4:20 AM, Miquel Raynal wrote:
> Hi Dinh,
>
> Masahiro Yamada wrote on Wed, 16 Jan
> 2019 10:27:11 +0900:
>
>> (+CC Dinh Nguyen)
>>
>> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal
>> wrote:
>>>
>>> Hi Masahiro,
>&g
Hi Miquel,
Let me review this today.
Thanks,
Dinh
On 1/28/19 4:20 AM, Miquel Raynal wrote:
> Hi Dinh,
>
> Masahiro Yamada wrote on Wed, 16 Jan
> 2019 10:27:11 +0900:
>
>> (+CC Dinh Nguyen)
>>
>> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal
>> wrote
On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
> + Marek (as I really want to keep the dts in Linux and U-Boot in sync)
> On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen wrote:
>>
>>
>>
>> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
>>> From: Simon
On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
> From: Simon Goldschmidt
>
> The documentation for socfpga gen5 says the base address of the sdram
> controller is 0xffc2, while the current devicetree says it is at
> 0xffc25000.
>
> While this is not a problem for Linux, as it only accesses
On 1/29/19 2:05 PM, Simon Goldschmidt wrote:
> Am 29.01.2019 um 20:46 schrieb Simon Goldschmidt:
>> Add reset property for dma, can and sdram on socfpga gen5.
>>
>> Signed-off-by: Simon Goldschmidt
>
> That should have been:
> Signed-off-by: Simon Goldschmidt
>
Patch applied!
Thanks,
Dinh
On 1/23/19 11:01 AM, Alan Tull wrote:
> On Wed, Jan 23, 2019 at 10:42 AM Dinh Nguyen wrote:
>>
>>
>>
>> On 1/23/19 10:37 AM, Alan Tull wrote:
>>> On Wed, Jan 23, 2019 at 10:00 AM Greg KH wrote:
>>>
>>> Hi Greg,
>>>
On 1/23/19 10:37 AM, Alan Tull wrote:
> On Wed, Jan 23, 2019 at 10:00 AM Greg KH wrote:
>
> Hi Greg,
>
>>
>> On Wed, Jan 23, 2019 at 09:47:56AM -0600, richard.g...@linux.intel.com wrote:
>>> From: Richard Gong
>>>
>>> Add a Kconfig dependency to ensure Intel Stratix10 service layer driver
minor nit
On 1/14/19 4:33 PM, Alan Tull wrote:
> The Altera Freeze Bridge should not be restricted to ARCH_SOCFPGA
> since it can be used on other platforms such as Stratix10.
>
> Signed-off-by: Alan Tull
> ---
> drivers/fpga/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
On 1/4/19 1:23 PM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> Now there are device tree clocks for the ARM64 SMMU,
> add SMMU support to the Stratix10 Device Tree which
> includes adding the SMMU node and adding IOMMU stream
> ids to the SMMU peripherals.
>
> Signed-off-by:
On 1/8/19 12:43 AM, Manivannan Sadhasivam wrote:
> On Sat, Dec 15, 2018 at 08:31:50AM +0530, Manivannan Sadhasivam wrote:
>> Hello,
>>
>> This patchset adds board support for Chameleon96 board from Novetech
>> based on Intel Cyclone V SoC FPGA. This board is one of the Consumer
>> Edition
On 12/17/18 7:54 PM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2018-12-06 07:16:47)
>>
>>
>> On 12/5/18 9:55 AM, Stephen Boyd wrote:
>>> Quoting Dinh Nguyen (2018-12-05 07:17:41)
>>>> Hi Stephen,
>>>>
>>>> On 12/5/18 1:17 AM,
On 12/13/18 2:59 PM, dwest...@gmail.com wrote:
> From: Dalon Westergreen
>
> Add the stmmac ptp_ref clock as it is configured in the arria10 socdk.
> The stmmac driver defaults the ptp_ref clock to the main stmmac clock
> if the ptp_ref clock is not set in the devicetree. This is
abel
> ---
Acked-by: Dinh Nguyen
On 12/5/18 9:55 AM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2018-12-05 07:17:41)
>> Hi Stephen,
>>
>> On 12/5/18 1:17 AM, Stephen Boyd wrote:
>>> (Adding Dinh's korg email)
>>>
>>> I also wonder if this driver is even used anymore or maybe w
On 12/5/18 9:55 AM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2018-12-05 07:17:41)
>> Hi Stephen,
>>
>> On 12/5/18 1:17 AM, Stephen Boyd wrote:
>>> (Adding Dinh's korg email)
>>>
>>> I also wonder if this driver is even used anymore or maybe w
Hi Stephen,
On 12/5/18 1:17 AM, Stephen Boyd wrote:
> (Adding Dinh's korg email)
>
> I also wonder if this driver is even used anymore or maybe we can delete
> it?
>
The armv7 SoCFPGA platforms are using this driver.
Dinh
Hi Stephen,
On 12/5/18 1:17 AM, Stephen Boyd wrote:
> (Adding Dinh's korg email)
>
> I also wonder if this driver is even used anymore or maybe we can delete
> it?
>
The armv7 SoCFPGA platforms are using this driver.
Dinh
On 11/29/18 6:56 AM, Clément Péron wrote:
> unit-address does not have a leading "0x" (the number is assumed to be
> hexadecimal).
>
> Signed-off-by: Clément Péron
> ---
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied!
Thanks,
Dinh
On 11/29/18 6:56 AM, Clément Péron wrote:
> unit-address does not have a leading "0x" (the number is assumed to be
> hexadecimal).
>
> Signed-off-by: Clément Péron
> ---
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied!
Thanks,
Dinh
On 11/15/18 9:34 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Tue, 2018-11-13 at 12:50 -0600, Dinh Nguyen wrote:
>> @@ -120,7 +120,8 @@ static const struct reset_simple_devdata
>> reset_simple_active_low = {
>> };
>>
>> static const
On 11/15/18 9:34 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Tue, 2018-11-13 at 12:50 -0600, Dinh Nguyen wrote:
>> @@ -120,7 +120,8 @@ static const struct reset_simple_devdata
>> reset_simple_active_low = {
>> };
>>
>> static const
On 11/15/18 3:33 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> The standard reset-simple driver the uses the "altr,rst-mgr" binding is
>> not getting initialized
On 11/15/18 3:33 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> The standard reset-simple driver the uses the "altr,rst-mgr" binding is
>> not getting initialized
On 11/15/18 3:32 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
>> "altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
>>
>> Signed-off-by: Dinh Nguyen
>> ---
>> Documentatio
On 11/15/18 3:32 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-11-05 at 14:05 -0600, Dinh Nguyen wrote:
>> "altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
>>
>> Signed-off-by: Dinh Nguyen
>> ---
>> Documentatio
platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.
Signed-off-by: Dinh Nguyen
---
v4: remove !ARCH_STRATIX10 condition in Kconfig
clean up checkpatch.pl errors
v3: use "altr,stratix10-rst-mgr" for Stratix10
remove "altr,modrst-offset" from reset-simple
v
platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.
Signed-off-by: Dinh Nguyen
---
v4: remove !ARCH_STRATIX10 condition in Kconfig
clean up checkpatch.pl errors
v3: use "altr,stratix10-rst-mgr" for Stratix10
remove "altr,modrst-offset" from reset-simple
v
On 11/5/18 2:39 PM, Simon Goldschmidt wrote:
> In two of the gen5 socfpga devicetree files, there are some lines
> indented using spaces instead of tabs.
>
> Fix this by correctly indenting them with tabs.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfpga.dtsi
On 11/5/18 2:39 PM, Simon Goldschmidt wrote:
> In two of the gen5 socfpga devicetree files, there are some lines
> indented using spaces instead of tabs.
>
> Fix this by correctly indenting them with tabs.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfpga.dtsi
Hi Clément,
On 11/2/18 10:58 AM, Clément Péron wrote:
> Hi Dinh,
>
> Could you have a look at this serie ?
>
I've applied 1/3 and 3/3. I need to look over 2/3 to determine if that
patch is still valid. I think a better solution would be to set a clock
as critical so that it doesn't get gated.
Hi Clément,
On 11/2/18 10:58 AM, Clément Péron wrote:
> Hi Dinh,
>
> Could you have a look at this serie ?
>
I've applied 1/3 and 3/3. I need to look over 2/3 to determine if that
patch is still valid. I think a better solution would be to set a clock
as critical so that it doesn't get gated.
On 11/5/18 2:27 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> Resending this as requested by Dinh. It still applies on top of
> 4.20-rc1
On 11/5/18 2:27 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> Resending this as requested by Dinh. It still applies on top of
> 4.20-rc1
From: Dinh Nguyen
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.
We do not need this early reset driver for Stratix10
"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/socfpga-re
From: Dinh Nguyen
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.
We do not need this early reset driver for Stratix10
"altr,stratix10-rst-mgr" is used for the Stratix10 reset manager.
Signed-off-by: Dinh Nguyen
---
Documentation/devicetree/bindings/reset/socfpga-reset.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/socfpga-re
From: Dinh Nguyen
The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
From: Dinh Nguyen
The standard reset-simple driver the uses the "altr,rst-mgr" binding is
not getting initialized early enough in the boot process, so timers
that the kernel needs are still left in reset. Thus an early
reset driver was created. This early reset driver is only for the
Hi Simon,
On 10/23/2018 02:08 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfpga.dtsi| 16 +--
>
Hi Simon,
On 10/23/2018 02:08 PM, Simon Goldschmidt wrote:
> Follow the recent trend for the license description.
>
> This is also in an effort to fully sync the devicetrees with U-Boot.
>
> Signed-off-by: Simon Goldschmidt
> ---
> arch/arm/boot/dts/socfpga.dtsi| 16 +--
>
Hi
On 10/24/2018 09:11 AM, Clément Péron wrote:
> Hi,
>
> On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König
> wrote:
>>
>> On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>>>
>>>
>>> On 10/23/2018 09:44 AM, Clément Péron wrote:
&
Hi
On 10/24/2018 09:11 AM, Clément Péron wrote:
> Hi,
>
> On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König
> wrote:
>>
>> On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>>>
>>>
>>> On 10/23/2018 09:44 AM, Clément Péron wrote:
&
On 10/23/2018 09:44 AM, Clément Péron wrote:
> HI Dinh,
>
> On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
>>
>> Hi Clément,
>>
>> On 10/09/2018 06:28 AM, Clément Péron wrote:
>>> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>
On 10/23/2018 09:44 AM, Clément Péron wrote:
> HI Dinh,
>
> On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
>>
>> Hi Clément,
>>
>> On 10/09/2018 06:28 AM, Clément Péron wrote:
>>> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>
Hi Clément,
On 10/09/2018 06:28 AM, Clément Péron wrote:
> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>
> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for
> Cylone5.
>
I'm not sure the need for this patch. Are there any cyclone5 based
boards that
Hi Clément,
On 10/09/2018 06:28 AM, Clément Péron wrote:
> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>
> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for
> Cylone5.
>
I'm not sure the need for this patch. Are there any cyclone5 based
boards that
Hi Philipp
On 10/17/2018 09:37 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Thu, 2018-10-11 at 08:52 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in
>> reset-simple. The reset driver for the SoCFPGA platform needs to
>&
Hi Philipp
On 10/17/2018 09:37 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Thu, 2018-10-11 at 08:52 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in
>> reset-simple. The reset driver for the SoCFPGA platform needs to
>&
, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer.
Signed-off-by: Dinh Nguyen
---
v2: Do not build separate reset driver for STRATIX10
fix warning: symbol 'socfpga_reset_init' was not declared. Should
it be static?
---
arch/arm
, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer.
Signed-off-by: Dinh Nguyen
---
v2: Do not build separate reset driver for STRATIX10
fix warning: symbol 'socfpga_reset_init' was not declared. Should
it be static?
---
arch/arm
?
Thanks,
Dinh
On 10/05/2018 10:30 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Fri, 2018-10-05 at 10:17 -0500, Dinh Nguyen wrote:
> [...]
>>>> +static int a10_reset_init(struct device_node *np)
>>>> +{
>>>> + struct reset_simple_data *data;
>>&
?
Thanks,
Dinh
On 10/05/2018 10:30 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Fri, 2018-10-05 at 10:17 -0500, Dinh Nguyen wrote:
> [...]
>>>> +static int a10_reset_init(struct device_node *np)
>>>> +{
>>>> + struct reset_simple_data *data;
>>&
On 10/04/2018 04:53 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-09-17 at 09:50 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in
>> reset-simple.
>> The reset driver for the SoCFPGA platform needs to register e
On 10/04/2018 04:53 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Mon, 2018-09-17 at 09:50 -0500, Dinh Nguyen wrote:
>> Create a separate reset driver that uses the reset operations in
>> reset-simple.
>> The reset driver for the SoCFPGA platform needs to register e
r or do you just mention it? in the
> commit log ?
Sure, just keep the original Signed-off-by:.
Thanks,
Dinh
>
> Thanks,
> Clement
>
> From 6f7559407c1fcdb9b31c9493f0da79d614290e91 Mon Sep 17 00:00:00 2001
> From: Dinh Nguyen
> Date: Wed, 27 Feb 2013 18:29:14 -0600
>
r or do you just mention it? in the
> commit log ?
Sure, just keep the original Signed-off-by:.
Thanks,
Dinh
>
> Thanks,
> Clement
>
> From 6f7559407c1fcdb9b31c9493f0da79d614290e91 Mon Sep 17 00:00:00 2001
> From: Dinh Nguyen
> Date: Wed, 27 Feb 2013 18:29:14 -0600
>
On 09/27/2018 09:22 AM, Daniel Lezcano wrote:
> On 27/09/2018 15:52, Dinh Nguyen wrote:
>> Add code to retrieve the reset property from the dw-apb timers and if
>> the property is available, the safe operation is to assert the timer
>> into reset, and followed by a deasse
On 09/27/2018 09:22 AM, Daniel Lezcano wrote:
> On 27/09/2018 15:52, Dinh Nguyen wrote:
>> Add code to retrieve the reset property from the dw-apb timers and if
>> the property is available, the safe operation is to assert the timer
>> into reset, and followed by a deasse
On 09/26/2018 10:21 AM, Daniel Lezcano wrote:
> On 17/09/2018 16:52, Dinh Nguyen wrote:
>> Add code to retrieve the reset property for the dw-apb timers.
>
> The patch does more than that. Can you explain why the assert/deassert ?
Can I update the commit message to this?
Add c
On 09/26/2018 10:21 AM, Daniel Lezcano wrote:
> On 17/09/2018 16:52, Dinh Nguyen wrote:
>> Add code to retrieve the reset property for the dw-apb timers.
>
> The patch does more than that. Can you explain why the assert/deassert ?
Can I update the commit message to this?
Add c
Ping?
On 09/17/2018 09:52 AM, Dinh Nguyen wrote:
> Add code to retrieve the reset property for the dw-apb timers.
>
> Signed-off-by: Marek Vasut
> Signed-off-by: Dinh Nguyen
> ---
> drivers/clocksource/dw_apb_timer_of.c | 9 +
> 1 file changed, 9 insertio
Ping?
On 09/17/2018 09:52 AM, Dinh Nguyen wrote:
> Add code to retrieve the reset property for the dw-apb timers.
>
> Signed-off-by: Marek Vasut
> Signed-off-by: Dinh Nguyen
> ---
> drivers/clocksource/dw_apb_timer_of.c | 9 +
> 1 file changed, 9 insertio
Ping?
On 09/17/2018 09:50 AM, Dinh Nguyen wrote:
> Create a separate reset driver that uses the reset operations in reset-simple.
> The reset driver for the SoCFPGA platform needs to register early in order to
> be able bring online timers that needed early in the kernel bootup.
>
Ping?
On 09/17/2018 09:50 AM, Dinh Nguyen wrote:
> Create a separate reset driver that uses the reset operations in reset-simple.
> The reset driver for the SoCFPGA platform needs to register early in order to
> be able bring online timers that needed early in the kernel bootup.
>
Add code to retrieve the reset property for the dw-apb timers.
Signed-off-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource
Add code to retrieve the reset property for the dw-apb timers.
Signed-off-by: Marek Vasut
Signed-off-by: Dinh Nguyen
---
drivers/clocksource/dw_apb_timer_of.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clocksource/dw_apb_timer_of.c
b/drivers/clocksource
Create a separate reset driver that uses the reset operations in reset-simple.
The reset driver for the SoCFPGA platform needs to register early in order to
be able bring online timers that needed early in the kernel bootup.
Signed-off-by: Dinh Nguyen
---
arch/arm/mach-socfpga/socfpga.c | 4
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