On 05/13/2015 04:49 PM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> The Arria10 SOC uses a completely different SDRAM controller from the
> earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
> for the CycloneV/ArriaV SoCs in preparation for the Arria10
On 05/13/2015 04:49 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SDRAM and ECC system differs significantly from the
Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10
SoC.
1) IRQ handler needs to support SHARED IRQ
2)
On 05/13/2015 04:49 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation
On 5/13/15 4:49 PM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> The Arria10 SOC uses a completely different SDRAM controller from the
> earlier CycloneV and ArriaV SoCs. The memory size is calculated in
> the bootloader and passed via the device tree. Using this device
> tree
On 5/13/15 4:49 PM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. The memory size is calculated in
the bootloader and passed via the device tree.
On 05/05/2015 09:56 AM, Dinh Nguyen wrote:
> On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote:
>> 2015-05-05 4:52 GMT+09:00 Dinh Nguyen :
>>> On 05/04/2015 09:06 AM, Dinh Nguyen wrote:
>>>> +CC Olof
>>>>
>>>> On 5/4/15 8:50 AM, Krzysztof
On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote:
> 2015-05-05 4:52 GMT+09:00 Dinh Nguyen :
>> On 05/04/2015 09:06 AM, Dinh Nguyen wrote:
>>> +CC Olof
>>>
>>> On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
>>>> 2015-05-04 22:28 GMT+09:00 Dinh Nguyen
On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote:
2015-05-05 4:52 GMT+09:00 Dinh Nguyen dingu...@opensource.altera.com:
On 05/04/2015 09:06 AM, Dinh Nguyen wrote:
+CC Olof
On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
2015-05-04 22:28 GMT+09:00 Dinh Nguyen dingu...@opensource.altera.com
On 05/05/2015 09:56 AM, Dinh Nguyen wrote:
On 05/04/2015 10:55 PM, Krzysztof Kozlowski wrote:
2015-05-05 4:52 GMT+09:00 Dinh Nguyen dingu...@opensource.altera.com:
On 05/04/2015 09:06 AM, Dinh Nguyen wrote:
+CC Olof
On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
2015-05-04 22:28 GMT+09:00
On 05/04/2015 09:06 AM, Dinh Nguyen wrote:
> +CC Olof
>
> On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
>> 2015-05-04 22:28 GMT+09:00 Dinh Nguyen :
>>> Hi Krzystof,
>>>
>>> On 5/4/15 12:30 AM, Krzysztof Kozlowski wrote:
>>>> 2015-05-04 13:28
+CC Olof
On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
> 2015-05-04 22:28 GMT+09:00 Dinh Nguyen :
>> Hi Krzystof,
>>
>> On 5/4/15 12:30 AM, Krzysztof Kozlowski wrote:
>>> 2015-05-04 13:28 GMT+09:00 :
>>>> From: Dinh Nguyen
>>>>
>>&g
Hi Krzystof,
On 5/4/15 12:30 AM, Krzysztof Kozlowski wrote:
> 2015-05-04 13:28 GMT+09:00 :
>> From: Dinh Nguyen
>>
>> Turn on the clock to the PL330 DMA if there is a clock node provided.
>
> Why? There is no explanation in the patch for this important question -
Hi Krzystof,
On 5/4/15 12:30 AM, Krzysztof Kozlowski wrote:
2015-05-04 13:28 GMT+09:00 dingu...@opensource.altera.com:
From: Dinh Nguyen dingu...@opensource.altera.com
Turn on the clock to the PL330 DMA if there is a clock node provided.
Why? There is no explanation in the patch
+CC Olof
On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
2015-05-04 22:28 GMT+09:00 Dinh Nguyen dingu...@opensource.altera.com:
Hi Krzystof,
On 5/4/15 12:30 AM, Krzysztof Kozlowski wrote:
2015-05-04 13:28 GMT+09:00 dingu...@opensource.altera.com:
From: Dinh Nguyen dingu
On 05/04/2015 09:06 AM, Dinh Nguyen wrote:
+CC Olof
On 5/4/15 8:50 AM, Krzysztof Kozlowski wrote:
2015-05-04 22:28 GMT+09:00 Dinh Nguyen dingu...@opensource.altera.com:
Hi Krzystof,
On 5/4/15 12:30 AM, Krzysztof Kozlowski wrote:
2015-05-04 13:28 GMT+09:00 dingu...@opensource.altera.com
On 04/20/2015 11:24 AM, Vince Bridgers wrote:
> Add multicast-filter-bins and perfect-filter-entries configuration properties
> to the socfpga devicetree for the Arria 10 socfpga.
>
> Signed-off-by: Vince Bridgers
> ---
> This patch is based on patches
>
On 04/20/2015 11:24 AM, Vince Bridgers wrote:
Add multicast-filter-bins and perfect-filter-entries configuration properties
to the socfpga devicetree for the Arria 10 socfpga.
Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
This patch is based on patches
On Mon, Apr 20, 2015 at 10:45 AM, Joe Perches wrote:
> On Mon, 2015-04-20 at 10:37 -0500, Dinh Nguyen wrote:
>> On Thu, Apr 16, 2015 at 5:54 PM, Rob Herring wrote:
>> > +arm-soc
>> > On Thu, Apr 16, 2015 at 5:49 PM, Joe Perches wrote:
>> >> Change th
Hi Joe,
On Thu, Apr 16, 2015 at 5:54 PM, Rob Herring wrote:
> +arm-soc
>
> On Thu, Apr 16, 2015 at 5:49 PM, Joe Perches wrote:
>> Change the .dts file permissions from 755 to 644.
>>
>> Signed-off-by: Joe Perches
>
> ARM dts files go in thru arm-soc tree.
>
> Acked-by: Rob Herring
>
Thanks
Hi Joe,
On Thu, Apr 16, 2015 at 5:54 PM, Rob Herring robherri...@gmail.com wrote:
+arm-soc
On Thu, Apr 16, 2015 at 5:49 PM, Joe Perches j...@perches.com wrote:
Change the .dts file permissions from 755 to 644.
Signed-off-by: Joe Perches j...@perches.com
ARM dts files go in thru arm-soc
On Mon, Apr 20, 2015 at 10:45 AM, Joe Perches j...@perches.com wrote:
On Mon, 2015-04-20 at 10:37 -0500, Dinh Nguyen wrote:
On Thu, Apr 16, 2015 at 5:54 PM, Rob Herring robherri...@gmail.com wrote:
+arm-soc
On Thu, Apr 16, 2015 at 5:49 PM, Joe Perches j...@perches.com wrote:
Change
Hi Mike, Stephen,
On 04/02/2015 11:40 PM, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Hi,
>
> This patch series add the clock driver for the Arria10 platform. Although the
> Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5, the
> d
Hi Mike, Stephen,
On 04/02/2015 11:40 PM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hi,
This patch series add the clock driver for the Arria10 platform. Although the
Arria10 SoC's clock framework has some similarities the Cyclone/Arria 5
Hi Walter,
On 3/19/15 4:27 PM, Walter Lozano wrote:
> Hi Dinh,
>
> On Mon, Mar 16, 2015 at 10:10 AM, Walter Lozano
> wrote:
>> On Mon, Jan 5, 2015 at 6:21 AM, Steffen Trumtrar
>> wrote:
>>> Hi!
>>>
>>> On Wed, Dec 24, 2014 at 08:11:52PM -0300, Walter Lozano wrote:
This patch adds the DTS
Hi Walter,
On 3/19/15 4:27 PM, Walter Lozano wrote:
Hi Dinh,
On Mon, Mar 16, 2015 at 10:10 AM, Walter Lozano
wal...@vanguardiasur.com.ar wrote:
On Mon, Jan 5, 2015 at 6:21 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Wed, Dec 24, 2014 at 08:11:52PM -0300, Walter Lozano
Hi Rob,
On 2/19/15 12:13 PM, Rob Herring wrote:
> On Thu, Feb 19, 2015 at 11:06 AM, wrote:
>> From: Dinh Nguyen
>>
>> By not having bit 22 set in the PL310 Auxiliary Control register (shared
>> attribute override enable) has the side effect of transforming Normal
&g
On Wed, 11 Feb 2015, Vince Bridgers wrote:
> Correct SCU virtual mapping that was causing this BUG message:
>
> "BUG: mapping for 0xfffec000 at 0xfffec000 out of vmalloc space"
>
> Signed-off-by: Vince Bridgers
> ---
> arch/arm/mach-socfpga/core.h | 2 +-
> 1 file changed, 1 insertion(+), 1
Hi Rob,
On 2/19/15 12:13 PM, Rob Herring wrote:
On Thu, Feb 19, 2015 at 11:06 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
By not having bit 22 set in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect
On Wed, 11 Feb 2015, Vince Bridgers wrote:
Correct SCU virtual mapping that was causing this BUG message:
BUG: mapping for 0xfffec000 at 0xfffec000 out of vmalloc space
Signed-off-by: Vince Bridgers vbrid...@opensource.altera.com
---
arch/arm/mach-socfpga/core.h | 2 +-
1 file changed,
Hi Brian,
On Wed, Jan 14, 2015 at 9:38 AM, wrote:
> From: Graham Moore
>
> The Denali Controller IP does not support sub-page writes.
>
> Signed-off-by: Graham Moore
> Signed-off-by: Dinh Nguyen
> ---
> drivers/mtd/nand/denali.c | 3 +++
> 1 file changed, 3 i
Hi Brian,
On Wed, Jan 14, 2015 at 9:38 AM, dingu...@opensource.altera.com wrote:
From: Graham Moore grmo...@opensource.altera.com
The Denali Controller IP does not support sub-page writes.
Signed-off-by: Graham Moore grmo...@opensource.altera.com
Signed-off-by: Dinh Nguyen dingu
On 01/05/2015 09:02 PM, Paul Zimmerman wrote:
>> From: Kever Yang [mailto:kever.y...@rock-chips.com]
>> Sent: Monday, January 05, 2015 5:42 PM
>>
>> Hi Paul,
>>
>> I think you need this patch to fix the problem:
>>
>> usb: dwc2: resume root hub when device detect with suspend state
>>
On 01/05/2015 09:02 PM, Paul Zimmerman wrote:
From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent: Monday, January 05, 2015 5:42 PM
Hi Paul,
I think you need this patch to fix the problem:
usb: dwc2: resume root hub when device detect with suspend state
Hi Arnd,
On 11/21/14, 5:04 AM, Arnd Bergmann wrote:
> On Thursday 20 November 2014 23:04:40 dingu...@opensource.altera.com wrote:
>>
>> ---
>> arch/arm/mach-socfpga/socfpga.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/socfpga.c
>>
On 12/16/14, 12:33 AM, Ley Foon Tan wrote:
> On Tue, Dec 16, 2014 at 4:54 AM, Suman Anna wrote:
>> Hi Ley Foon,
>>
>> On 12/12/2014 08:38 AM, Dinh Nguyen wrote:
>>>
>>>
>>> On 12/12/14, 4:04 AM, Ley Foon Tan wrote:
>>>> The Altera
On 12/16/14, 12:33 AM, Ley Foon Tan wrote:
On Tue, Dec 16, 2014 at 4:54 AM, Suman Anna s-a...@ti.com wrote:
Hi Ley Foon,
On 12/12/2014 08:38 AM, Dinh Nguyen wrote:
On 12/12/14, 4:04 AM, Ley Foon Tan wrote:
The Altera mailbox allows for interprocessor communication. It supports
only one
Hi Arnd,
On 11/21/14, 5:04 AM, Arnd Bergmann wrote:
On Thursday 20 November 2014 23:04:40 dingu...@opensource.altera.com wrote:
---
arch/arm/mach-socfpga/socfpga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/socfpga.c
On 12/15/14, 12:22 AM, Ley Foon Tan wrote:
> On Fri, Dec 12, 2014 at 10:38 PM, Dinh Nguyen wrote:
>
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#includ
On 12/15/14, 12:22 AM, Ley Foon Tan wrote:
On Fri, Dec 12, 2014 at 10:38 PM, Dinh Nguyen dinh.li...@gmail.com wrote:
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/interrupt.h
+#include linux/io.h
On 12/12/14, 4:04 AM, Ley Foon Tan wrote:
> The Altera mailbox allows for interprocessor communication. It supports
> only one channel and work as either sender or receiver.
>
> Signed-off-by: Ley Foon Tan
> ---
> .../devicetree/bindings/mailbox/altera-mailbox.txt | 49 +++
>
On 12/12/14, 4:04 AM, Ley Foon Tan wrote:
The Altera mailbox allows for interprocessor communication. It supports
only one channel and work as either sender or receiver.
Signed-off-by: Ley Foon Tan lf...@altera.com
---
.../devicetree/bindings/mailbox/altera-mailbox.txt | 49 +++
Apologies for the noise, but it looks like Arnd has already send a patch
for this.
http://www.spinics.net/lists/netdev/msg306603.html
Dinh
On 12/1/14, 2:00 PM, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> The commit 571dcfde23712b ("stmmac: platform: fix
Apologies for the noise, but it looks like Arnd has already send a patch
for this.
http://www.spinics.net/lists/netdev/msg306603.html
Dinh
On 12/1/14, 2:00 PM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
The commit 571dcfde23712b (stmmac: platform
Hi Arnd,
On 11/21/14, 5:04 AM, Arnd Bergmann wrote:
> On Thursday 20 November 2014 23:04:40 dingu...@opensource.altera.com wrote:
>>
>> ---
>> arch/arm/mach-socfpga/socfpga.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/mach-socfpga/socfpga.c
>>
Hi Arnd,
On 11/21/14, 5:04 AM, Arnd Bergmann wrote:
On Thursday 20 November 2014 23:04:40 dingu...@opensource.altera.com wrote:
---
arch/arm/mach-socfpga/socfpga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/socfpga.c
d ECC EN defines.
> ---
> arch/arm/mach-socfpga/Makefile |1 +
> arch/arm/mach-socfpga/core.h|1 +
> arch/arm/mach-socfpga/ocram.c | 90
> +++
> arch/arm/mach-socfpga/socfpga.c |9
> 4 files changed, 101 insertions(+)
&
t; arch/arm/mach-socfpga/core.h |2 ++
> arch/arm/mach-socfpga/l2_cache.c | 41
> ++
> arch/arm/mach-socfpga/socfpga.c |4 +++-
> 4 files changed, 47 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-socfpga/l2_cach
/mach-socfpga/core.h |2 ++
arch/arm/mach-socfpga/l2_cache.c | 41
++
arch/arm/mach-socfpga/socfpga.c |4 +++-
4 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-socfpga/l2_cache.c
Acked-by: Dinh Nguyen dingu
-socfpga/ocram.c
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
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Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> This patch enables the ECC for On-Chip RAM on machine
> startup. The ECC has to be enabled before data is
> is stored in memory otherwise the ECC will fail on
> reads.
>
> Signed-off-by: Thor Thayer
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> This patch enables the ECC for L2 cache on machine
> startup. The ECC has to be enabled before data is
> is stored in memory otherwise the ECC will fail on
> reads.
>
> Signed-off-by: Thor Thayer
>
Hi Boris,
On 11/06/2014 10:31 AM, Borislav Petkov wrote:
> Hi Thor,
>
> On Tue, Nov 04, 2014 at 04:57:44PM -0600, Thor Thayer wrote:
>> We want to at least separate L2/OCRAM ECC from the SDRAM ECC because
>> 1) the SDRAM preparation can take almost 2 seconds on boot and some
>> customers need a
Hi Boris,
On 11/06/2014 10:31 AM, Borislav Petkov wrote:
Hi Thor,
On Tue, Nov 04, 2014 at 04:57:44PM -0600, Thor Thayer wrote:
We want to at least separate L2/OCRAM ECC from the SDRAM ECC because
1) the SDRAM preparation can take almost 2 seconds on boot and some
customers need a faster
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for L2 cache on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Hi Thor,
On 11/07/2014 10:54 AM, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
This patch enables the ECC for On-Chip RAM on machine
startup. The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.
Hi Philipp,
On 10/24/2014 10:53 AM, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> Populate the reset_status callback for SOCFPGA.
>
> Signed-off-by: Alan Tull
> Signed-off-by: Dinh Nguyen
> ---
> drivers/reset/reset-socfpga.c | 18
On 10/31/2014 02:31 PM, Dinh Nguyen wrote:
> On 10/31/2014 12:42 PM, Felipe Balbi wrote:
>> Hi,
>>
>> On Fri, Oct 31, 2014 at 10:20:06AM -0500, Dinh Nguyen wrote:
>>>>> @@ -339,7 +339,8 @@ static void dwc2_handle_wakeup_detected_
On 10/31/2014 12:42 PM, Felipe Balbi wrote:
> Hi,
>
> On Fri, Oct 31, 2014 at 10:20:06AM -0500, Dinh Nguyen wrote:
>>>> @@ -339,7 +339,8 @@ static void dwc2_handle_wakeup_detected_intr(struct
>>>> dwc2_hsotg *hsotg)
>>>>}
>>>>
On 10/30/2014 09:04 AM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Oct 28, 2014 at 06:25:47PM -0500, dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>>
>> Since the dwc2 hcd driver is currently not looking for a clock node during
>> init, we shoul
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 08:54 AM, Felipe Balbi wrote:
> On Tue, Oct 28, 2014 at 06:25:42PM -0500,
> dingu...@opensource.altera.com wrote:
>> From: Dinh Nguyen
>>
>> Adds the gadget data structure and appropriate data structure
&
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 09:01 AM, Felipe Balbi wrote:
> On Tue, Oct 28, 2014 at 06:25:46PM -0500,
> dingu...@opensource.altera.com wrote:
>> From: Dinh Nguyen
>>
>> Update the dwc2 wakeup and suspend interrupt functions to use
&g
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 09:00 AM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Oct 28, 2014 at 06:25:45PM -0500,
> dingu...@opensource.altera.com wrote:
>> From: Dinh Nguyen
>>
>> Make dwc2_handle_common_intr call the gadget interr
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 08:57 AM, Felipe Balbi wrote:
> On Tue, Oct 28, 2014 at 06:25:43PM -0500,
> dingu...@opensource.altera.com wrote:
>> From: Dinh Nguyen
>>
>> This patch will aggregate the probing of gadget/hcd driver into
&
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 08:57 AM, Felipe Balbi wrote:
On Tue, Oct 28, 2014 at 06:25:43PM -0500,
dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
This patch will aggregate the probing of gadget/hcd driver
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 09:00 AM, Felipe Balbi wrote:
Hi,
On Tue, Oct 28, 2014 at 06:25:45PM -0500,
dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Make dwc2_handle_common_intr call the gadget interrupt function
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 09:01 AM, Felipe Balbi wrote:
On Tue, Oct 28, 2014 at 06:25:46PM -0500,
dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Update the dwc2 wakeup and suspend interrupt functions to use
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 10/30/2014 08:54 AM, Felipe Balbi wrote:
On Tue, Oct 28, 2014 at 06:25:42PM -0500,
dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Adds the gadget data structure and appropriate data structure
pointers
On 10/30/2014 09:04 AM, Felipe Balbi wrote:
Hi,
On Tue, Oct 28, 2014 at 06:25:47PM -0500, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Since the dwc2 hcd driver is currently not looking for a clock node during
init, we should not completely fail
On 10/31/2014 12:42 PM, Felipe Balbi wrote:
Hi,
On Fri, Oct 31, 2014 at 10:20:06AM -0500, Dinh Nguyen wrote:
@@ -339,7 +339,8 @@ static void dwc2_handle_wakeup_detected_intr(struct
dwc2_hsotg *hsotg)
}
/* Change to L0 state */
hsotg-lx_state = DWC2_L0
On 10/31/2014 02:31 PM, Dinh Nguyen wrote:
On 10/31/2014 12:42 PM, Felipe Balbi wrote:
Hi,
On Fri, Oct 31, 2014 at 10:20:06AM -0500, Dinh Nguyen wrote:
@@ -339,7 +339,8 @@ static void dwc2_handle_wakeup_detected_intr(struct
dwc2_hsotg *hsotg)
}
/* Change to L0 state
Hi Philipp,
On 10/24/2014 10:53 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Populate the reset_status callback for SOCFPGA.
Signed-off-by: Alan Tull at...@opensource.altera.com
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
tionality, move
>> the call the host portion for the DWC2 driver.
>>
>> Signed-off-by: Dinh Nguyen
>> ---
>> drivers/usb/dwc2/hcd.c | 3 +++
>> drivers/usb/dwc2/platform.c | 3 ---
>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> di
in the following build error
when (!USB USB_GADGET) condition is met.
ERROR: usb_disabled [drivers/usb/dwc2/dwc2_platform.ko] undefined!
Since usb_disabled() is mostly used to disable USB host functionality, move
the call the host portion for the DWC2 driver.
Signed-off-by: Dinh Nguyen dingu
On 10/24/2014 07:07 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> On Thu, Oct 23, 2014 at 10:01:45AM -0500, Dinh Nguyen wrote:
>> Hi Philipp,
>>
>> On 10/10/2014 10:21 AM, dingu...@opensource.altera.com wrote:
>>> From: Dinh Nguyen
>>>
>>> Th
On 10/24/2014 07:07 AM, Philipp Zabel wrote:
Hi Dinh,
On Thu, Oct 23, 2014 at 10:01:45AM -0500, Dinh Nguyen wrote:
Hi Philipp,
On 10/10/2014 10:21 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
There are cases where a system will want to read
On 10/23/2014 01:28 PM, Paul Zimmerman wrote:
>> From: Bartlomiej Zolnierkiewicz [mailto:b.zolnier...@samsung.com]
>> Sent: Wednesday, October 22, 2014 5:26 AM
>>
>> On Monday, October 20, 2014 01:52:06 PM dingu...@opensource.altera.com wrote:
>>> F
On 10/22/2014 03:27 PM, Paul Bolle wrote:
> On Tue, 2014-10-21 at 15:47 -0500, Dinh Nguyen wrote:
>> On 10/20/2014 02:42 PM, Paul Bolle wrote:
>>> (Side note: drivers/usb/dwc2/Kconfig is sourced (in drivers/usb/Kconfig)
>>> even if USB is _not_ set. But USB_DCW
Hi Philipp,
On 10/10/2014 10:21 AM, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen
>
> There are cases where a system will want to read a reset status bit before
> doing any other toggling. Add a reset_control_status helper function to the
> reset controller API.
er/state
>
> Signed-off-by: Alan Tull
> Cc: Pavel Machek
> Cc: Arnd Bergmann
> Cc: Dinh Nguyen
> Cc: Steffen Trumtrar
> ---
> v2: use Generic on-chip SRAM driver to allocate ocram
> rm fncpy_align since generic allocator handles alignment
> check __arm_ioremap_e
at...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Steffen Trumtrar s.trumt...@pengutronix.de
---
v2: use Generic on-chip SRAM driver to allocate ocram
rm fncpy_align since generic allocator handles alignment
Hi Philipp,
On 10/10/2014 10:21 AM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
There are cases where a system will want to read a reset status bit before
doing any other toggling. Add a reset_control_status helper function to the
reset controller
On 10/22/2014 03:27 PM, Paul Bolle wrote:
On Tue, 2014-10-21 at 15:47 -0500, Dinh Nguyen wrote:
On 10/20/2014 02:42 PM, Paul Bolle wrote:
(Side note: drivers/usb/dwc2/Kconfig is sourced (in drivers/usb/Kconfig)
even if USB is _not_ set. But USB_DCW2 still depends on USB. Why
On 10/23/2014 01:28 PM, Paul Zimmerman wrote:
From: Bartlomiej Zolnierkiewicz [mailto:b.zolnier...@samsung.com]
Sent: Wednesday, October 22, 2014 5:26 AM
On Monday, October 20, 2014 01:52:06 PM dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
config
On 10/20/2014 02:42 PM, Paul Bolle wrote:
> dingu...@opensource.altera.com schreef op ma 20-10-2014 om 13:52
> [-0500]:
>> From: Dinh Nguyen
>>
>> Update DWC2 kconfig and makefile to support dual-role mode. The platform
>> file will always get compiled for
On 10/20/2014 02:42 PM, Paul Bolle wrote:
dingu...@opensource.altera.com schreef op ma 20-10-2014 om 13:52
[-0500]:
From: Dinh Nguyen dingu...@opensource.altera.com
Update DWC2 kconfig and makefile to support dual-role mode. The platform
file will always get compiled for the case where
On Tue, 14 Oct 2014, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Patch 1: socfpga: hotplug: put cpu1 in wfi
> Use WFI when putting CPU1 to sleep. Don't hold CPU1 in reset
> since that results in increased power consumption. Only
> briefly reset CPU1.
>
> Patch 2: socfpga:
On 10/15/14, 5:02 AM, Steffen Trumtrar wrote:
> Hi!
>
> On Tue, Oct 14, 2014 at 01:45:29PM -0500, atull wrote:
>> The FPGA bridge driver that I submitted last year handled the following
>> things:
>> * The bridges might have been brought out of reset in the bootloader. Some
>>of the
On 10/15/14, 5:02 AM, Steffen Trumtrar wrote:
Hi!
On Tue, Oct 14, 2014 at 01:45:29PM -0500, atull wrote:
The FPGA bridge driver that I submitted last year handled the following
things:
* The bridges might have been brought out of reset in the bootloader. Some
of the bridges have
On Tue, 14 Oct 2014, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
Patch 1: socfpga: hotplug: put cpu1 in wfi
Use WFI when putting CPU1 to sleep. Don't hold CPU1 in reset
since that results in increased power consumption. Only
briefly reset CPU1.
Hi Philipp,
On 10/9/14, 3:44 AM, Philipp Zabel wrote:
> Hi Dinh,
>
> thank you for the patch. Just two small issues below:
>
> Am Mittwoch, den 08.10.2014, 17:45 -0500 schrieb
> dingu...@opensource.altera.com:
> [...]
>> @@ -126,6 +126,19 @@ int reset_control_deassert(struct reset_control
Hi Philipp,
On 10/9/14, 4:03 AM, Philipp Zabel wrote:
> Am Mittwoch, den 08.10.2014, 21:44 -0500 schrieb
> dingu...@opensource.altera.com:
>> From: Dinh Nguyen
>>
>> There are certain drivers that are required to get loaded very early using
>> arch_initcal
Hi Philipp,
On 10/9/14, 4:03 AM, Philipp Zabel wrote:
Am Mittwoch, den 08.10.2014, 21:44 -0500 schrieb
dingu...@opensource.altera.com:
From: Dinh Nguyen dingu...@opensource.altera.com
There are certain drivers that are required to get loaded very early using
arch_initcall. An example
Hi Philipp,
On 10/9/14, 3:44 AM, Philipp Zabel wrote:
Hi Dinh,
thank you for the patch. Just two small issues below:
Am Mittwoch, den 08.10.2014, 17:45 -0500 schrieb
dingu...@opensource.altera.com:
[...]
@@ -126,6 +126,19 @@ int reset_control_deassert(struct reset_control *rstc)
On 10/8/14, 8:02 AM, Chen-Yu Tsai wrote:
> The A80 Optimus Board is was launched with the Allwinner A80 SoC.
> It was jointly developed by Allwinner and Merrii.
>
> This board has a UART port, a JTAG connector, USB host ports, a USB
> 3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND
On 10/8/14, 8:02 AM, Chen-Yu Tsai wrote:
The A80 Optimus Board is was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.
This board has a UART port, a JTAG connector, USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 8G NAND
On 10/07/2014 07:10 AM, Pavel Machek wrote:
> Hi!
>
> After some testing:
>
> u-boot-2013.01.01 + linux-3.17 => ethernet does not work
> (unless ethernet is used in u-boot, for example
> using ping)
> u-boot-marex-20140920a + linux-3.17 => working
On 10/07/2014 07:10 AM, Pavel Machek wrote:
Hi!
After some testing:
u-boot-2013.01.01 + linux-3.17 = ethernet does not work
(unless ethernet is used in u-boot, for example
using ping)
u-boot-marex-20140920a + linux-3.17 = working ethernet
One
On 10/1/14, 6:16 PM, Pavel Machek wrote:
> On Wed 2014-10-01 11:07:18, Dinh Nguyen wrote:
>>
>>
>> On 10/1/14, 10:04 AM, Pavel Machek wrote:
>>> Hi!
>>>
>>>>>> +__raw_writel(RSTMGR_MPUMODRST_CPU1,
>>
On 10/1/14, 6:16 PM, Pavel Machek wrote:
On Wed 2014-10-01 11:07:18, Dinh Nguyen wrote:
On 10/1/14, 10:04 AM, Pavel Machek wrote:
Hi!
+__raw_writel(RSTMGR_MPUMODRST_CPU1,
+ rst_manager_base_addr + 0x10);
Would it be possible to copy reset
On 10/1/14, 10:04 AM, Pavel Machek wrote:
> Hi!
>
+ __raw_writel(RSTMGR_MPUMODRST_CPU1,
+ rst_manager_base_addr + 0x10);
>>>
>>> Would it be possible to copy reset manager description struct from
>>> u-boot and use it here, instead of raw offset?
>>
>> I
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