From: Dongjiu Geng
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon
From: Dongjiu Geng
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
Reviewed-by: Rob Herring
---
.../clock/hisilicon,hi3559av100-clock.yaml | 59
include/dt-bindings/clock/hi3559av100-clock.h | 165 +
2 files changed
This patchset is separated from this series:
https://lore.kernel.org/patchwork/cover/1353321/
v7->v8:
Mainly address Stephen's comments
1. Add const for some function and variables
2. Remove the useless function and variables
3. Add a define for a mask width
Dongjiu Geng (2):
dt-
On 2021/1/12 18:40, Vinod Koul wrote:
> On 15-12-20, 11:09, Dongjiu Geng wrote:
>> v6->v7:
>> 1. rename hisi,misc-control to hisi,misc-control to hisilicon,misc-control
>>
>> v5->v6:
>> 1. Drop #size-cells and #address-cell in the hisilicon,hi3559av100-cloc
On 2020/12/22 2:54, Rob Herring wrote:
> On Tue, 15 Dec 2020 11:09:44 +0000, Dongjiu Geng wrote:
>> Add DT bindings documentation for hi3559a SoC clock.
>>
>> Signed-off-by: Dongjiu Geng
>> ---
>> .../clock/hisilicon,hi3559av100-clock.yaml| 59
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
On 2020/12/12 4:57, Rob Herring wrote:
> On Sat, 12 Dec 2020 13:11:14 +0000, Dongjiu Geng wrote:
>> The Hiedma Controller v310 Provides eight DMA channels, each
>> channel can be configured for one-way transfer. The data can
>> be transferred in 8-bit, 16-bit, 32-bit,
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
. fix the 'make dt_binding_check' issues in 'Enable HiSilicon Hiedma
Controller' patchset
v2->v3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (4):
dt-bindings: Document the hi3559a clock bindings
Signed-off-by: Dongjiu Geng
---
drivers/dma/Kconfig | 14 +
drivers/dma/Makefile |1 +
drivers/dma/hiedmacv310.c | 1442 +
drivers/dma/hiedmacv310.h | 136
4 files changed, 1593 insertions(+)
create mode 100644 drivers/dma/hiedmacv310.c
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
Signed-off-by: Dongjiu Geng
---
drivers/dma/Kconfig | 14 +
drivers/dma/Makefile |1 +
drivers/dma/hiedmacv310.c | 1442 +
drivers/dma/hiedmacv310.h | 136
4 files changed, 1593 insertions(+)
create mode 100644 drivers/dma/hiedmacv310.c
Controller' patchset
v2->v3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (4):
dt-bindings: Document the hi3559a clock bindings
clk: hisilicon: Add clock driver for hi3559A SoC
dt: bindings: dma: Add DT bindings f
Controller' patchset
v2->v3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (4):
dt-bindings: Document the hi3559a clock bindings
clk: hisilicon: Add clock driver for hi3559A SoC
dt: bindings: dma: Add DT bindings f
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
Signed-off-by: Dongjiu Geng
---
drivers/dma/Kconfig | 14 +
drivers/dma/Makefile |1 +
drivers/dma/hiedmacv310.c | 1442 +
drivers/dma/hiedmacv310.h | 136
4 files changed, 1593 insertions(+)
create mode 100644 drivers/dma/hiedmacv310.c
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 59 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 224 insertions(+)
create mode 100644
Documentation
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
Signed-off-by: Dongjiu Geng
---
drivers/dma/Kconfig | 14 +
drivers/dma/Makefile |1 +
drivers/dma/hiedmacv310.c | 1442 +
drivers/dma/hiedmacv310.h | 136
4 files changed, 1593 insertions(+)
create mode 100644 drivers/dma/hiedmacv310.c
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
ilicon Hiedma
Controller' patchset
v2->v3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (4):
dt-bindings: Document the hi3559a clock bindings
clk: hisilicon: Add clock driver for hi3559A SoC
dt: bindings:
On 2020/12/1 6:07, Rob Herring wrote:
> On Thu, Nov 19, 2020 at 08:01:26PM +0000, Dongjiu Geng wrote:
>> Add DT bindings documentation for hi3559a SoC clock.
>>
>> Signed-off-by: Dongjiu Geng
>> ---
>> .../clock/hisilicon,hi3559av100-clock.yaml| 66
ping, sorry for the noise.
On 2020/11/20 4:01, Dongjiu Geng wrote:
> v4->v5:
> 1. change the patch author mail name
>
> v3->v4:
> 1. fix the 'make dt_binding_check' issues.
> 2. Combine the 'Enable HiSilicon Hiedma Controller' series p
issues in hisi_clk_init().
Fixes: 75af25f581b1 ("clk: hisi: remove static variable")
Fixes: 62ac983b6141 ("clk: hisilicon: add hi3620_mmc_clks")
Cc: Markus Elfring
Signed-off-by: Dongjiu Geng
---
v3->v4:
1. omit a blank in hisi_register_clk_mmc()
2. Further need to do:
con
On 2020/11/19 22:40, Markus Elfring wrote:
>> How about we adjust such a function call in another series patches?
>
> You can try to offer desirable changes also in a corresponding patch series
> as usual.
sure, ok
>
> Regards,
> Markus
> .
>
On 2020/11/19 17:07, Markus Elfring wrote:
>> Refine hi3620_mmc_clk_init() to use of_clk_add_hw_provider()
>> instead of of_clk_add_provider(), …
>
> …
>> +++ b/drivers/clk/hisilicon/clk-hi3620.c
> …
>> @@ -439,17 +440,22 @@ static struct clk *hisi_register_clk_mmc(struct
>> hisi_mmc_clock *mmc_
On 2020/11/16 23:27, Rob Herring wrote:
> On Sat, 14 Nov 2020 00:34:39 +0000, Dongjiu Geng wrote:
>> The Hiedma Controller v310 Provides eight DMA channels, each
>> channel can be configured for one-way transfer. The data can
>> be transferred in 8-bit, 16-bit, 32-bit,
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
Signed-off-by: Dongjiu Geng
---
drivers/dma/Kconfig | 14 +
drivers/dma/Makefile |1 +
drivers/dma/hiedmacv310.c | 1441 +
drivers/dma/hiedmacv310.h | 136
4 files changed, 1592 insertions(+)
create mode 100644 drivers/dma/hiedmacv310.c
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 66 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 231 insertions(+)
create mode 100644
Documentation
ntroller' patchset
v2->v3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (4):
dt-bindings: Document the hi3559a clock bindings
clk: hisilicon: Add clock driver for hi3559A SoC
dt: bindings: dma: Add DT bindings for
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 66 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 231 insertions(+)
create mode 100644
Documentation
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
Signed-off-by: Dongjiu Geng
---
drivers/dma/Kconfig | 14 +
drivers/dma/Makefile |1 +
drivers/dma/hiedmacv310.c | 1441 +
drivers/dma/hiedmacv310.h | 136
4 files changed, 1592 insertions(+)
create mode 100644 drivers/dma/hiedmacv310.c
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (4):
dt-bindings: Document the hi3559a clock bindings
clk: hisilicon: Add clock driver for hi3559A SoC
dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controlle
ping, sorry for this noise.
On 2020/11/13 3:22, Dongjiu Geng wrote:
> Refine hi3620_mmc_clk_init() to use of_clk_add_hw_provider()
> instead of of_clk_add_provider(), the called function hisi_register_clk_mmc()
> returns 'clk_hw *' to adapt to this change. Also free memory
On 2020/11/16 23:02, Rob Herring wrote:
> On Sat, 14 Nov 2020 00:22:36 +0000, Dongjiu Geng wrote:
>> Add DT bindings documentation for hi3559a SoC clock.
>>
>> Signed-off-by: Dongjiu Geng
>> ---
>> .../clock/hisilicon,hi3559av100-clock.yaml| 65
Hisilicon EDMA Controller(EDMAC) directly transfers data
between a memory and a peripheral, between peripherals, or
between memories. This avoids the CPU intervention and reduces
the interrupt handling overhead of the CPU, this driver enables
this controller.
Signed-off-by: Dongjiu Geng
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng
---
.../bindings/dma
Hisilicon EDMA Controller(EDMAC) directly transfers data
between a memory and a peripheral, between peripherals, or
between memories. This avoids the CPU intervention and reduces
the interrupt handling overhead of the CPU, this driver enables
this controller.
Signed-off-by: Dongjiu Geng
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/clk-hi3559a.c | 865
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../clock/hisilicon,hi3559av100-clock.yaml| 65 +++
include/dt-bindings/clock/hi3559av100-clock.h | 165 ++
2 files changed, 230 insertions(+)
create mode 100644
Documentation
v2->v3:
1. change dt-bindings documents from txt to yaml format.
2. Add SHUB clock to access the devices of m7
Dongjiu Geng (2):
dt-bindings: Document the hi3559a clock bindings
clk: hisilicon: Add clock driver for hi3559A SoC
.../clock/hisilicon,hi3559av100-clock.yaml| 65 ++
driv
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile| 1 +
drivers/clk/hisilicon
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../bindings/clock/hi3559av100-clock.txt | 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/hi3559av100-clock.txt
diff --git a
Add clock drivers for hi3559A SoC, this driver
controls the SoC registers to supply different
clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile| 1 +
drivers/clk/hisilicon
Add DT bindings documentation for hi3559a SoC clock.
Signed-off-by: Dongjiu Geng
---
.../bindings/clock/hi3559av100-clock.txt | 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/hi3559av100-clock.txt
diff --git a
add Markus
On 2020/11/13 3:22, Dongjiu Geng wrote:
> Refine hi3620_mmc_clk_init() to use of_clk_add_hw_provider()
> instead of of_clk_add_provider(), the called function hisi_register_clk_mmc()
> returns 'clk_hw *' to adapt to this change. Also free memory mapping and
>
issues in hisi_clk_init().
Fixes: 75af25f581b1 ("clk: hisi: remove static variable")
Fixes: 62ac983b6141 ("clk: hisilicon: add hi3620_mmc_clks")
Cc: Markus Elfring
Signed-off-by: Dongjiu Geng
---
v2->v3:
1. Refind hi3620_mmc_clk_init() and hisi_register_clk_mmc() in order to u
issues in hisi_clk_init().
Fixes: 75af25f581b1 ("clk: hisi: remove static variable")
Fixes: 62ac983b6141 ("clk: hisilicon: add hi3620_mmc_clks")
Cc: Markus Elfring
Signed-off-by: Dongjiu Geng
---
v2->v3:
1. Refind hi3620_mmc_clk_init() and hisi_register_clk_mmc() in order to u
On 2020/11/12 6:23, Rob Herring wrote:
> On Mon, Nov 09, 2020 at 08:28:38PM +0000, Dongjiu Geng wrote:
>> Add clock drivers for hi3559A SoC, this driver controls the SoC
>> registers to supply different clocks to different IPs in the SoC.
>>
>> Signed-off-by: Dongjiu G
On 2020/11/10 1:54, Markus Elfring wrote:
> …
>> +++ b/drivers/clk/hisilicon/clk-hi3620.c
> …
>> @@ -478,6 +478,10 @@ static void __init hi3620_mmc_clk_init(struct
>> device_node *node)
>>
>> clk_data->clk_num = num;
>> of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
>> +
Add clock drivers for hi3559A SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile| 1 +
drivers/clk/hisilicon
add Markus
On 2020/11/10 2:09, Dongjiu Geng wrote:
> Free memory mapping and free clk_data, if clock initialization
> is not successful.
>
> Fixes: 75af25f581b1 ("clk: hisi: remove static variable")
> Fixes: 62ac983b6141 ("clk: hisilicon: add hi3620_mmc_clks&q
On 2020/11/8 21:55, Markus Elfring wrote:
>> When return errors, …
>
> I would find an other wording more appropriate for this change description.
>
>
>> …, so fix this issue.
>
> I suggest to replace this information by an other imperative wording
> and the tag “Fixes”.
OK, done， I have submi
Free memory mapping and free clk_data, if clock initialization
is not successful.
Fixes: 75af25f581b1 ("clk: hisi: remove static variable")
Fixes: 62ac983b6141 ("clk: hisilicon: add hi3620_mmc_clks")
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/clk-hi3620.c | 8 +
When return errors, the clock driver does not unmap
the mapped memory, so fix this issue.
Signed-off-by: Dongjiu Geng
---
drivers/clk/hisilicon/clk-hi3620.c | 8 ++--
drivers/clk/hisilicon/clk.c| 5 -
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/clk
On 2020/10/31 17:55, Marc Zyngier wrote:
> Dongjiu,
>
> On Sat, 31 Oct 2020 02:19:19 +,
> Dongjiu Geng wrote:
>>
>> Hi Marc,
>> Sorry to disturb you, Currently the LPI number is not fixed for the
>> device. The LPI number is dynamically allocated start f
On 2020/10/31 17:58, Marc Zyngier wrote:
> On Sat, 31 Oct 2020 03:10:24 +,
> Dongjiu Geng wrote:
>
> [...]
>
>> Sorry for the noise, Because Marc rarely uses the ARM email address,
>> so I replace to use Marc's kernel.org address instead of ARM emai
On 2020/10/31 10:59, Thomas Gleixner wrote:
> On Sat, Oct 31 2020 at 10:19, Dongjiu Geng wrote:
>> Hi Marc,
>> Sorry to disturb you, Currently the LPI number is not fixed for
>> the device. The LPI number is dynamically allocated start from 8092.
>> For two OS w
Hi Marc,
Sorry to disturb you, Currently the LPI number is not fixed for the device.
The LPI number is dynamically allocated start from 8092.
For two OS which shares the ITS, One OS needs to configure the device
interrupt required by another OS, and the other OS uses a fixed interrupt
ID t
Hi Marc,
Sorry to disturb you, Currently the LPI number is not fixed for the device.
The LPI number is dynamically allocated start from 8092.
For two OS which shares the ITS, One OS needs to configure the device interrupt
required by another OS, and the other OS uses a fixed interrupt
ID to re
On 2020/9/1 15:48, Marc Zyngier wrote:
> Hi Dongjiu,
>
> In the future, please use my kernel.org address, as I don't work
> for ARM anymore, and would have missed this email if I wasn't pointed
> to it.
>
> On 2020-08-14 18:10, Dongjiu Geng wrote:
>> Hi Ma
s/kernel/debug/tracing/events/sched/sched_leave_running_time/filter
echo 1 >
/sys/kernel/debug/tracing/events/sched/sched_leave_running_time/enable
Signed-off-by: Dongjiu Geng
---
include/linux/sched.h| 7
include/trace/events/sched.h | 66 +
ents/sched/sched_leave_running_time/filter
echo 1 >
/sys/kernel/debug/tracing/events/sched/sched_leave_running_time/enable
Signed-off-by: Dongjiu Geng
---
include/linux/sched.h| 7
include/trace/events/sched.h | 66
kernel/sched/core.c
Hi Marc,
In the Linux kernel, we can not adjust the interrupt Priority, For all the
interrupts, the interrupt Priority are fixed to 0xa0.
In some scenarios, it needs to change the Priority. so I want to upstream a
serie patch to support to change the Priority through procfs. do you agree I
u
When user space do memory recovery, it will check whether KVM and
guest support the error recovery, only when both of them support,
user space will do the error recovery. This patch exports this
capability of KVM to user space.
Cc: Peter Maydell
Signed-off-by: Dongjiu Geng
---
User space needs
When user space do memory recovery, it will check whether KVM and
guest support the error recovery, only when both of them support,
user space will do the error recovery. This patch exports this
capability of KVM to user space.
Cc: Peter Maydell
Signed-off-by: Dongjiu Geng
---
User space needs
sages.
Dongjiu Geng (2):
arm/arm64: KVM: rename function kvm_arch_dev_ioctl_check_extension()
arm/arm64: KVM: enable 32 bits kvm vcpu events support
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/kvm/reset.c| 5 ++---
virt/kvm/arm/
Rename kvm_arch_dev_ioctl_check_extension() to
kvm_arch_vm_ioctl_check_extension(), because it does
not have any relationship with device.
Renaming this function can make code readable.
Cc: James Morse
Reviewed-by: Suzuki K Poulose
Signed-off-by: Dongjiu Geng
---
I remeber James also
ports vcpu events by checking
the KVM_CAP_VCPU_EVENTS extension
Cc: James Morse
Reviewed-by : Suzuki K Poulose
Signed-off-by: Dongjiu Geng
---
For the 32 bits kvm migration, it needs to enable the vcpu events,
this patch will enable it. The user space QEMU patch is here:
https://patchwork.ozlabs
In order to remove the additional check before calling the
ghes_notify_sea(), make stub definition when !CONFIG_ACPI_APEI_SEA.
After this cleanup, we can simply call the ghes_notify_sea() to let
APEI driver handle the SEA notification.
CC: Tyler Baicar
CC: James Morse
Signed-off-by: Dongjiu
In order to remove the additional check before calling the
ghes_notify_sea(), make stub definition when !CONFIG_ACPI_APEI_SEA.
After this cleanup, we can simply call the ghes_notify_sea() to let
APEI driver handle the SEA notification.
CC: Tyler Baicar
CC: James Morse
Signed-off-by: Dongjiu
In order to remove the additional check before calling the
ghes_notify_sea(), make stub definition when !CONFIG_ACPI_APEI_SEA.
Signed-off-by: Dongjiu Geng
---
This cleanup is ever mentioned by Mark Rutland in [1]
[1]:
https://lkml.org/lkml/2018/5/31/289
---
arch/arm64/mm/fault.c | 7
In order to remove the additional check before calling the
ghes_notify_sea(), make stub definition when !CONFIG_ACPI_APEI_SEA.
Signed-off-by: Dongjiu Geng
---
This cleanup is ever mentioned by Mark Rutland in [1]
[1]:
https://lkml.org/lkml/2018/5/31/289
---
arch/arm64/mm/fault.c | 7
, user space can get/set
the SError exception state to do migrate/snapshot/suspend.
Signed-off-by: Dongjiu Geng
---
change since v4:
Address Christoffer's comments, thanks Christoffer's review.
1. Change the 'Capebility' to 'Capability' to fix the typo issue
2. Not wra
/host/xhci-tegra.c:482:6: note: ‘err’ was declared here
Signed-off-by: Dongjiu Geng
---
How to reproduce:
1. make defconfig ARCH=arm
2. make -j100 CROSS_COMPILE=arm-linux-gnueabi- ARCH=arm
Then you can see below warnings:
drivers/usb/host/xhci-tegra.c: In function ‘tegra_xusb_mbox_thread’:
driver
, user space can get/set
the SError exception state to do migrate/snapshot/suspend.
Signed-off-by: Dongjiu Geng
--
this series patch is separated from
https://www.spinics.net/lists/kvm/msg168917.html
change since V12:
1. change (vcpu->arch.hcr_el2 & HCR_VSE) to !!(vcpu->arch.hcr_el2 &am
This series patch is separated from
https://www.spinics.net/lists/kvm/msg168917.html
1. CPI 6.1 adds support for NOTIFY_SEI as a GHES notification mechanism, so
this patch supports this
notification in software
Dongjiu Geng (2):
ACPI / APEI: Add SEI notification type support for ARMv8
When kernel or KVM gets the NOTIFY_SEI notification, it firstly
calls the APEI driver to handle this notification.
Signed-off-by: Dongjiu Geng
---
arch/arm64/kernel/traps.c | 15 +++
1 file changed, 15 insertions(+)
---
change since https://www.spinics.net/lists/kvm/msg168919.html
ACPI 6.x adds support for NOTIFY_SEI as a GHES notification
mechanism, so add new GHES notification handling functions.
Expose API ghes_notify_sei() to arch code, arch code will call
this API when it gets this NOTIFY_SEI.
Signed-off-by: Dongjiu Geng
---
Note:
Firmware will follow the SError mask
ACPI 6.x adds support for NOTIFY_SEI as a GHES notification
mechanism, so add new GHES notification handling functions.
Expose API ghes_notify_sei() to arch code, arch code will call
this API when it gets this NOTIFY_SEI.
Signed-off-by: Dongjiu Geng
Note:
Firmware will follow the SError mask
user space, otherwise returns false.
Signed-off-by: Dongjiu Geng
Reviewed-by: James Morse
Change from V11:
1. Change the commit message
2. Update the Documentation/virtual/kvm/api.tx
---
Documentation/virtual/kvm/api.txt | 11 +++
arch/arm64/kvm/reset.c| 3 +++
include
Add a helper to handle the NOTIFY_SEI notification, when kernel
gets the NOTIFY_SEI notification, call this helper and let APEI
driver to handle this notification.
Signed-off-by: Dongjiu Geng
---
arch/arm64/include/asm/system_misc.h | 1 +
arch/arm64/kernel/traps.c| 4
arch
, user space can get/set
the SError exception state to do migrate/snapshot/suspend.
Signed-off-by: Dongjiu Geng
Change since V11:
Address James's comments, thanks James
1. Align the struct of kvm_vcpu_events to 64 bytes
2. Avoid exposing the stale ESR value in the kvm_arm_vcpu_get_events()
3. C
Initialise kvm_vcpu_events to 0 so that padding transferred to user-space
doesn't
contain kernel stack.
Dongjiu Geng (4):
arm64: KVM: export the capability to set guest SError syndrome
arm/arm64: KVM: Add KVM_GET/SET_VCPU_EVENTS
ACPI / APEI: Add SEI notification type supp
Add a helper to handle the NOTIFY_SEI notification, when kernel
gets the NOTIFY_SEI notification, call this helper and let APEI
driver to handle this notification.
Signed-off-by: Dongjiu Geng
---
arch/arm64/include/asm/system_misc.h | 1 +
arch/arm64/kernel/traps.c| 4
arch
This new IOCTL exports user-invisible states related to SError.
Together with appropriate user space changes, it can inject
SError with specified syndrome to guest by setup kvm_vcpu_events
value. Also it can support live migration.
Signed-off-by: Dongjiu Geng
Change since V10:
Address James&#
ACPI 6.x adds support for NOTIFY_SEI as a GHES notification
mechanism, so add new GHES notification handling functions.
Expose API ghes_notify_sei() to arch code, arch code will call
this API when it gets this NOTIFY_SEI.
Signed-off-by: Dongjiu Geng
---
drivers/acpi/apei/Kconfig | 15
Make kvm_vcpu_events struct align to 4 bytes
4. Add something check in the kvm_arm_vcpu_set_events()
5. Check kvm_arm_vcpu_get/set_events()'s return value.
6. Initialise kvm_vcpu_events to 0 so that padding transferred to user-space
doesn't
contain kernel stack.
Dongjiu Geng (4):
arm64:
Before user space injects a SError, it needs to know whether it can
specify the guest Exception Syndrome, so KVM should tell user space
whether it has such capability.
Signed-off-by: Dongjiu Geng
---
Documentation/virtual/kvm/api.txt | 11 +++
arch/arm64/kvm/reset.c| 3
Before user space injects a SError, it needs to know whether it can
specify the guest Exception Syndrome, so KVM should tell user space
whether it has such capability.
Signed-off-by: Dongjiu Geng
---
Documentation/virtual/kvm/api.txt | 11 +++
arch/arm64/kvm/reset.c| 3
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