the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3:
- Add dependency on COMMON_CLK (actually in v2.1) (Guenter Roeck)
- Add colle
mmc: configure default output tap delay
phy: rockchip-emmc: reindent the register definitions
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes
Documentation: mmc: sdhci-of-arasan: Add soc-ctl-sys
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson
Reviewed-by: Heiko Stuebner
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add dependency on COMMON_CLK (actually in v2.1) (Guenter Roeck)
- Add collected tags
Changes in v2: None
drivers/mmc/host/Kconfig | 1
ms if picked without that change.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Reviewed-by: Shawn Lin <shawn@rock-chips.com>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3:
- Add collected tags
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: Kishon Vijay A
ms if picked without that change.
Signed-off-by: Douglas Anderson
Reviewed-by: Shawn Lin
Tested-by: Heiko Stuebner
---
Changes in v3:
- Add collected tags
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --gi
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Reviewed-by: Shawn
..@chromium.org>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: Kishon Vijay Abraham I <kis...@ti.com>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3:
- Add Brian's PHY patches into my series
Changes in v2: None
drivers/phy/phy-rockchip-emm
to 4
(approx 90 degree phase?). If we need to configure this any further
(e.g., based on board or speed factors), we may need to consider a
device tree representation.
Suggested-by: Shawn Lin
Signed-off-by: Brian Norris
Signed-off-by: Douglas Anderson
Acked-by: Kishon Vijay Abraham I
Tested
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Note: just sending the one quick fix as v2.1. If further spins are
needed I'll send out a full v3.
Changes in v2.1:
- Add dependency on COMMON_CLK (Guenter Roeck)
Changes in v2: None
drive
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson
---
Note: just sending the one quick fix as v2.1. If further spins are
needed I'll send out a full v3.
Changes in v2.1:
- Add dependency on COMMON_CLK (Guenter Roeck)
Changes in v2: None
drivers/mmc/host/Kconfig
ute from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/b
ute from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk33
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- In
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Indicate that 5.1 ms
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v2:
- Clean up description of rk3399 PHY (Shawn)
- Add Rob Herring's Ack.
.../devicetree/bindings/
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
Acked-by: Rob Herring
---
Changes in v2:
- Clean up description of rk3399 PHY (Shawn)
- Add Rob Herring's Ack.
.../devicetree/bindings/mmc/arasan,sdhci.txt | 27 +++
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 ins
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64
series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Warn if we're more than 15 MHz from ide
the SDHCI card clock using a standard device tree mechanism
so that the PHY can get access to it and query the card clock frequency.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v2:
- Adjust commit message wording (Ro
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
arch/arm6
series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Warn if we're more than 15 MHz from ideal rate (Shawn)
- Move code
the SDHCI card clock using a standard device tree mechanism
so that the PHY can get access to it and query the card clock frequency.
Signed-off-by: Douglas Anderson
Acked-by: Rob Herring
---
Changes in v2:
- Adjust commit message wording (Rob)
- Add Rob Herring's Ack.
Documentation/devicetree
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399
om/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- List out clocks and clock names (Rob)
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 9 +
1 file changed, 9 insertions(+)
diff --git a/Docume
om/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
Changes in v2:
- List out clocks and clock names (Rob)
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bin
There's no reason to store the return value of rockchip_emmc_phy_power()
in a variable nor to check it. Just return it.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Move code cleanup before set phyctrl_frqsel based on card clock (Shawn)
drivers/phy/phy-ro
There's no reason to store the return value of rockchip_emmc_phy_power()
in a variable nor to check it. Just return it.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Move code cleanup before set phyctrl_frqsel based on card clock (Shawn)
drivers/phy/phy-rockchip-emmc.c | 14
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 125 -
1 file changed, 122 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-ar
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson
---
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 125 -
1 file changed, 122 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host
r
SoCs. Note that a specific compatible string for rk3399 is already in
use and so we add that to the table to match rk3399.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Reorder include
ms if picked without that change.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/ho
HCI (Shawn)
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes
Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg
regs
mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3
r
SoCs. Note that a specific compatible string for rk3399 is already in
use and so we add that to the table to match rk3399.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Reorder includes (Shawn)
drivers/m
ms if picked without that change.
Signed-off-by: Douglas Anderson
---
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.
HCI (Shawn)
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes
Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg
regs
mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3
>From their website:
http://www.b001.com.cn/
Starry appears to be a company involved in LCD panels and related
components.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
d
>From their website:
http://www.b001.com.cn/
Starry appears to be a company involved in LCD panels and related
components.
Signed-off-by: Douglas Anderson
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicet
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Proper title (sorry!)
.../devicetree/bindings/display/panel/starry,kr122ea0sra.txt | 7 +++
1 file
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Proper title (sorry!)
.../devicetree/bindings/display/panel/starry,kr122ea0sra.txt | 7 +++
1 file changed, 7 insertions(+)
create
turer-specified data, tag 15
ASCII string: STARRY
ASCII string: KR122EA0SRA
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/
turer-specified data, tag 15
ASCII string: STARRY
ASCII string: KR122EA0SRA
Signed-off-by: Douglas Anderson
---
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/driver
turer-specified data, tag 15
ASCII string: STARRY
ASCII string: KR122EA0SRA
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
turer-specified data, tag 15
ASCII string: STARRY
ASCII string: KR122EA0SRA
Signed-off-by: Douglas Anderson
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
.../devicetree/bindings/display/panel/starry,kr122ea0sra.txt | 7 +++
1 file changed, 7 insertions(+)
create
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson
---
.../devicetree/bindings/display/panel/starry,kr122ea0sra.txt | 7 +++
1 file changed, 7 insertions(+)
create mode 100644
Documentation/devicetree/bin
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 27 --
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/D
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 27 --
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/ara
ms if picked without that change.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-a
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/phy/phy-ro
ms if picked without that change.
Signed-off-by: Douglas Anderson
---
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 533e2bcb10bc.
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson
---
drivers/phy/phy-rockchip-emmc.c | 27
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/host/sdhci-of-arasan.c | 125 -
1 file changed, 122 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mm
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson
---
drivers/mmc/host/sdhci-of-arasan.c | 125 -
1 file changed, 122 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index
series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/phy/phy-rockchip-emmc.c | 74 +++
om/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/rockchip/
Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work
with arasan,sdhci-5.1) need to know the card clock in order to function
properly. Let's expose this clock using a standard device tree
mechanism so that the PHY can get access to and query the card clock.
Signed-off-by: Douglas
There's no reason to store the return value of rockchip_emmc_phy_power()
in a variable nor to check it. Just return it.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/phy/phy-rockchip-emmc.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/d
om/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
b/Documentation/devicetree/bindin
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4
1 file
Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work
with arasan,sdhci-5.1) need to know the card clock in order to function
properly. Let's expose this clock using a standard device tree
mechanism so that the PHY can get access to and query the card clock.
Signed-off-by: Douglas
There's no reason to store the return value of rockchip_emmc_phy_power()
in a variable nor to check it. Just return it.
Signed-off-by: Douglas Anderson
---
drivers/phy/phy-rockchip-emmc.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/phy/phy-rockchip-emmc.c
series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
drivers/phy/phy-rockchip-emmc.c | 74 +++--
1 file
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip
with the outstanding code patches
or I could try folding those patches into mine. Since those patches
aren't in 4.7-rc1 presumably they would also make sense to take through
the MMC tree if others agree.
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci
r
SoCs. Note that a specific compatible string for rk3399 is already in
use and so we add that to the table to match rk3399.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/host/sdhc
with the outstanding code patches
or I could try folding those patches into mine. Since those patches
aren't in 4.7-rc1 presumably they would also make sense to take through
the MMC tree if others agree.
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci
r
SoCs. Note that a specific compatible string for rk3399 is already in
use and so we add that to the table to match rk3399.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson
---
drivers/mmc/host/sdhci-of-a
is 676
MHz which gives us 169 MHz).
Signed-off-by: David Wu <david...@rock-chips.com>
Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Note: this patch
MHz).
Signed-off-by: David Wu
Signed-off-by: Jianqun Xu
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson
---
Note: this patch is based upon David Wu's patch series to add rk3399
support to i2c-rk3x.c and shouldn't land until at least device tree
h=arm") and use
a symlink. Note that in this case we put the files in a new
"include/common" directory since these snippets may need to be
referenced by dts files in many different subdirectories.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Note that, as of rig
h=arm") and use
a symlink. Note that in this case we put the files in a new
"include/common" directory since these snippets may need to be
referenced by dts files in many different subdirectories.
Signed-off-by: Douglas Anderson
---
Note that, as of right now, there are no users of t
(mostly UHS,
though a few not) into a veyron_minnie and confirmed that they still
seem to enumerate properly. For a subset of them I tried putting a
filesystem on them and also tried running mmc_test.
Fixes: 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card
initialization")
Si
(mostly UHS,
though a few not) into a veyron_minnie and confirmed that they still
seem to enumerate properly. For a subset of them I tried putting a
filesystem on them and also tried running mmc_test.
Fixes: 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card
initialization")
Signe
ken patch and fix everything.
3. Both patches: fixes everyone. Once dw_mmc is initting properly then
any defaults from the clock code doesn't mattery.
Fixes: 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card
initialization")
Signed-off-by: Douglas Anderson <diand...
ken patch and fix everything.
3. Both patches: fixes everyone. Once dw_mmc is initting properly then
any defaults from the clock code doesn't mattery.
Fixes: 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card
initialization")
Signed-off-by: Douglas Anderson
---
drive
same card.
This is more expected:
Good phase range 189-1 (173 len)
Good phase range 82-85 (4 len)
Good phase range 166-168 (3 len)
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --g
same card.
This is more expected:
Good phase range 189-1 (173 len)
Good phase range 82-85 (4 len)
Good phase range 166-168 (3 len)
Signed-off-by: Douglas Anderson
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-r
confirmed that they still
seem to enumerate properly. For a subset of them I tried putting a
filesystem on them and also tried running mmc_test.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Now use 90 degrees for some modes; updated comments to say why.
confirmed that they still
seem to enumerate properly. For a subset of them I tried putting a
filesystem on them and also tried running mmc_test.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Now use 90 degrees for some modes; updated comments to say why.
drivers/mmc/host/dw_mmc-rockc
bility.
I have tested this by inserting my collection of uSD cards (mostly UHS,
though a few not) into a veyron_minnie and confirmed that they still
seem to enumerate properly. For a subset of them I tried putting a
filesystem on them and also tried running mmc_test.
Signed-off-by: Douglas Ander
bility.
I have tested this by inserting my collection of uSD cards (mostly UHS,
though a few not) into a veyron_minnie and confirmed that they still
seem to enumerate properly. For a subset of them I tried putting a
filesystem on them and also tried running mmc_test.
Signed-off-by: Dougla
The rk3399 clock table had a simple typo in it, calling the SDMMC sample
and drive clocks by the wrong name. Fix this minor typo.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
The rk3399 clock table had a simple typo in it, calling the SDMMC sample
and drive clocks by the wrong name. Fix this minor typo.
Signed-off-by: Douglas Anderson
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip
p://crosreview.com/259916]
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Rebased atop mmc-next
- Stat dynamic allocation after fixed allocation; thanks Wolfram!
drivers/mmc/core/host.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
Now that mmc aliases are officially in bindings, add them to rk3288.
This could be done to lots of platforms, but this is the one I tested
with.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- rk3288 patch new for v2
arch/arm/boot/dts/rk3288.dtsi | 4
with block device numbering using MMC/SD host device ID, this
results in predictable name assignment of the internal eMMC block
device.
Signed-off-by: Stefan Agner
Signed-off-by: Dmitry Torokhov
[dianders: rebase + roll in http://crosreview.com/259916]
Signed-off-by: Douglas Anderson
---
Changes
Now that mmc aliases are officially in bindings, add them to rk3288.
This could be done to lots of platforms, but this is the one I tested
with.
Signed-off-by: Douglas Anderson
---
Changes in v2:
- rk3288 patch new for v2
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions
quot; will always refer to eMMC is handy.
Changes in v2:
- Rebased atop mmc-next
- Stat dynamic allocation after fixed allocation; thanks Wolfram!
- rk3288 patch new for v2
Douglas Anderson (1):
ARM: dts: rockchip: Add mmc aliases for rk3288 platform
Jaehoon Chung (1):
Documentation: mmc: Docum
quot; will always refer to eMMC is handy.
Changes in v2:
- Rebased atop mmc-next
- Stat dynamic allocation after fixed allocation; thanks Wolfram!
- rk3288 patch new for v2
Douglas Anderson (1):
ARM: dts: rockchip: Add mmc aliases for rk3288 platform
Jaehoon Chung (1):
Documentation: mmc: Docum
for SD */
mmc2 =/* mmc2/mmcblk2 for SDIO*/
};
If there are no corresponding values, it might be allocated with
existing scheme.
Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
[dianders: just bindings now; mention mmc not just mmcblk]
Signed-off-by: Douglas Anderson <diand.
for SDIO*/
};
If there are no corresponding values, it might be allocated with
existing scheme.
Signed-off-by: Jaehoon Chung
[dianders: just bindings now; mention mmc not just mmcblk]
Signed-off-by: Douglas Anderson
---
Changes in v2: None
Documentation/devicetree/bindings/mmc/mmc.txt | 11
nation is not ordered by
the SD/MMC host device ID (since mmc_rescan is called in order of
the memory mapped pheripherial addresses).
Signed-off-by: Stefan Agner <ste...@agner.ch>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Rebased atop mmc-next
drivers/mm
/MMC host device ID (since mmc_rescan is called in order of
the memory mapped pheripherial addresses).
Signed-off-by: Stefan Agner
Signed-off-by: Douglas Anderson
---
Changes in v2:
- Rebased atop mmc-next
drivers/mmc/card/block.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
p://crosreview.com/259916]
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/core/host.c | 25 -
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 71bb2372f71d..7ecb6a6351b3
for SD */
mmc2 =/* mmc2/mmcblk2 for SDIO*/
};
If there are no corresponding values, it might be allocated with
existing scheme.
Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
[dianders: just bindings now; mention mmc not just mmcblk]
Signed-off-by: Douglas Anderson <diand.
This series picks patches from various different places to produce what
I consider the best solution to getting consistent mmc and mmcblk
ordering.
Why consistent ordering and why not just use UUIDs? IMHO consistent
ordering solves a few different problems:
1. For poor, feeble-minded humans
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