On 08/03/2017 13:43, Mark Brown wrote:
> On Wed, Mar 08, 2017 at 11:35:02AM +0100, Frode Isaksen wrote:
>
>> To avoid data corruption issues with UBIFS volume over SPI NOR, DMA should
>> not be used for vmalloc'ed buffers. The 5'th patch in my series fixes that:
> It
On 08/03/2017 13:43, Mark Brown wrote:
> On Wed, Mar 08, 2017 at 11:35:02AM +0100, Frode Isaksen wrote:
>
>> To avoid data corruption issues with UBIFS volume over SPI NOR, DMA should
>> not be used for vmalloc'ed buffers. The 5'th patch in my series fixes that:
> It
SPI_IO_TYPE_INTR mode to transfer data even if DMA channels are
> defined in the DT.
>
> This commit changes the behaviour to select the SPI_IO_TYPE_DMA mode
> if DMA channels are defined in the DT and will keep SPI_IO_TYPE_INTR
> if the channels are not defined in it.
>
> Signe
fer data even if DMA channels are
> defined in the DT.
>
> This commit changes the behaviour to select the SPI_IO_TYPE_DMA mode
> if DMA channels are defined in the DT and will keep SPI_IO_TYPE_INTR
> if the channels are not defined in it.
>
> Signed-off-by: Fabien Parent
&g
On 02/03/2017 16:25, Boris Brezillon wrote:
> On Thu, 2 Mar 2017 16:03:17 +0100
> Frode Isaksen <fisak...@baylibre.com> wrote:
>
>> On 02/03/2017 15:29, Boris Brezillon wrote:
>>> On Thu, 2 Mar 2017 19:24:43 +0530
>>> Vignesh R <vigne...@ti.com> wrote
On 02/03/2017 16:25, Boris Brezillon wrote:
> On Thu, 2 Mar 2017 16:03:17 +0100
> Frode Isaksen wrote:
>
>> On 02/03/2017 15:29, Boris Brezillon wrote:
>>> On Thu, 2 Mar 2017 19:24:43 +0530
>>> Vignesh R wrote:
>>>
>>>>>>>>
On 02/03/2017 15:29, Boris Brezillon wrote:
> On Thu, 2 Mar 2017 19:24:43 +0530
> Vignesh R wrote:
>
>>
> Not really, I am debugging another issue with UBIFS on DRA74 EVM (ARM
> cortex-a15) wherein pages allocated by vmalloc are in highmem region
> that are
On 02/03/2017 15:29, Boris Brezillon wrote:
> On Thu, 2 Mar 2017 19:24:43 +0530
> Vignesh R wrote:
>
>>
> Not really, I am debugging another issue with UBIFS on DRA74 EVM (ARM
> cortex-a15) wherein pages allocated by vmalloc are in highmem region
> that are not addressable
On 01/03/2017 17:55, Boris Brezillon wrote:
> On Wed, 1 Mar 2017 17:16:30 +0530
> Vignesh R wrote:
>
>> On Wednesday 01 March 2017 04:13 PM, Cyrille Pitchen wrote:
>>> Le 01/03/2017 à 05:54, Vignesh R a écrit :
On Wednesday 01 March 2017 03:11 AM, Richard Weinberger
On 01/03/2017 17:55, Boris Brezillon wrote:
> On Wed, 1 Mar 2017 17:16:30 +0530
> Vignesh R wrote:
>
>> On Wednesday 01 March 2017 04:13 PM, Cyrille Pitchen wrote:
>>> Le 01/03/2017 à 05:54, Vignesh R a écrit :
On Wednesday 01 March 2017 03:11 AM, Richard Weinberger wrote:
>
On 01/03/2017 11:43, Cyrille Pitchen wrote:
> Le 01/03/2017 à 05:54, Vignesh R a écrit :
>>
>> On Wednesday 01 March 2017 03:11 AM, Richard Weinberger wrote:
>>> Vignesh,
>>>
>>> Am 27.02.2017 um 13:08 schrieb Vignesh R:
Many SPI controller drivers use DMA to read/write from m25p80
On 01/03/2017 11:43, Cyrille Pitchen wrote:
> Le 01/03/2017 à 05:54, Vignesh R a écrit :
>>
>> On Wednesday 01 March 2017 03:11 AM, Richard Weinberger wrote:
>>> Vignesh,
>>>
>>> Am 27.02.2017 um 13:08 schrieb Vignesh R:
Many SPI controller drivers use DMA to read/write from m25p80
On 01/03/2017 11:18, Boris Brezillon wrote:
> On Wed, 1 Mar 2017 11:09:57 +0100
> Cyrille Pitchen wrote:
>
>> Le 28/02/2017 à 22:39, Richard Weinberger a écrit :
>>> Vignesh,
>>>
>>> Am 27.02.2017 um 13:08 schrieb Vignesh R:
Filesystems like UBIFS may pass
On 01/03/2017 11:18, Boris Brezillon wrote:
> On Wed, 1 Mar 2017 11:09:57 +0100
> Cyrille Pitchen wrote:
>
>> Le 28/02/2017 à 22:39, Richard Weinberger a écrit :
>>> Vignesh,
>>>
>>> Am 27.02.2017 um 13:08 schrieb Vignesh R:
Filesystems like UBIFS may pass vmalloc'd buffers to SPI NOR
On 27/02/2017 13:08, Vignesh R wrote:
> This series implements bounce buffer support to handle vmalloc'd buffers
> in case of drivers use DMA, similar to what is done in MTD NAND
> framework.
>
> I have tested this on two platform:
> DRA74 SoC (cortex a15 @1GHz) with s25fl256s1 QSPI (SPI bus
On 27/02/2017 13:08, Vignesh R wrote:
> This series implements bounce buffer support to handle vmalloc'd buffers
> in case of drivers use DMA, similar to what is done in MTD NAND
> framework.
>
> I have tested this on two platform:
> DRA74 SoC (cortex a15 @1GHz) with s25fl256s1 QSPI (SPI bus
16 matches
Mail list logo