ed Linux and Kernel engineering
> http://free-electrons.com
>
> ___________
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
http://free-electrons.com
>
> ___________
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree
More and more SoCs use the pxa3xx_nand driver for their controller but
the list of them was not updated. This patch add the last SoCs using the
driver.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mtd/nand/Kconfig | 3 ++-
1 file changed, 2 insertions
More and more SoCs use the pxa3xx_nand driver for their controller but
the list of them was not updated. This patch add the last SoCs using the
driver.
Signed-off-by: Gregory CLEMENT
---
drivers/mtd/nand/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd
Armada XP A0 and the
Armada 38x SoCs.
And I still have to check it for Armada 375 and Armada 39x, but of
course it is not preventing merging your patches.
Gregory
> - interrupts : The interrupt number
>
> Optional properties :
> --
> 2.14.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
l have to check it for Armada 375 and Armada 39x, but of
course it is not preventing merging your patches.
Gregory
> - interrupts : The interrupt number
>
> Optional properties :
> --
> 2.14.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Chris,
On mer., sept. 27 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz>
wrote:
> Hi Gregory,
>
> On 27/09/17 00:56, Gregory CLEMENT wrote:
>> Hi Kalyan,
>>
>> Please try avoid top-posting.
>>
>> On dim., sept. 24 2017, Kalyan Kint
Hi Chris,
On mer., sept. 27 2017, Chris Packham
wrote:
> Hi Gregory,
>
> On 27/09/17 00:56, Gregory CLEMENT wrote:
>> Hi Kalyan,
>>
>> Please try avoid top-posting.
>>
>> On dim., sept. 24 2017, Kalyan Kinthada
>> wrote:
>>
>>
ble enable the errata fix but not the offloading feature. That
means that it is exactly the compatible you need for Armada 38x (and
Armada 39x and 375 I think).
Gregory
>
> Thanks,
> Kalyan
>
> From: Gregory CLEMENT <gregory.clem...@free-electron
at
means that it is exactly the compatible you need for Armada 38x (and
Armada 39x and 375 I think).
Gregory
>
> Thanks,
> Kalyan
>
> From: Gregory CLEMENT
> Sent: Friday, 22 September 2017 7:30 p.m.
> To: Kalyan Kinthada
> Cc: de
had broken offload support. Linux
> auto-detects this and sets it appropriately.
> + - "marvell,armada-38x-i2c"
> - interrupts : The interrupt number
>
> Optional properties :
> --
> 2.14.1
&
auto-detects this and sets it appropriately.
> + - "marvell,armada-38x-i2c"
> - interrupts : The interrupt number
>
> Optional properties :
> --
> 2.14.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
C: add support for reduced-width Armada-XP SDRAM
>
> .../bindings/memory-controllers/mvebu-sdram-controller.txt | 6
> ++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 1 +
> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
th Armada-XP SDRAM
>
> .../bindings/memory-controllers/mvebu-sdram-controller.txt | 6
> ++
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 1 +
> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +
> drivers/edac/armada_xp_edac
21..4773145246ed 100644
> --- a/include/linux/mbus.h
> +++ b/include/linux/mbus.h
> @@ -31,8 +31,8 @@ struct mbus_dram_target_info
> struct mbus_dram_window {
> u8 cs_index;
> u8 mbus_attr;
> - u32 base;
> - u32
b/include/linux/mbus.h
> @@ -31,8 +31,8 @@ struct mbus_dram_target_info
> struct mbus_dram_window {
> u8 cs_index;
> u8 mbus_attr;
> - u32 base;
> - u32 size;
> + u64 base;
> +
For those functions the mask is
computed at each call which is not a issue as these functions are not
located in a hot path but are used sporadically for configuration.
Fixes: dc749a09ea5e ("gpiolib: allow gpio irqchip to map irqs
dynamically")
Cc: <sta...@vger.kernel.org>
Sign
For those functions the mask is
computed at each call which is not a issue as these functions are not
located in a hot path but are used sporadically for configuration.
Fixes: dc749a09ea5e ("gpiolib: allow gpio irqchip to map irqs
dynamically")
Cc:
Signed-off-by: Gregory CLEMENT
---
now.
However I am not against the fact that it is applied through an other
tree because we don't touch this file for the next release so there is
no risk for a conflict, I can give my Acked-by if needed.
Thanks,
Gregory
>
> I'll look for an ack from Thomas or Jason before applying the sec
inst the fact that it is applied through an other
tree because we don't touch this file for the next release so there is
no risk for a conflict, I can give my Acked-by if needed.
Thanks,
Gregory
>
> I'll look for an ack from Thomas or Jason before applying the second patch,
> which tou
RATA_753970
> select ARM_GIC
> + select ARM_GLOBAL_TIMER
> + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
> select ARMADA_370_XP_IRQ
> select ARMADA_38X_CLK
> select HAVE_ARM_SCU
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, dri
ct ARM_GIC
> + select ARM_GLOBAL_TIMER
> + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
> select ARMADA_370_XP_IRQ
> select ARMADA_38X_CLK
> select HAVE_ARM_SCU
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
compatible = "arm,cortex-a9-twd-timer";
> reg = <0xc600 0x20>;
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
00 0x20>;
> + interrupts = | GIC_CPU_MASK_SIMPLE(2))>;
> + clocks = < 2>;
> + };
> +
> timer@c600 {
> compatible = "arm,cortex-a9-twd-t
+ b/arch/arm64/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y
> CONFIG_AUDIT=y
> CONFIG_NO_HZ_IDLE=y
> CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> CONFIG_BSD_PROCESS_ACCT=y
> CONFIG_BSD_PROCESS_ACCT_V3=y
> CONFIG_TASKSTATS=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
6 +3,7 @@ CONFIG_POSIX_MQUEUE=y
> CONFIG_AUDIT=y
> CONFIG_NO_HZ_IDLE=y
> CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> CONFIG_BSD_PROCESS_ACCT=y
> CONFIG_BSD_PROCESS_ACCT_V3=y
> CONFIG_TASKSTATS=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
tive-high;
>> +};
>> };
>>
>> /* J9 */
>> @@ -71,6 +86,17 @@
>> status = "okay";
>> };
>>
>> +/* J1 */
>> + {
>> +wp-inverted;
>> +bus-width = <4>;
>> +cd-gpios = < 3 GPIO_ACTIVE_L
t;>
>> +/* J1 */
>> + {
>> +wp-inverted;
>> +bus-width = <4>;
>> +cd-gpios = < 3 GPIO_ACTIVE_LOW>;
>> +no-1-8-v;
>> +marvell,pad-type = "sd";
>> +vqmmc-supply = <_sd_reg1>;
>> +status = "okay";
>> +};
>> +
>> /* Exported on the micro USB connector J5 through an FTDI */
>> {
>> status = "okay";
>
>
>
> --
> Miquel Raynal, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
POSIX_MQUEUE=y
> CONFIG_AUDIT=y
> CONFIG_NO_HZ_IDLE=y
> CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> CONFIG_BSD_PROCESS_ACCT=y
> CONFIG_BSD_PROCESS_ACCT_V3=y
> CONFIG_TASKSTATS=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IRQ_TIME_ACCOUNTING=y
> CONFIG_BSD_PROCESS_ACCT=y
> CONFIG_BSD_PROCESS_ACCT_V3=y
> CONFIG_TASKSTATS=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Linus,
On lun., juil. 24 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Hi Linus,
>
> On mer., juil. 12 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
> wrote:
>
>> When switching to regmap, the way to compute the irq
Hi Linus,
On lun., juil. 24 2017, Gregory CLEMENT
wrote:
> Hi Linus,
>
> On mer., juil. 12 2017, Gregory CLEMENT
> wrote:
>
>> When switching to regmap, the way to compute the irq cause was
>> reorganized. However while doing it, a typo was intr
d pin controller support
for Armada 37xx")
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mveb
d pin controller support
for Armada 37xx")
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index c9
.
Please apply them for v4.13-rc.
Thanks,
Gregory
Gregory CLEMENT (2):
pinctrl: armada-37xx: Fix the pin 23 on south bridge
pinctrl: armada-37xx: Fix number of pin in south bridge
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 25 ++---
1 file changed, 18 insertions(+), 7
.
Please apply them for v4.13-rc.
Thanks,
Gregory
Gregory CLEMENT (2):
pinctrl: armada-37xx: Fix the pin 23 on south bridge
pinctrl: armada-37xx: Fix number of pin in south bridge
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 25 ++---
1 file changed, 18 insertions(+), 7
a-37xx: Add pin controller support
for Armada 37xx")
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada
a-37xx: Add pin controller support
for Armada 37xx")
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl
Hi Linus,
On mer., juil. 12 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> When switching to regmap, the way to compute the irq cause was
> reorganized. However while doing it, a typo was introduced: a 'xor'
> replaced a 'and'.
>
> This l
Hi Linus,
On mer., juil. 12 2017, Gregory CLEMENT
wrote:
> When switching to regmap, the way to compute the irq cause was
> reorganized. However while doing it, a typo was introduced: a 'xor'
> replaced a 'and'.
>
> This lead to wrong behavior in the interrupt
Hi,
On mer., juil. 19 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> The NAND controller used in A7K/A8K is present on the CP110 master
> part. It is compatible with the pxa-nand driver.
>
> Unlike most of the controller on the CP110 this o
Hi,
On mer., juil. 19 2017, Gregory CLEMENT
wrote:
> The NAND controller used in A7K/A8K is present on the CP110 master
> part. It is compatible with the pxa-nand driver.
>
> Unlike most of the controller on the CP110 this one is only present on
> the master for the Armada 8K
The controller supported by the pxa3xx_nand driver is also available on
the mvebu 64-bit SoCs, such as the Armada 7K and Armada 8K SoCs. This
patch updates the Kconfig dependency to allow building the kernel for
this SoC family too.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
The controller supported by the pxa3xx_nand driver is also available on
the mvebu 64-bit SoCs, such as the Armada 7K and Armada 8K SoCs. This
patch updates the Kconfig dependency to allow building the kernel for
this SoC family too.
Signed-off-by: Gregory CLEMENT
---
drivers/mtd/nand/Kconfig
.
The patches are completely independent.
Thanks,
Gregory
Gregory CLEMENT (2):
mtd: nand: pxa3xx_nand: enable building on mvebu 64-bit platforms
ARM64: dts: marvell: add NAND support on the CP110 master
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 14 ++
drivers/mtd/nand
.
The patches are completely independent.
Thanks,
Gregory
Gregory CLEMENT (2):
mtd: nand: pxa3xx_nand: enable building on mvebu 64-bit platforms
ARM64: dts: marvell: add NAND support on the CP110 master
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 14 ++
drivers/mtd/nand
The NAND controller used in A7K/A8K is present on the CP110 master
part. It is compatible with the pxa-nand driver.
Unlike most of the controller on the CP110 this one is only present on
the master for the Armada 8K SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.
The NAND controller used in A7K/A8K is present on the CP110 master
part. It is compatible with the pxa-nand driver.
Unlike most of the controller on the CP110 this one is only present on
the master for the Armada 8K SoCs.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada
t; Cc: Sascha Hauer <ker...@pengutronix.de>
> Cc: Fabio Estevam <fabio.este...@nxp.com>
> Cc: Jason Cooper <ja...@lakedaemon.net>
> Cc: Andrew Lunn <and...@lunn.ch>
> Cc: Gregory Clement <gregory.clem...@free-electrons.com>
> Cc: Sebastian Hesselbarth <
Russell King
> Cc: Kukjin Kim
> Cc: Krzysztof Kozlowski
> Cc: Javier Martinez Canillas
> Cc: Shawn Guo
> Cc: Sascha Hauer
> Cc: Fabio Estevam
> Cc: Jason Cooper
> Cc: Andrew Lunn
> Cc: Gregory Clement
> Cc: Sebastian Hesselbarth
> Cc: Tony Lindgren
>
gmap for register access")
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/gpio/gpio-mvebu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index e338c3743562..45c65f805fd6 100644
--
gmap for register access")
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/gpio-mvebu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index e338c3743562..45c65f805fd6 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/driver
>>
>>> arch/arm/mach-mvebu/platsmp.c: writel(virt_to_phys(boot_addr), base +
>>> MV98DX3236_CPU_RESUME_ADDR_REG);
>>>
>>> and these in mach-at91:
>>>
>>> arch/arm/mach-at91/pm.c:pm_bu->canary = virt_to_phys();
>>> ar
X3236_CPU_RESUME_ADDR_REG);
>>>
>>> and these in mach-at91:
>>>
>>> arch/arm/mach-at91/pm.c:pm_bu->canary = virt_to_phys();
>>> arch/arm/mach-at91/pm.c:pm_bu->resume = virt_to_phys(cpu_resume);
>>>
>>
>> Th
on Armada 7K/8K
(2017-06-27 09:07:17 +0200)
Gregory CLEMENT (6):
dt-bindings: cp110: do not depend anymore of the *-clock-output-names
dt-bindings: cp110: introduce a new binding
dt-bindings: cp110: add sdio clock
on Armada 7K/8K
(2017-06-27 09:07:17 +0200)
Gregory CLEMENT (6):
dt-bindings: cp110: do not depend anymore of the *-clock-output-names
dt-bindings: cp110: introduce a new binding
dt-bindings: cp110: add sdio clock
The sdio_sb group is composed of 6 pins and not 5.
Reported-by: Ken Ma <m...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dri
The sdio_sb group is composed of 6 pins and not 5.
Reported-by: Ken Ma
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu
Hi,
Ken Ma found few issues in the driver. I wrote the first fix is based
on his report and the second one was written for U-Boot but as they
use the same driver it can be applied on linux too.
thanks,
Gregory
Gregory CLEMENT (1):
pinctrl: armada-37xx: Fix number of pin in sdio_sb
Ken Ma (1
group and it must be set
for both "gpio" and "uart" functions of uart2 group.
Signed-off-by: Ken Ma <m...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
1 file changed, 3 ins
Hi,
Ken Ma found few issues in the driver. I wrote the first fix is based
on his report and the second one was written for U-Boot but as they
use the same driver it can be applied on linux too.
thanks,
Gregory
Gregory CLEMENT (1):
pinctrl: armada-37xx: Fix number of pin in sdio_sb
Ken Ma (1
for both "gpio" and "uart" functions of uart2 group.
Signed-off-by: Ken Ma
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/d
Hi Mike,
as you were not in CC of the thread here is the reference:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/514497.html
On jeu., juin 22 2017, Rob Herring <r...@kernel.org> wrote:
> On Tue, Jun 20, 2017 at 05:34:57PM +0200, Gregory CLEMENT wrote:
Hi Mike,
as you were not in CC of the thread here is the reference:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/514497.html
On jeu., juin 22 2017, Rob Herring wrote:
> On Tue, Jun 20, 2017 at 05:34:57PM +0200, Gregory CLEMENT wrote:
>> Hi Rob,
>>
>&
t MVEBU_ICU
> select MVEBU_ODMI
> select MVEBU_PIC
> help
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Marc,
On mer., juin 21 2017, Marc Zyngier <marc.zyng...@arm.com> wrote:
> On 21/06/17 16:42, Gregory CLEMENT wrote:
>> Hi Marc and Thomas,
>>
>> On mer., juin 21 2017, Thomas Petazzoni
>> <thomas.petazz...@free-electrons.com> wrote:
>>
&g
> @@ -106,6 +106,8 @@ config ARCH_MVEBU
> select ARMADA_AP806_SYSCON
> select ARMADA_CP110_SYSCON
> select ARMADA_37XX_CLK
> + select MVEBU_GICP
> + select MVEBU_ICU
> select MVEBU_ODMI
> select MVEBU_PIC
> help
> --
> 2.9.4
>
Hi Marc,
On mer., juin 21 2017, Marc Zyngier wrote:
> On 21/06/17 16:42, Gregory CLEMENT wrote:
>> Hi Marc and Thomas,
>>
>> On mer., juin 21 2017, Thomas Petazzoni
>> wrote:
>>
>>> Hello,
>>>
>>> On Wed, 21 Jun 2017 16:14
,
> - ,
> - ,
> - ;
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_
,
> - ,
> - ;
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "mem", "ring0", "ring1",
> "ring2", "ring3", "eip";
> clocks = <_syscon0 1 26>;
> @@ -254,8 +263,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfa00 0 0xfa00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 256
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 22
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
> num-lanes = <1>;
> clocks = <_syscon0 1 13>;
> status = "disabled";
> @@ -280,8 +289,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfb00 0 0xfb00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 258
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 24
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
>
> num-lanes = <1>;
> clocks = <_syscon0 1 11>;
> @@ -307,8 +316,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfc00 0 0xfc00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 257
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 23
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
>
> num-lanes = <1>;
> clocks = <_syscon0 1 12>;
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
the last one?
>
> I think you should take the first four patches, and Grégory takes the
> last two ones. But I'll let Grégory confirm.
Indeed it makes more sens to merge the patch 4 through the arm-soc
subsystem.
Thanks,
Gregory
>
> Once again, thanks a lot for your help on thi
should take the first four patches, and Grégory takes the
> last two ones. But I'll let Grégory confirm.
Indeed it makes more sens to merge the patch 4 through the arm-soc
subsystem.
Thanks,
Gregory
>
> Once again, thanks a lot for your help on this series, it's in a much
> better shap
Hi Linus,
On ven., juin 16 2017, Linus Walleij <linus.wall...@linaro.org> wrote:
> On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
> <gregory.clem...@free-electrons.com> wrote:
>
>> This commit makes sure the drivers for the Armada 7K/8K pin controllers
>
Hi Linus,
On ven., juin 16 2017, Linus Walleij wrote:
> On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
> wrote:
>
>> This commit makes sure the drivers for the Armada 7K/8K pin controllers
>> are enabled.
>>
>> Reviewed-by: Thomas Petazzoni
>> Si
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni <thomas.petazz...@free-electrons.com>
wrote:
> Hello,
>
> On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
>
>> > +#include
>>
>> With this line you created a dependency with the patch
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni
wrote:
> Hello,
>
> On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
>
>> > +#include
>>
>> With this line you created a dependency with the patch "irqchip:
>> irq-mvebu-icu: new dri
> - ,
> - ,
> - ;
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "mem", "ring0", "ring1",
> "ring2", "ring3", "eip";
> clocks = <_syscon0 1 26>;
> @@ -254,8 +261,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfa00 0 0xfa00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 256
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 22
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
> num-lanes = <1>;
> clocks = <_syscon0 1 13>;
> status = "disabled";
> @@ -280,8 +287,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfb00 0 0xfb00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 258
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 24
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
>
> num-lanes = <1>;
> clocks = <_syscon0 1 11>;
> @@ -307,8 +314,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfc00 0 0xfc00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 257
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 23
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
>
> num-lanes = <1>;
> clocks = <_syscon0 1 12>;
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
,
> - ;
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>,
> + IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "mem", "ring0", "ring1",
> "ring2", "ring3", "eip";
> clocks = <_syscon0 1 26>;
> @@ -254,8 +261,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfa00 0 0xfa00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 256
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 22
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
> num-lanes = <1>;
> clocks = <_syscon0 1 13>;
> status = "disabled";
> @@ -280,8 +287,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfb00 0 0xfb00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 258
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 24
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
>
> num-lanes = <1>;
> clocks = <_syscon0 1 11>;
> @@ -307,8 +314,8 @@
> /* non-prefetchable memory */
> 0x8200 0 0xfc00 0 0xfc00 0
> 0xf0>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 0 GIC_SPI 257
> IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = ;
> + interrupt-map = <0 0 0 0 _icu 0 ICU_GRP_NSR 23
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = ;
>
> num-lanes = <1>;
> clocks = <_syscon0 1 12>;
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi,
On lun., juin 12 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.
>
> The Armada 8K has two CP110 blocks, each having two GPIO controllers.
> However, in each CP110 block, one of t
Hi,
On lun., juin 12 2017, Gregory CLEMENT
wrote:
> Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.
>
> The Armada 8K has two CP110 blocks, each having two GPIO controllers.
> However, in each CP110 block, one of the GPIO controller cannot be
> used: in t
Hi,
On lun., juin 12 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
>
> The CP master being different between Armada 7k and Armada 8k. This
> commit introduces the intermediates file
Hi,
On lun., juin 12 2017, Gregory CLEMENT
wrote:
> Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
>
> The CP master being different between Armada 7k and Armada 8k. This
> commit introduces the intermediates files armada-70x0.dtsi and
> armada-80x0.dtsi.
>
Hi,
On jeu., juin 01 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> The new binding for the system controller on cp110 moved the clock
> controller into a subnode. This preliminary step will allow to add gpio
> and pinctrl subnodes.
>
> Reviewed
Hi,
On jeu., juin 01 2017, Gregory CLEMENT
wrote:
> The new binding for the system controller on cp110 moved the clock
> controller into a subnode. This preliminary step will allow to add gpio
> and pinctrl subnodes.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-b
Hi,
On jeu., juin 01 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> The *-clock-output-names of the cp110-system-controller0 node are not
> used anymore, so remove them.
>
> Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Hi,
On jeu., juin 01 2017, Gregory CLEMENT
wrote:
> The *-clock-output-names of the cp110-system-controller0 node are not
> used anymore, so remove them.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-by: Gregory CLEMENT
Applied on mvebu/dt64
Thanks,
Gregory
> ---
Hi Stephen,
On mar., juin 20 2017, Stephen Boyd <sb...@codeaurora.org> wrote:
> On 06/19, Gregory CLEMENT wrote:
>>
>> Hi Mike, Stephen,
>>
>> This time I turned the series in a pull request so I removed the
>> device tree binding part which will b
Hi Stephen,
On mar., juin 20 2017, Stephen Boyd wrote:
> On 06/19, Gregory CLEMENT wrote:
>>
>> Hi Mike, Stephen,
>>
>> This time I turned the series in a pull request so I removed the
>> device tree binding part which will be in an other series for Rob
>
controllers and the clock tree
of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The
clk driver is modified accordingly from this new information.
Gregory CLEMENT (3):
clk: mvebu: cp110: make failure labels more meaningful
controllers and the clock tree
of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The
clk driver is modified accordingly from this new information.
Gregory CLEMENT (3):
clk: mvebu: cp110: make failure labels more meaningful
warning, I fix it right now.
Gregory
>
> --
> Cheers,
> Stephen Rothwell
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
y
>
> --
> Cheers,
> Stephen Rothwell
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
interrupt-controller;
> #interrupt-cells = <2>;
> interrupts = ,
>,
>,
>;
> + clocks = < 0>;
> };
>
> systemc: system-controller@18200 {
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
quot;, "pwm";
> ngpios = <28>;
> gpio-controller;
> #gpio-cells = <2>;
> + #pwm-cells = <2>;
> interrupt-controller;
>
<and...@lunn.ch>
> URL: https://patchwork.ozlabs.org/patch/427294/
> [Ralph Sennhauser: Add new compatible string marvell,armada-370-gpio]
> Signed-off-by: Ralph Sennhauser <ralph.sennhau...@gmail.com>
> Tested-by: Andrew Lunn <and...@lunn.ch>
> Acked-by: Linus Wall
alph Sennhauser: Add new compatible string marvell,armada-370-gpio]
> Signed-off-by: Ralph Sennhauser
> Tested-by: Andrew Lunn
> Acked-by: Linus Walleij
> Signed-off-by: Gregory CLEMENT
Applied on mvebu/dt as a replacement on the former version.
Thanks,
Gregory
>
> ---
&
<j...@semihalf.com>
[ - rebased on 4.12-rc1
- fixed the 80 character limit for mvebu_mpp_mode array
- aligned the compatible name on the ones already used
- fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT <g
sed
- fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT
Tested-by: Thomas Petazzoni
---
drivers/pinctrl/mvebu/Kconfig| 4 +-
drivers/pinctrl/mvebu/Makefile | 1 +-
drivers/pinctrl/mvebu/pinc
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