The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
The current settings for 28nm PHY data lane CFG4 registers do
not work with certain panels. This change is to modify them to
hw recommended values.
Signed-off-by: Hai Li <h...@codeaurora.org>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 ++
1 file changed, 2 insertions(+), 4 del
Lane swap configuration is based on the board design.
This change allows the DSI host to get this information
from device tree, instead of hardcoding in driver.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++
drivers/gpu/drm/msm/dsi/dsi_host.c
Lane swap configuration is based on the board design.
This change allows the DSI host to get this information
from device tree, instead of hardcoding in driver.
Signed-off-by: Hai Li <h...@codeaurora.org>
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 13 ++
drivers/gpu/drm/m
With more platforms supported, the DSI host
configuration array keeps expanding. This change
moves those to a separate dsi_cfg module.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 92 ++
drivers/gpu/drm/msm/dsi
The bit position to configure source PLL will change
on new types of PHYs. The caller should pass down
this information.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi
This change is to update DSI register definition changes
introduced by the following change:
rnndb/dsi: Add more bits for DSI PHY
More registers and bit fields are added for PHY timings
and bitclk source selection.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 5
This change moves each PHY type specific code into
separate files.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile | 6 +-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 756 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 448
On a certain platform, only one type of DSI PHY is used.
This change allows the user to only compile the PHY type
which is being used.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 14 ++
drivers/gpu/drm/msm/Makefile | 11 +++
drivers/gpu/drm/msm
We are not checking the return value from msm_dsi_phy_disable().
Change the return type to void.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +---
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers
The DSI PHY driver currently includes the implementation of all PHY types.
To support more types in the future, this patch series is moving each PHY
code into a separate file and making them compile independent. Some clean
up patches for DSI PHY are also included.
Hai Li (5):
drm/msm/dsi
More registers and bit fields are added for PHY timings
and bitclk source selection.
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 02cfa3b..956f3ff 100644
--- a/rnndb/dsi
The DSI PHY driver currently includes the implementation of all PHY types.
To support more types in the future, this patch series is moving each PHY
code into a separate file and making them compile independent. Some clean
up patches for DSI PHY are also included.
Hai Li (5):
drm/msm/dsi
With more platforms supported, the DSI host
configuration array keeps expanding. This change
moves those to a separate dsi_cfg module.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 92 ++
drivers
More registers and bit fields are added for PHY timings
and bitclk source selection.
Signed-off-by: Hai Li h...@codeaurora.org
---
rnndb/dsi/dsi.xml | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 02cfa3b..956f3ff 100644
This change moves each PHY type specific code into
separate files.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/Makefile | 6 +-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 756 -
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 448
The bit position to configure source PLL will change
on new types of PHYs. The caller should pass down
this information.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers
This change is to update DSI register definition changes
introduced by the following change:
rnndb/dsi: Add more bits for DSI PHY
More registers and bit fields are added for PHY timings
and bitclk source selection.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm
On a certain platform, only one type of DSI PHY is used.
This change allows the user to only compile the PHY type
which is being used.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/Kconfig | 14 ++
drivers/gpu/drm/msm/Makefile | 11
We are not checking the return value from msm_dsi_phy_disable().
Change the return type to void.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 +-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +---
2 files changed, 6 insertions(+), 12 deletions
AHB clock should be enabled before accessing registers during
enable/disable_vblank(). Since these 2 callbacks are called in
atomic context while clk_prepare may cause thread sleep, a work
is scheduled to control vblanks.
v2: fixup spinlock initialization
Signed-off-by: Hai Li
---
drivers/gpu
AHB clock should be enabled before accessing registers during
enable/disable_vblank(). Since these 2 callbacks are called in
atomic context while clk_prepare may cause thread sleep, a work
is scheduled to control vblanks.
v2: fixup spinlock initialization
Signed-off-by: Hai Li h
AHB clock should be enabled before accessing registers during
enable/disable_vblank(). Since these 2 callbacks are called in
atomic context while clk_prepare may cause thread sleep, a work
is scheduled to control vblanks.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c | 9
AHB clock should be enabled before accessing registers during
enable/disable_vblank(). Since these 2 callbacks are called in
atomic context while clk_prepare may cause thread sleep, a work
is scheduled to control vblanks.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp4
Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.
v2: Rebase on clk-next and avoid build warning
Signed-off-by: Hai Li
Tested-by: Archit Taneja
Fixes
Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.
v2: Rebase on clk-next and avoid build warning
Signed-off-by: Hai Li h...@codeaurora.org
Tested-by: Archit
to match HW status with cached status
in clock driver.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.h | 9 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 21 +++
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 42 +-
drivers/gpu/drm/msm
to match HW status with cached status
in clock driver.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi.h | 9 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 21 +++
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 42
This change takes advantage of a HW feature that synchronize
flush operation on CTL1 to CTL0, to keep dual DSI pipes in
sync.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 140
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 4 +-
drivers
is to
associate a CTL with each interface.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 12 --
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 26 +++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 49 +
drivers/gpu/drm/msm/mdp/mdp5
Instead of allocating CTL for each CRTC, we start to associate CTL
to each display interface, which reflects real HW requirement.
It also helps in making use of HW single FLUSH feature to sync
between dual DSI pipes.
Hai Li (2):
drm/msm/mdp5: Allocate CTL for each display interface
drm/msm
is to
associate a CTL with each interface.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 12 --
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 26 +++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 49 +
drivers/gpu
Instead of allocating CTL for each CRTC, we start to associate CTL
to each display interface, which reflects real HW requirement.
It also helps in making use of HW single FLUSH feature to sync
between dual DSI pipes.
Hai Li (2):
drm/msm/mdp5: Allocate CTL for each display interface
drm/msm
This change takes advantage of a HW feature that synchronize
flush operation on CTL1 to CTL0, to keep dual DSI pipes in
sync.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 140
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h
Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.
Signed-off-by: Hai Li
---
drivers/clk/qcom/clk-rcg2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Since the parent rate has been recalculated, pixel RCG clock
should rely on it to find the correct M/N values during set_rate,
instead of calling __clk_round_rate() to its parent again.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/clk/qcom/clk-rcg2.c | 3 ++-
1 file changed, 2
and treat it as the whole pipe's limitation for MDP5. The size
limit on MDP4 is not changed.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 5 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 ++
drivers/gpu/drm/msm/mdp/mdp5
and treat it as the whole pipe's limitation for MDP5. The size
limit on MDP4 is not changed.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 5 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 ++
drivers/gpu
DSI controller on msm8x94 is version 1.3, which requires different
power supplies and works with 20nm DSI PHY. This change is to add
the basic support for this version.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 ++
drivers/gpu/drm/msm/dsi/dsi.h
Hai Li (2):
drm/msm/dsi: Update generated headers with 20nm PHY support
drm/msm/dsi: Add support for msm8x94
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 192
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 192 +++---
1 file changed, 181 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 9791ea0..9bb63a9 100644
--- a/drivers/gpu/drm
This change introduces new domains of PHY and PHY_REGULATOR
for 20nm DSI PHY registers.
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 91 +++
1 file changed, 91 insertions(+)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index d19bea9
This change introduces new domains of PHY and PHY_REGULATOR
for 20nm DSI PHY registers.
Signed-off-by: Hai Li h...@codeaurora.org
---
rnndb/dsi/dsi.xml | 91 +++
1 file changed, 91 insertions(+)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 192 +++---
1 file changed, 181 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 9791ea0..9bb63a9 100644
Hai Li (2):
drm/msm/dsi: Update generated headers with 20nm PHY support
drm/msm/dsi: Add support for msm8x94
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 +
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 192
DSI controller on msm8x94 is version 1.3, which requires different
power supplies and works with 20nm DSI PHY. This change is to add
the basic support for this version.
Signed-off-by: Hai Li h...@codeaurora.org
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 ++
drivers/gpu/drm/msm
Some targets use pinctrl framework to configure some
pins. This change allows DSI driver to set default and
sleep pinctrl status.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 +++
drivers/gpu/drm/msm/dsi/dsi_host.c| 12
2
Some targets use pinctrl framework to configure some
pins. This change allows DSI driver to set default and
sleep pinctrl status.
Signed-off-by: Hai Li h...@codeaurora.org
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 7 +++
drivers/gpu/drm/msm/dsi/dsi_host.c| 12
The current term of *dual panel* in DSI driver code causes confusion.
It is supposed to indicate the panel using two DSI links. Rename it
to *dual DSI*.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 12 ++--
drivers/gpu/drm/msm/dsi/dsi_manager.c | 84
manager and PHY.
With this change, PLL selection can be supported on different
targets.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.h | 14 +-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 ++-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 34
These changes are for code cleanup and better support new targets in the future.
Hai Li (2):
drm/msm/dsi: Update source PLL selection in DSI PHY
drm/msm/dsi: Rename *dual panel* to *dual DSI*
Documentation/devicetree/bindings/drm/msm/dsi.txt | 12 +--
drivers/gpu/drm/msm/dsi/dsi.h
manager and PHY.
With this change, PLL selection can be supported on different
targets.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi.h | 14 +-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 15 ++-
drivers/gpu/drm/msm/dsi/dsi_phy.c | 34
The current term of *dual panel* in DSI driver code causes confusion.
It is supposed to indicate the panel using two DSI links. Rename it
to *dual DSI*.
Signed-off-by: Hai Li h...@codeaurora.org
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 12 ++--
drivers/gpu/drm/msm/dsi
These changes are for code cleanup and better support new targets in the future.
Hai Li (2):
drm/msm/dsi: Update source PLL selection in DSI PHY
drm/msm/dsi: Rename *dual panel* to *dual DSI*
Documentation/devicetree/bindings/drm/msm/dsi.txt | 12 +--
drivers/gpu/drm/msm/dsi/dsi.h
DSI video mode engine can only take active-high sync signals. This
change prevents MDP5 sending active-low sync signals to DSI in any
case.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git
DSI video mode engine can only take active-high sync signals. This
change prevents MDP5 sending active-low sync signals to DSI in any
case.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 12
1 file changed, 8 insertions(+), 4 deletions
and clock consumer make DSI driver better fit into
common clock framework.
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 59 +++--
drivers/gpu/drm/msm/dsi/dsi.c | 45 +++-
drivers/gpu/drm/msm/dsi/dsi.h | 25 +-
drivers/gpu/drm/msm
This change activates PLL driver for DSI to work with
common clock framework.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.c | 14 +++
drivers/gpu/drm/msm/dsi/dsi.h | 43 ---
drivers/gpu/drm/msm/dsi/dsi_host.c| 60
DSI byte clock and pixel clocks are sourced from DSI PLL.
This change adds the DSI PLL source clock driver under
common clock framework.
This change handles DSI 28nm PLL only.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
Signed-off-by: Stephane Viau
Signed-off-by: Wentao Xu
DSI PLL driver can work with common clock framework and provide source of DSI
byte clock and pixel clock, as a clock provider.
Hai Li (3):
drm/msm/dsi: Add DSI PLL clock driver support
drm/msm/dsi: Enable PLL driver in MSM DSI
drm/msm/dsi: Separate PHY to another platform device
This change activates PLL driver for DSI to work with
common clock framework.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi.c | 14 +++
drivers/gpu/drm/msm/dsi/dsi.h | 43 ---
drivers/gpu/drm/msm/dsi/dsi_host.c| 60
DSI byte clock and pixel clocks are sourced from DSI PLL.
This change adds the DSI PLL source clock driver under
common clock framework.
This change handles DSI 28nm PLL only.
Signed-off-by: Hai Li h...@codeaurora.org
Signed-off-by: Archit Taneja arch...@codeaurora.org
Signed-off-by: Stephane
and clock consumer make DSI driver better fit into
common clock framework.
Signed-off-by: Hai Li h...@codeaurora.org
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 59 +++--
drivers/gpu/drm/msm/dsi/dsi.c | 45 +++-
drivers/gpu/drm/msm/dsi/dsi.h | 25
DSI PLL driver can work with common clock framework and provide source of DSI
byte clock and pixel clock, as a clock provider.
Hai Li (3):
drm/msm/dsi: Add DSI PLL clock driver support
drm/msm/dsi: Enable PLL driver in MSM DSI
drm/msm/dsi: Separate PHY to another platform device
for more bit fields
- Rebase on change "rnndb: dsi: Add DSI_LANE_CTRL info"
Signed-off-by: Stephane Viau
Signed-off-by: Hai Li
---
rnndb/dsi/dsi.xml | 80 +
rnndb/edp/edp.xml | 51 ++
rnndb/hdmi/hdm
registers
may not be implemented the same way for each interface PHY.
v2:
- Add description for more bit fields
- Rebase on change "rnndb: dsi: Add DSI_LANE_CTRL info"
Signed-off-by: Stephane Viau
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.xml
:
- Add description for more bit fields
- Rebase on change rnndb: dsi: Add DSI_LANE_CTRL info
Signed-off-by: Stephane Viau sv...@codeaurora.org
Signed-off-by: Hai Li h...@codeaurora.org
---
rnndb/dsi/dsi.xml | 80 +
rnndb/edp/edp.xml | 51
registers
may not be implemented the same way for each interface PHY.
v2:
- Add description for more bit fields
- Rebase on change rnndb: dsi: Add DSI_LANE_CTRL info
Signed-off-by: Stephane Viau sv...@codeaurora.org
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm
the data type to detect error.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 473d417..72d4d5f 100644
--- a/drivers/gpu
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index fdc54e3..473d417 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi
These 2 patches are to fix the issues during DSI command rx.
Hai Li (2):
drm/msm/dsi: Fixup missing *break* statement during cmd rx
drm/msm/dsi: Simplify the code to get the number of read byte
drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +--
1 file changed, 5 insertions(+), 10
These 2 patches are to fix the issues during DSI command rx.
Hai Li (2):
drm/msm/dsi: Fixup missing *break* statement during cmd rx
drm/msm/dsi: Simplify the code to get the number of read byte
drivers/gpu/drm/msm/dsi/dsi_host.c | 15 +--
1 file changed, 5 insertions(+), 10
the data type to detect error.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 473d417..72d4d5f
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index fdc54e3..473d417 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu
*_wait_for_commit_done
functions to wait for FLUSH register cleared at vsync, before commit
completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 39 ++
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 1
flag to differentiate cmd mode wait
function from video mode. (From Rob Clark)
Hai Li (2):
drm/msm: Use customized function to wait for atomic commit done
drm/msm/mdp5: Wait for PP_DONE irq for command mode CRTC atomic commit
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c| 39
CRTCs in DSI command mode data path should wait for pingpong done,
instead of vblank, to finish atomic commit.
This change is to enable PP_DONE irq on command mode CRTCs and wait for
this irq happens before atomic commit completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5
*_wait_for_commit_done
functions to wait for FLUSH register cleared at vsync, before commit
completion.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 39 ++
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7
drivers/gpu/drm/msm/mdp/mdp4
flag to differentiate cmd mode wait
function from video mode. (From Rob Clark)
Hai Li (2):
drm/msm: Use customized function to wait for atomic commit done
drm/msm/mdp5: Wait for PP_DONE irq for command mode CRTC atomic commit
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c| 39
CRTCs in DSI command mode data path should wait for pingpong done,
instead of vblank, to finish atomic commit.
This change is to enable PP_DONE irq on command mode CRTCs and wait for
this irq happens before atomic commit completion.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm
*_wait_for_commit_done
functions to wait for FLUSH register cleared at vsync, before commit
completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 46
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 1
The current way to wait for atomic commit done may cause unnecessary wait for
another vsync for video mode path. Also, for command mode path, we need to wait
for PP_DONE event other than vsync before finish. This patch series is to fix
these issues.
Hai Li (2):
drm/msm: Use customized function
CRTCs in DSI command mode data path should wait for pingpong done,
instead of vblank, to finish atomic commit.
This change is to enable PP_DONE irq on command mode CRTCs and wait for
this irq happens before atomic commit completion.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/mdp/mdp5
CRTCs in DSI command mode data path should wait for pingpong done,
instead of vblank, to finish atomic commit.
This change is to enable PP_DONE irq on command mode CRTCs and wait for
this irq happens before atomic commit completion.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm
The current way to wait for atomic commit done may cause unnecessary wait for
another vsync for video mode path. Also, for command mode path, we need to wait
for PP_DONE event other than vsync before finish. This patch series is to fix
these issues.
Hai Li (2):
drm/msm: Use customized function
*_wait_for_commit_done
functions to wait for FLUSH register cleared at vsync, before commit
completion.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 46
drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 7
drivers/gpu/drm/msm/mdp/mdp4
drm_mode_connector_attach_encoder() function call is missing
during eDP and DSI connector initialization. As a result,
no encoder is returned by DRM_IOCTL_MODE_GETCONNECTOR system
call. This change is to fix this issue.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/dsi/dsi.c | 10
drm_mode_connector_attach_encoder() function call is missing
during eDP and DSI connector initialization. As a result,
no encoder is returned by DRM_IOCTL_MODE_GETCONNECTOR system
call. This change is to fix this issue.
Signed-off-by: Hai Li h...@codeaurora.org
---
drivers/gpu/drm/msm/dsi/dsi.c
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/edp.txt | 61 +++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/msm/edp.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/edp.txt
b/Documentation
Signed-off-by: Hai Li
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/msm/dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt
b/Documentation
Signed-off-by: Hai Li h...@codeaurora.org
---
Documentation/devicetree/bindings/drm/msm/dsi.txt | 97 +++
1 file changed, 97 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/msm/dsi.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/dsi.txt
b
Signed-off-by: Hai Li h...@codeaurora.org
---
Documentation/devicetree/bindings/drm/msm/edp.txt | 61 +++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/drm/msm/edp.txt
diff --git a/Documentation/devicetree/bindings/drm/msm/edp.txt
b
Hi Djakov,
Georgi Djakov linaro.org> writes:
>
> In the current parent mapping code, we can get duplicate or
inconsistent
> indexes, which leads to discrepancy between the number of elements in
the
> array and the number of parents. Until now, this was solved with some
> reordering but this
Hi Djakov,
Georgi Djakov georgi.djakov at linaro.org writes:
In the current parent mapping code, we can get duplicate or
inconsistent
indexes, which leads to discrepancy between the number of elements in
the
array and the number of parents. Until now, this was solved with some
reordering
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
v3: Fix issues when initialization is failed
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
v3: Fix issues when initialization is failed
Signed-off-by: Hai Li h...@codeaurora.org
to not depend on msm_drm_sub_dev change
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Makefile| 3 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 4 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 343
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
This change adds the DSI connector support in msm drm driver.
v1: Initial change
v2:
- Address comments from Archit + minor clean-ups
- Rebase to not depend on msm_drm_sub_dev change [Rob's comment]
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/Kconfig | 11 +
drivers/gpu/drm/msm
Resending initial MSM DSI patches
DSI is supported by both mdp4 and mdp5. This patch series adds the common DSI
controller driver and also enable it in mdp5.
Hai Li (4):
drm/msm/mdp5: Move *_modeset_init out of construct_encoder function
drm/msm: Add split display interface
drm/msm: Initial
This change is to add an interface to MDP for connector devices
setting split display information.
Signed-off-by: Hai Li
---
drivers/gpu/drm/msm/msm_kms.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 3a78cb4..a9f17bd
1 - 100 of 156 matches
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