Initial Allwinner T3 support.
Allwinner T3 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU, and a
Mali400 MP2 GPU from ARM. It is a not-pin-compatible quad core sucessor
of the A20). It's also known as the Allwinner R40.
Hao Zhang (2):
ARM: dts: sun8i: Add board dts file for t3-cqa3
2018-05-15 19:17 GMT+08:00 Maxime Ripard :
> Hi,
>
> On Mon, May 14, 2018 at 10:45:44PM +0800, Hao Zhang wrote:
>> 2018-02-26 17:00 GMT+08:00 Maxime Ripard :
>> > Thanks for respinning this serie. It looks mostly good, but you still
>> > have a quite significa
2018-02-28 9:53 GMT+08:00 André Przywara :
> Hi,
>
> The subject line should mention the R40, there are far too many sun8i SoCs.
Okey.
>
> On 25/02/18 13:51, hao_zhang wrote:
>> This patch adds pwm node for sun8i.
>>
>> Signed-off-by: hao_zhang
>> ---
>> arch/arm/boot/dts/sun8i-r40.dtsi | 13 ++
ut the generic property).
>
> This would mean you don't need a SoC specific structure at all.
okey.
>
>> +};
>> +
>> +static const struct of_device_id sun8i_pwm_dt_ids[] = {
>> + {
>> + .compatible = "allwinner,sun8i-r40-pwm",
>> + .data = &sun8i_pwm_data_r40,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids);
>> +
>> +static int sun8i_pwm_probe(struct platform_device *pdev)
>> +{
>> + struct sun8i_pwm_chip *pwm;
>> + struct resource *res;
>> + int ret;
>> + const struct of_device_id *match;
>> +
>> + match = of_match_device(sun8i_pwm_dt_ids, &pdev->dev);
>> + if (!match) {
>> + dev_err(&pdev->dev, "Error: No device match found\n");
>> + return -ENODEV;
>> + }
>> +
>> + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
>> + if (!pwm)
>> + return -ENOMEM;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + pwm->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(pwm->base))
>> + return PTR_ERR(pwm->base);
>> +
>> + pwm->regmap = devm_regmap_init_mmio(&pdev->dev, pwm->base,
>> + &sun8i_pwm_regmap_config);
>> + if (IS_ERR(pwm->regmap)) {
>> + dev_err(&pdev->dev, "Failed to create regmap\n");
>> + return PTR_ERR(pwm->regmap);
>> + }
>> +
>> + pwm->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(pwm->clk))
>> + return PTR_ERR(pwm->clk);
>
> This would need to be extended to get multiple clocks.
okey.
>
>> +
>> + pwm->data = match->data;
>> + pwm->chip.dev = &pdev->dev;
>> + pwm->chip.ops = &sun8i_pwm_ops;
>> + pwm->chip.base = -1;
>> + pwm->chip.npwm = pwm->data->npwm;
>
> It should be fairly easy to initialise this from some DT property.
>
> That's it for the my first review round. Haven't checked the actual
> algorithm and bit assignments yet.
> Did you manage to test this?
Sure :-)
All has been tested on my T3 board (compatible V40, R40)
PWM signal is work well observe from oscilloscope.
>
> Cheers,
> Andre.
>
>> + pwm->chip.of_xlate = of_pwm_xlate_with_flags;
>> + pwm->chip.of_pwm_n_cells = 3;
>> +
>> + spin_lock_init(&pwm->ctrl_lock);
>> +
>> + ret = pwmchip_add(&pwm->chip);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "Failed to add PWM chip: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + platform_set_drvdata(pdev, pwm);
>> +
>> + return 0;
>> +}
>> +
>> +static int sun8i_pwm_remove(struct platform_device *pdev)
>> +{
>> + struct sun8i_pwm_chip *pwm = platform_get_drvdata(pdev);
>> +
>> + return pwmchip_remove(&pwm->chip);
>> +}
>> +
>> +static struct platform_driver sun8i_pwm_driver = {
>> + .driver = {
>> + .name = "sun8i-pwm",
>> + .of_match_table = sun8i_pwm_dt_ids,
>> + },
>> + .probe = sun8i_pwm_probe,
>> + .remove = sun8i_pwm_remove,
>> +};
>> +module_platform_driver(sun8i_pwm_driver);
>> +
>> +MODULE_ALIAS("platform: sun8i-pwm");
>> +MODULE_AUTHOR("Hao Zhang ");
>> +MODULE_DESCRIPTION("Allwinner sun8i PWM driver");
>> +MODULE_LICENSE("GPL v2");
>>
>
2018-02-26 17:00 GMT+08:00 Maxime Ripard :
> Hi,
>
> Thanks for respinning this serie. It looks mostly good, but you still
> have a quite significant number of checkpatch (--strict) warnings that
> you should address.
Thanks for reviews :) ,i'm sorry for that, it will be fixed next time.
and, besi
2018-01-15 16:38 GMT+08:00 Maxime Ripard :
> Hi,
>
> On Sun, Jan 14, 2018 at 02:43:39PM +0800, Hao Zhang wrote:
>> 2018-01-11 20:47 GMT+08:00 Maxime Ripard :
>> > On Thu, Jan 11, 2018 at 07:34:12PM +0800, hao_zhang wrote:
>> >> This patch add pwm node for r40.
possible, and if we just apply this patch the DT will not compile
> anymore.
>
> Your patch 4 should come before this one.
>
Do you mean that the order of patch be applied is from the first to
the last in the patch set ?
because you apply the last patch first also break the DT compile...
nction = "pwm";
};
pwm1_pin: pwm1-pin {
pins = "PB3";
function = "pwm";
};
the node of pwm2~7 should also be added here?
On sun8i-r40-bananapi-m2-ultra.dts:
because of the special customize board, i think just add pinctrl-0 = <&pwm0_pin>
(PB3 I jus
2017-12-13 23:45 GMT+08:00 Maxime Ripard :
> Hi,
>
> Thanks for your patch!
>
> On Wed, Dec 13, 2017 at 10:47:48PM +0800, hao_zhang wrote:
>> Pin function can not be match correctly when SUNXI_PIN describe with
>> mutiple variant and same function.
>>
>> such as:
>> on pinctrl-sun4i-a10.c
>>
>> SUN
ction called by dmaengine_slave_config,
and test the configuration whether is support for the device.
Signed-off-by: Hao Zhang
---
drivers/dma/sun6i-dma.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/
Accroding to the Allwinner_A64_User_Manual_V1.0 P198
the DMA base address is 0x01c02000.
Signed-off-by: Hao Zhang
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts
dma and add the buswidth test, thinks!
It has test on Pine64 using dmatest.
Regards :)
Hao Zhang (3):
Documentation: DT: add dma compatible for sun50i A64 SOC
ARM64: dts: sun6i: add dma node for a64.
dmaengine: sun6i: share the dma driver with sun50i
.../devicetree/bindings/dma/sun6i
This add the property of Allwinner sun50i A64 dma.
Signed-off-by: Hao Zhang
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
dma_pool_alloc does not initialize the value of the newly allocated
block for the v_lli, and the uninitilize value make the tests failed
which is on pine64 with dmatest.
we can fix it just change the "|=" to "=" for the v_lli->cfg.
Signed-off-by: Hao Zhang
---
v1: https:
According to the datasheet, the dma of A64 support 8/16/32/64 bits
so, we can add the condition of device compatible in convert_buswidth
function and other place to determine the device whether is for A64,
and then accept the 8 bytes bus width to it.
Signed-off-by: Hao Zhang
---
drivers/dma
This adds documentation of the sun50i a64 dma binding compatible.
Signed-off-by: Hao Zhang
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
b/Documentation/devicetree/bindings/dma
This adds the dma node for sun50i a64.
Signed-off-by: Hao Zhang
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index e3c3d7d8..855ae2c
Add soc a64 dma support.
Signed-off-by: Hao Zhang
---
drivers/dma/sun6i-dma.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 8346199..00fcfc7 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
clocks, device tree and other support for a64 is not merged,
this patch does not contain the support about them.
It has been test on pin64 using dmatest.
Regards,
Hao Zhang
Hi, is there any mainline kernel or uboot for hisilicon hi3520dv200 or
hi3520dv300? just want some base support to boot , anything close to
mainline is ok :)
2016-10-29 14:13 GMT+08:00 Jiancheng Xue :
> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
> Generator) module generates clock and
e
and Banana PI BPI-M1 supports?
5.the maintainer doesn't has the device, how do they know the driver
is work well on my board? just buit without error or warning ?
Best regards :)
Hao Zhang
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