[tip:perf/core] perf/x86/intel/uncore: Add Knights Landing uncore PMU support

Commit-ID: 77af0037de0a280eeabc632890de871f062ea7be Gitweb: http://git.kernel.org/tip/77af0037de0a280eeabc632890de871f062ea7be Author: Harish Chegondi AuthorDate: Mon, 7 Dec 2015 14:32:32 -0800 Committer: Ingo Molnar CommitDate: Wed, 6 Jan 2016 11:15:38 +0100 perf/x86/intel/uncore

[tip:perf/core] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

Commit-ID: 1e7b93906249a7ccca730be03168ace15f95709e Gitweb: http://git.kernel.org/tip/1e7b93906249a7ccca730be03168ace15f95709e Author: Harish Chegondi AuthorDate: Mon, 7 Dec 2015 14:28:18 -0800 Committer: Ingo Molnar CommitDate: Wed, 6 Jan 2016 11:15:37 +0100 perf/x86/intel: Add perf

[tip:perf/core] perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset

Commit-ID: dae25530a44ad9e6523495ebc8b37bb0a1640490 Gitweb: http://git.kernel.org/tip/dae25530a44ad9e6523495ebc8b37bb0a1640490 Author: Harish Chegondi AuthorDate: Mon, 7 Dec 2015 14:32:31 -0800 Committer: Ingo Molnar CommitDate: Wed, 6 Jan 2016 11:15:37 +0100 perf/x86/intel/uncore

Re: [PATCH 2/2] perf/x86/intel/uncore: Add Knights Landing uncore PMU support

On 12/09/2015 03:37 PM, Peter Zijlstra wrote: > On Wed, Dec 09, 2015 at 01:03:43PM -0800, Harish Chegondi wrote: >> >> On 12/08/2015 01:07 AM, Peter Zijlstra wrote: >>> On Mon, Dec 07, 2015 at 02:32:32PM -0800, Harish Chegondi wrote: >>>> @@ -981,6 +990,8

Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

On 12/09/2015 03:37 PM, Peter Zijlstra wrote: > On Wed, Dec 09, 2015 at 03:22:29PM -0800, Harish Chegondi wrote: > >> On 12/08/2015 12:37 AM, Peter Zijlstra wrote: >>> On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote: >>>> Knights Landing core

Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

On 12/08/2015 12:37 AM, Peter Zijlstra wrote: > On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote: >> Knights Landing core is based on Silvermont core with several differences. >> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the >> LBR

Re: [PATCH 2/2] perf/x86/intel/uncore: Add Knights Landing uncore PMU support

On 12/08/2015 01:07 AM, Peter Zijlstra wrote: > On Mon, Dec 07, 2015 at 02:32:32PM -0800, Harish Chegondi wrote: >> @@ -981,6 +990,8 @@ static int __init uncore_pci_init(void) >> break; >> case 61: /* Broadwell */ >> ret = bdw_uncore_

[PATCH 1/2] perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset

Call uncore_pci_box_ctl() function to get the PMON box control MSR offset instead of hard coding the offset. This would allow us to use this snbep_uncore_pci_init_box() function for other PCI PMON devices whose box control MSR offset is different from SNBEP_PCI_PMON_BOX_CTL. Signed-off-by: Harish

[PATCH 2/2] perf/x86/intel/uncore: Add Knights Landing uncore PMU support

intel/uncore: Remove hard coding of PMON box control MSR offset"). Signed-off-by: Harish Chegondi Cc: Andi Kleen Cc: Kan Liang Cc: Lukasz Anaczkowski --- arch/x86/kernel/cpu/perf_event_intel_uncore.h | 3 + arch/x86/kernel/cpu/perf_event_intel_uncore.c | 13 + arch/x86/

[PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing

E2%84%A2x200ProcessorPerformanceMonitoringReferenceManual_Volume1_Registers_v0%206.pdf Signed-off-by: Harish Chegondi Cc: Andi Kleen Cc: Kan Liang Cc: Lukasz Anaczkowski --- arch/x86/kernel/cpu/perf_event.h | 2 + arch/x86/kernel/cpu/perf_event_intel.c | 62 ++ arc