[PATCHv16 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

u/drm/ivip/intel_vip_drv.h diff --git a/MAINTAINERS b/MAINTAINERS index e7e81fadff65..0fdec52a356a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5229,6 +5229,15 @@ L: dri-de...@lists.freedesktop.org F: include/drm/ttm/ F: drivers/gpu/drm/ttm/ +DRM INTEL IVIP +M: Hean Loon

[PATCHv16 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: "Ong, Hean Loong" Device tree binding for Intel FPGA Video and Image Processing Suite. The bindings would set the max width, max height, bits per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr.

[PATCHv14 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The bindings would set the max width, max height, bits per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr. V12:

[PATCHv13 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git

[PATCHv13 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The bindings would set the max width, max height, bits per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr. V12:

[PATCHv13 0/3] Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the Sodt IP

[PATCHv13 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv12 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The bindings would set the max width, max height, bits per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr.

[PATCHv12 0/3] Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the Sodt

[PATCHv12 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git

[PATCHv12 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Signed-off-by: Ong, Hean Loong --- drivers/gpu/drm/Kconfig |2 + drivers/gpu/drm/Makefile |1 + drivers/gpu/drm/ivip/Kconfig | 14 +++ drivers/gpu/drm/ivip/Makefile |7 ++ drivers/gpu/drm/ivip/intel_vip_conn.c |

[PATCHv11 0/3] Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv11 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git

[PATCHv11 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports

[PATCHv11 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Signed-off-by: Ong, Hean Loong --- drivers/gpu/drm/ivip/Kconfig | 14 +++ drivers/gpu/drm/ivip/Makefile |7 ++ drivers/gpu/drm/ivip/intel_vip_conn.c | 91 drivers/gpu/drm/ivip/intel_vip_core.c | 189

[PATCHv<8> 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv<8> 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv<8> 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig |5 + 1 files changed, 5

[PATCHv<8> 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git

[PATCHv<8> 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device

[PATCHv<8> 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports

[PATCHv<8> 0/3] Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to

[PATCHv<8> 0/3] Intel FPGA Video and Image Processing Suite

From: Ong, Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv7] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height and memory port width. The device tree binding only

[PATCHv7] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height and memory port width. The device tree binding only supports the Intel Arria10

[PATCHv7 0/3] Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be

[PATCHv7 0/3] Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv7 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv7 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6

[PATCHv7 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv7 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv6 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6

[PATCHv6 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCHv6 0/3]

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to

[PATCHv6 0/3]

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree

[PATCHv6 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the

[PATCHv5 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6

[PATCHv5 0/3] Intel FPGA VIP Frame Buffer II drm driver

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to

[PATCHv5 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCHv5 0/3] Intel FPGA VIP Frame Buffer II drm driver

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv5 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Signed-off-by: Ong Hean Loong --- V5: *Fix Comments V4: *Fix Comments V3: *Changes to fixing drm_simple_pipe *Used drm_fb_cma_get_gem_addr V2: *Adding drm_simple_display_pipe_init --- drivers/gpu/drm/Kconfig

[PATCHv5 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Signed-off-by: Ong Hean Loong --- V5: *Fix Comments V4: *Fix Comments V3: *Changes to fixing drm_simple_pipe *Used drm_fb_cma_get_gem_addr V2: *Adding drm_simple_display_pipe_init --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile

[PATCHv5 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree

[PATCHv5 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the

[PATCHv4 3/3] DRM:ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv4 3/3] DRM:ivip Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv4 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6

[PATCHv4 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCHv4 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree

[PATCHv4 1/3] ARM:dt-bindings Intel FPGA Video and Image Processing Suite

From: Ong Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the

[PATCHv4 0/3] Intel FPGA VIP Frame Buffer II drm driver

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to

[PATCHv4 0/3] Intel FPGA VIP Frame Buffer II drm driver

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv3 0/3] Intel FPGA VIP Frame Buffer II drm driver

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels

[PATCHv3 0/3] Intel FPGA VIP Frame Buffer II drm driver

From: Ong Hean Loong The FPGA FrameBuffer Soft IP could be seen as the GPU and the DRM driver patch here is allocating memory for information to be streamed from the ARM/Linux to the display port. Basically the driver just wraps the information such as the pixels to be drawn by the FPGA

[PATCHv3 2/3] ARM: socfpga: drm driver updates in socfpga_defconfig

From: "Ong, Hean Loong" Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6

[PATCHv3 1/3] dt-bindings: display: Intel FPGA VIP drm driver Devicetree bindings

From: "Ong, Hean Loong" Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device

[PATCHv3 2/3] ARM: socfpga: drm driver updates in socfpga_defconfig

From: "Ong, Hean Loong" Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git

[PATCHv3 1/3] dt-bindings: display: Intel FPGA VIP drm driver Devicetree bindings

From: "Ong, Hean Loong" Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports

[PATCHv3 3/3] ARM: drm: Intel FPGA VIP Frame Buffer II drm driver

From: "Ong, Hean Loong" Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at:

[PATCHv3 3/3] ARM: drm: Intel FPGA VIP Frame Buffer II drm driver

From: "Ong, Hean Loong" Driver for Intel FPGA Video and Image Processing Suite Frame Buffer II. The driver only supports the Intel Arria10 devkit and its variants. This driver can be either loaded staticlly or in modules. The OF device tree binding is located at: