> s/FILER/FILTER?
executed,thanks
hopefully no silly mistakes anymore
> s/FILER/FILTER?
executed,thanks
hopefully no silly mistakes anymore
upport')
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
Signed-off-by: Lawrence F Meadows <lawrence.f.mead...@intel.com>
---
arch/x86/events/intel/uncore_snbep.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/events/intel/uncore_snbep.c
b/arc
From: hchrzani
CHA events in Knights Landing platform require programming filter registers
properly.
Remote node, local node and NonNearMemCachable bits should be set to 1 at all
times.
Fixes: 77af003 ('perf/x86/intel/uncore: Add Knights Landing uncore PMU support')
Signed-off-by: Hubert
Patch corrects a typo introduced previously.
As a result under some configurations dimms were not
correctly recognized. Problem affects only Xeon Phi architecture.
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
---
drivers/edac/sb_edac.c | 2 +-
1 file changed, 1 insertion
Patch corrects a typo introduced previously.
As a result under some configurations dimms were not
correctly recognized. Problem affects only Xeon Phi architecture.
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Knights Landing does not come with register that could be used
to fetch DIMM width. However the value is fixed for this architecture
so it can be hardcoded.
Fixes: d0cdf900314 (sb_edac: Add Knights Landing (Xeon Phi gen 2) support)
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 8
Knights Landing does not come with register that could be used
to fetch DIMM width. However the value is fixed for this architecture
so it can be hardcoded.
Fixes: d0cdf900314 (sb_edac: Add Knights Landing (Xeon Phi gen 2) support)
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 8
Knights Landing does not come with register that could be used
to fetch DIMM width. However the value is fixed for this architecture
so it can be hardcoded.
Fixes: d0cdf900314 (sb_edac: Add Knights Landing (Xeon Phi gen 2) support)
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.
Knights Landing does not come with register that could be used
to fetch DIMM width. However the value is fixed for this architecture
so it can be hardcoded.
Fixes: d0cdf900314 (sb_edac: Add Knights Landing (Xeon Phi gen 2) support)
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.
From: Jim Snow
SAD limit, interleave mode and DRAM related functionalities
are now virtualized, so that overriding them is easier.
Signed-off-by: Jim Snow
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 59
From: Jim Snow
Add options to sbridge_get_all_devices to allow
for duplicate device IDs and devices that are scattered
across mulitple PCI buses.
Signed-off-by: Jim Snow
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 40
From: Jim Snow
Make EDAC aware of DDR4/RDDR4 mem types.
Signed-off-by: Jim Snow
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk
---
include/linux/edac.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/linux/edac.h b
Series of patches that enable support for Knights Landing processor which is
based on Silvermont microarchitecture.
First 3 patches are pretty much straightforward and self-explantory.
Last one is the biggest, however, is logically consistent and breaking into
many smaller patches does not make
.
which channels are populated with what DIMM sizes
(knl_get_dimm_capacity function)
() handle MCE errors - channel swizzling
Reviewed-by: Tony Luck
Signed-off-by: Jim Snow
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 966
From: Jim Snow <jim.m.s...@intel.com>
SAD limit, interleave mode and DRAM related functionalities
are now virtualized, so that overriding them is easier.
Signed-off-by: Jim Snow <jim.m.s...@intel.com>
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hube
rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
---
drivers/edac/sb_edac.c | 966 ++---
1 file changed, 921 insertions(+), 45 deletions(-)
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index c8fbde2..b3d9
Series of patches that enable support for Knights Landing processor which is
based on Silvermont microarchitecture.
First 3 patches are pretty much straightforward and self-explantory.
Last one is the biggest, however, is logically consistent and breaking into
many smaller patches does not make
From: Jim Snow <jim.m.s...@intel.com>
Make EDAC aware of DDR4/RDDR4 mem types.
Signed-off-by: Jim Snow <jim.m.s...@intel.com>
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
---
include/linux/edac.h | 6 --
From: Jim Snow <jim.m.s...@intel.com>
Add options to sbridge_get_all_devices to allow
for duplicate device IDs and devices that are scattered
across mulitple PCI buses.
Signed-off-by: Jim Snow <jim.m.s...@intel.com>
[hubert.chrzan...@intel.com: patch rebase to 4.4-rc3]
Signed-of
From: Jim Snow
Add options to sbridge_get_all_devices to allow
for duplicate device IDs and devices that are scattered
across mulitple PCI buses.
Signed-off-by: Jim Snow
Signed-off-by: Lukasz Anaczkowski
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 40
From: Jim Snow
SAD limit, interleave mode and DRAM related functionalities
are now virtualized, so that overriding them is easier.
Signed-off-by: Jim Snow
Signed-off-by: Lukasz Anaczkowski
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 59
.
which channels are populated with what DIMM sizes
(knl_get_dimm_capacity function)
() handle MCE errors - channel swizzling
Reviewed-by: Tony Luck
Signed-off-by: Jim Snow
Signed-off-by: Lukasz Anaczkowski
Signed-off-by: Hubert Chrzaniuk
---
drivers/edac/sb_edac.c | 966
From: Jim Snow
Make EDAC aware of DDR4/RDDR4 mem types.
Signed-off-by: Jim Snow
Signed-off-by: Lukasz Anaczkowski
Signed-off-by: Hubert Chrzaniuk
---
include/linux/edac.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/linux/edac.h b/include/linux/edac.h
Series of patches that enable support for Knights Landing processor
which is based on Silvermont microarchitecture.
First 3 patches are pretty much straightforward and self-explantory.
Last one is the biggest, however, is logically consistent and breaking
into many smaller patches does not make
i <lukasz.anaczkow...@intel.com>
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
---
drivers/edac/sb_edac.c | 966 ++---
1 file changed, 921 insertions(+), 45 deletions(-)
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
Series of patches that enable support for Knights Landing processor
which is based on Silvermont microarchitecture.
First 3 patches are pretty much straightforward and self-explantory.
Last one is the biggest, however, is logically consistent and breaking
into many smaller patches does not make
From: Jim Snow <jim.m.s...@intel.com>
Make EDAC aware of DDR4/RDDR4 mem types.
Signed-off-by: Jim Snow <jim.m.s...@intel.com>
Signed-off-by: Lukasz Anaczkowski <lukasz.anaczkow...@intel.com>
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
---
include/li
From: Jim Snow <jim.m.s...@intel.com>
SAD limit, interleave mode and DRAM related functionalities
are now virtualized, so that overriding them is easier.
Signed-off-by: Jim Snow <jim.m.s...@intel.com>
Signed-off-by: Lukasz Anaczkowski <lukasz.anaczkow...@intel.com>
Sig
com>
Signed-off-by: Hubert Chrzaniuk <hubert.chrzan...@intel.com>
---
drivers/edac/sb_edac.c | 40
1 file changed, 32 insertions(+), 8 deletions(-)
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 2e50a3e..c8fbde2 100644
--- a/driv
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