Re: [PATCHv2 5/5] clk: samsung: exynos5410: Added clocks DPLL, EPLL, IPLL, and VPLL

Hi, On Thu, Jul 31, 2014 at 5:19 PM, Tomasz Figa wrote: > > I'm not sure I get the idea of the field you're suggesting. If I > understand correctly, your intention would be to provide a default > frequency if there is no table provided. I don't think there is a need > for it, because current code

Re: [PATCHv2 4/5] clk: samsung: exynos5410: Add fixed rate clocks

Hi, On Thu, Jul 31, 2014 at 1:45 PM, Sylwester Nawrocki wrote: > Can you explain what is rationale behind this change ? Is it related to > suspend/resume ordering ? I had forgotten, but now remember the reason why I did this. If you see the current implementation of clk-exynos5410, you will noti

Re: [PATCHv2 5/5] clk: samsung: exynos5410: Added clocks DPLL, EPLL, IPLL, and VPLL

Hi Tomasz, I remember checking these rates on my calculator. You might notice the odd frequency of 45158401Hz (no pun intended) in the EPLL clock. This particular clock frequency was giving me a big headache in a previous project, since it was wrongly listed as 45158400. At first it seems innocuou

Re: [PATCHv2 4/5] clk: samsung: exynos5410: Add fixed rate clocks

Hi Tomasz, I perfectly see your point. However my question was why you did you decide to postpone Sylwester's? Was there any specific reason? I suppose it would break all the dtb compatibility, but besides that, was there any other reason? Best, Humberto On Thu, Jul 31, 2014 at 2:53 PM, Tomasz F

Re: [PATCHv2 1/5] clk: samsung: exynos5410: Add NULL pointer checks in clock init

Hi, I am bit confused by your response: first you mentioned that I should remove the NULL check for variable np, but later on you suggested that I should rearrange the conditional statement to avoid adding more indentation. My guess is that I should remove that if statement altogether? Regarding