于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo <kv...@codeaurora.org> 写到:
>Icenowy Zheng <icen...@aosc.io> writes:
>
>> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to
>use
>> an out-of-band interrupt pin instead of SDIO in-band interrupt.
于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to
>use
>> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>>
>> Add the device tree bindi
endor prefix to allwinner and modify commit message]
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boo
-by: Icenowy Zheng
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
1 file changed, 3 insertions(+)
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng <icen...@aosc
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Acked-by: Rob
, then adds the interrupt to the device tree of
Orange Pi Zero.
Icenowy Zheng (1):
dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Sergey Matyukevich (1):
ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
.../bindings/net/wireless/allwinner,xr819.txt | 38
, then adds the interrupt to the device tree of
Orange Pi Zero.
Icenowy Zheng (1):
dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Sergey Matyukevich (1):
ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
.../bindings/net/wireless/allwinner,xr819.txt | 38
于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>>
于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard
写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>> + * are conservative values pro
于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +, Icenowy Zheng wrote:
>> + {
>> +vmmc-supply = <_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +
于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard
写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +0000, Icenowy Zheng wrote:
>> + {
>> +vmmc-supply = <_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +status = "okay";
&
power, reset, and boot control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Dropped the vcc5v0 regulator, a
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet
00 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
arch/arm/boot/dts/sun8i-r40.dtsi
. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
arch/arm/boot/dts/sun8i-r40.dtsi
于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Mon, Sep 25, 2017 at 10:12:09AM +, Icenowy Zheng wrote:
>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
><maxime.rip...@free-electrons.com> 写到:
>> >Hi,
>> &
于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard
写到:
>On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:
>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS support for Allwinner A64 SoC.
>>
>> As the thermal sensor drive
于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS support for Allwinner A64 SoC.
>>
>> As the thermal sensor driver is not yet implemented and some board
于 2017年9月25日 GMT+08:00 下午5:11:57, Quentin Schulz
<quentin.sch...@free-electrons.com> 写到:
>Hi Icenowy,
>
>On 20/09/2017 17:18, Icenowy Zheng wrote:
>> AXP803 PMIC features AC/USB/Battery power supplies.
>>
>> As we have now the device tree bindings for them,
于 2017年9月25日 GMT+08:00 下午5:11:57, Quentin Schulz
写到:
>Hi Icenowy,
>
>On 20/09/2017 17:18, Icenowy Zheng wrote:
>> AXP803 PMIC features AC/USB/Battery power supplies.
>>
>> As we have now the device tree bindings for them, add device tree
>> nodes for them.
&g
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-b
The DCDC2 regulator of the AXP803 PMIC is used for the voltage scaling
of the ARM cores on the A64 SoC.
Add this definition to enable it on Pine64.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4
1 file changed, 4 inse
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-b
The DCDC2 regulator of the AXP803 PMIC is used for the voltage scaling
of the ARM cores on the A64 SoC.
Add this definition to enable it on Pine64.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch
driver of A64, and the remaining patches
set up the device tree bits of the DVFS on Pine64.
Icenowy Zheng (3):
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
arm64: allwinner: a64: add CPU opp table
arm64: allwinner: a64: set CPU regulator for Pine64
.../arm64/boot/dts/allwinner
driver of A64, and the remaining patches
set up the device tree bits of the DVFS on Pine64.
Icenowy Zheng (3):
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
arm64: allwinner: a64: add CPU opp table
arm64: allwinner: a64: set CPU regulator for Pine64
.../arm64/boot/dts/allwinner
Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.
OPPs higher to 816MHz is temporarily dropped, to prevent overheat on
boards with AXP803 support and undervoltage on boards without AXP803
support.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/bo
Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.
OPPs higher to 816MHz is temporarily dropped, to prevent overheat on
boards with AXP803 support and undervoltage on boards without AXP803
support.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64
于 2017年9月21日 GMT+08:00 下午10:46:21, Jonathan Cameron
<jonathan.came...@huawei.com> 写到:
>On Wed, 20 Sep 2017 23:18:07 +0800
>Icenowy Zheng <icen...@aosc.io> wrote:
>
>> The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power
>inputs:
>> AC, USB an
于 2017年9月21日 GMT+08:00 下午10:46:21, Jonathan Cameron
写到:
>On Wed, 20 Sep 2017 23:18:07 +0800
>Icenowy Zheng wrote:
>
>> The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power
>inputs:
>> AC, USB and Battery.
>>
>> This patchset adds support fo
AXP803 PMIC features AC/USB/Battery power supplies.
As we have now the device tree bindings for them, add device tree
nodes for them.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
AXP803 PMIC features AC/USB/Battery power supplies.
As we have now the device tree bindings for them, add device tree
nodes for them.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot
-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..955f392af6a2
-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..955f392af6a2 100644
--- a/arch/arm64
As we have now support for AXP803 ADC/Battery, and the AC Power part of
AXP803 is the same as AXP22x, add MFD cells for these drivers.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/mfd/axp20x.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mfd/axp2
As we have now support for AXP803 ADC/Battery, and the AC Power part of
AXP803 is the same as AXP22x, add MFD cells for these drivers.
Signed-off-by: Icenowy Zheng
---
drivers/mfd/axp20x.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd
and GPADC channels
are complex and will be support after more investigation.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/iio/adc/axp20x_adc.c | 108 +++
1 file changed, 108 insertions(+)
diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/i
The AXP803 PMIC has battery support like other AXP PMICs, but with
different definition of max target charging voltage and constant
charging current.
Add support for AXP803 battery in axp20x-battery driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/power/supply/axp20x_bat
and GPADC channels
are complex and will be support after more investigation.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/axp20x_adc.c | 108 +++
1 file changed, 108 insertions(+)
diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
The AXP803 PMIC has battery support like other AXP PMICs, but with
different definition of max target charging voltage and constant
charging current.
Add support for AXP803 battery in axp20x-battery driver.
Signed-off-by: Icenowy Zheng
---
drivers/power/supply/axp20x_battery.c | 88
The ADC rate setup on AXP803 is more complex than AXP20x/22x.
As it's not a necessary setup, allow it to be skipped, to allow simpler
AXP803 support now.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/iio/adc/axp20x_adc.c | 6 --
1 file changed, 4 insertions(+), 2 del
The ADC rate setup on AXP803 is more complex than AXP20x/22x.
As it's not a necessary setup, allow it to be skipped, to allow simpler
AXP803 support now.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/axp20x_adc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
for the AXP803 Battery/USB power supplies. For AC
power supply the one on AXP803 is compatible with the one on AXP22x.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/power/supply/axp20x_battery.txt | 1 +
Documentation/devicetree/bindings/power/
for the AXP803 Battery/USB power supplies. For AC
power supply the one on AXP803 is compatible with the one on AXP22x.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/power/supply/axp20x_battery.txt | 1 +
Documentation/devicetree/bindings/power/supply/axp20x_usb_power.txt | 1 +
2
in this patchset because it's not
present on Pine series boards.
In order to enable battery monitoring the ADC for battery is also enabled
for AXs.
In order to enable battery monitoring the ADC for battery is also enabled
for AXP803.
Icenowy Zheng (7):
dt-bindings: add compatibles for AXP803 Battery/USB
in this patchset because it's not
present on Pine series boards.
In order to enable battery monitoring the ADC for battery is also enabled
for AXs.
In order to enable battery monitoring the ADC for battery is also enabled
for AXP803.
Icenowy Zheng (7):
dt-bindings: add compatibles for AXP803 Battery/USB
于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Mon, Sep 18, 2017 at 03:47:25PM +, icen...@aosc.io wrote:
>> 在 2017-09-18 16:30,Maxime Ripard 写道:
>> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
>>
于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard
写到:
>On Mon, Sep 18, 2017 at 03:47:25PM +, icen...@aosc.io wrote:
>> 在 2017-09-18 16:30,Maxime Ripard 写道:
>> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:
>> > > 于 2017年9月18日 GMT+08:00 下午3:3
于 2017年9月19日 GMT+08:00 下午4:20:19, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Mon, Sep 18, 2017 at 11:42:04PM +0800, Icenowy Zheng wrote:
>> Allwinner A64/H5 SoCs come with a SID controller like the one in H3,
>but
>> without the silicon bug that makes th
于 2017年9月19日 GMT+08:00 下午4:20:19, Maxime Ripard
写到:
>On Mon, Sep 18, 2017 at 11:42:04PM +0800, Icenowy Zheng wrote:
>> Allwinner A64/H5 SoCs come with a SID controller like the one in H3,
>but
>> without the silicon bug that makes the initial value at 0x200 wrong,
>so
>
Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but
without the silicon bug that makes the initial value at 0x200 wrong, so
the value at 0x200 can be directly read.
Add support for this kind of SID controller.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documen
Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but
without the silicon bug that makes the initial value at 0x200 wrong, so
the value at 0x200 can be directly read.
Add support for this kind of SID controller.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree
于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but has
>its
>> register re-arranged, the clock divider
于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard
写到:
>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but has
>its
>> register re-arranged, the clock divider moved to CCU (originally the
>>
readout register to be altered.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/iio/adc/sun4i-gpadc-iio.c | 123 +++---
1 file changed, 116 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc
readout register to be altered.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/sun4i-gpadc-iio.c | 123 +++---
1 file changed, 116 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 68926b986cd0
on A64 and H5 is like the one on H3, but with of
course different formula factors.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v4:
- Splitted out some code refactors.
- Code sequence changed back. (The gpadc_data went back to the start of
the source file)
drivers/iio/adc
on A64 and H5 is like the one on H3, but with of
course different formula factors.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Splitted out some code refactors.
- Code sequence changed back. (The gpadc_data went back to the start of
the source file)
drivers/iio/adc/sun4i-gpadc-iio.c | 48
some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Mention calibration data in commit message.
Changes in v3:
- Clock name changes.
- Splited out thermal zone addition.
arch/
are also not added yet.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3220da3ad790..687c6457d214 100644
--- a/arch/arm/boot/dts
some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v4:
- Mention calibration data in commit message.
Changes in v3:
- Clock name changes.
- Splited out thermal zone addition.
arch/arm/boot/dts/sun8i-h3.dtsi | 17
are also not added yet.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3220da3ad790..687c6457d214 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng <icen...@aosc
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen
SUN8I", not "SUN8I_A33".
Add "_A33" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
---
Changes in v4:
- Change A23 to A33, as the driver never supports A23.
drivers/iio/a
SUN8I", not "SUN8I_A33".
Add "_A33" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v4:
- Change A23 to A33, as the driver never supports A23.
drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
include/linux
ady merged.
Icenowy Zheng (6):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33
iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS
variants
iio: adc: sun4i-gpadc-iio: add supp
ady merged.
Icenowy Zheng (6):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33
iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS
variants
iio: adc: sun4i-gpadc-iio: add supp
The Lamobo R1 board connected the ACIN of the AXP209 PMIC to a MicroUSB
port, and the battery input is connected to a generic connector.
Enable these two power supplies in the device tree.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sun7i-a20-lamobo-r1.d
The Lamobo R1 board connected the ACIN of the AXP209 PMIC to a MicroUSB
port, and the battery input is connected to a generic connector.
Enable these two power supplies in the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 8
1 file changed
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4
1
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
.../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4
1 file changed, 4 insertions(+)
As we're going to add simplefb support for Allwinner SoCs with DE2, add
suitable pipeline strings in the device tree binding.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4
1 file changed, 4 insertions(+)
diff --git
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng <i
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/su
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch
CCU device node for H3 SoC, and the skeleton
of the node enters the H3/H5 common DTSI; the H5 support is splited
into the third patch, as they will enter different tree.
The fourth patch finally adds simplefb nodes, using the
pipeline strings introduced in the first patch.
Icenowy Zheng (4):
dt
CCU device node for H3 SoC, and the skeleton
of the node enters the H3/H5 common DTSI; the H5 support is splited
into the third patch, as they will enter different tree.
The fourth patch finally adds simplefb nodes, using the
pipeline strings introduced in the first patch.
Icenowy Zheng (4):
dt
locks")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 7a81c4885836..543c46d0e045 100644
--- a/drivers/
The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.
Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Ice
locks")
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 7a81c4885836..543c46d0e045 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-
The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.
Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Ice
for lock by adds CLK_SET_RATE_UNGATE
flag.
The second patch solves the problem that H3 GPU clock is not really tweaked
by add CLK_SET_RATE_PARENT flag to it.
Icenowy Zheng (2):
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
for lock by adds CLK_SET_RATE_UNGATE
flag.
The second patch solves the problem that H3 GPU clock is not really tweaked
by add CLK_SET_RATE_PARENT flag to it.
Icenowy Zheng (2):
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner V3s has a DMA engine similar to the ones from A31, but with
fewer channels and DRQs.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Acked-by: Chen-Yu Tsai <w...@csie.org>
Acked-by: Rob Herrin
From: Icenowy Zheng
Allwinner V3s has a DMA engine similar to the ones from A31, but with
fewer channels and DRQs.
Add support for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
drivers/dma/sun6i
From: Icenowy Zheng <icen...@aosc.xyz>
Originally we enable a special gate bit when the compatible indicates
A23/33.
But according to BSP sources and user manuals, more SoCs will need this
gate bit.
So make it a common quirk configured in the config struct.
Signed-off-by: Icenowy Zheng
From: Icenowy Zheng
Originally we enable a special gate bit when the compatible indicates
A23/33.
But according to BSP sources and user manuals, more SoCs will need this
gate bit.
So make it a common quirk configured in the config struct.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu
This is a dedicated patchset of Allwinner V3s DMA support, which used
to be part of the audio codec support patchset.
It's a derivation of the DMA part of v3 of the codec patchset.
Icenowy Zheng (2):
dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk
dmaengine: sun6i
This is a dedicated patchset of Allwinner V3s DMA support, which used
to be part of the audio codec support patchset.
It's a derivation of the DMA part of v3 of the codec patchset.
Icenowy Zheng (2):
dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk
dmaengine: sun6i
于 2017年8月28日 GMT+08:00 下午8:16:44, Antony Antony 写到:
>On Fri, Aug 25, 2017 at 03:28:41PM +0200, Code Kipper wrote:
>> On 25 August 2017 at 12:32, Antony Antony wrote:
>
>> > +
>> > + brcmf: bcrmf@1 {
>> > + reg = <1>;
>> > +
于 2017年8月28日 GMT+08:00 下午8:16:44, Antony Antony 写到:
>On Fri, Aug 25, 2017 at 03:28:41PM +0200, Code Kipper wrote:
>> On 25 August 2017 at 12:32, Antony Antony wrote:
>
>> > +
>> > + brcmf: bcrmf@1 {
>> > + reg = <1>;
>> > + compatible = "brcm,bcm4329-fmac";
>>
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