[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

As we have already the support for the DE2 on Allwinner H3, add the display engine pipeline device tree nodes to its DTSI file. The H5 pipeline has some differences and will be enabled later. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi

[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

As we have already the support for the DE2 on Allwinner H3, add the display engine pipeline device tree nodes to its DTSI file. The H5 pipeline has some differences and will be enabled later. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 170

[PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3

_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it). Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c in

[PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3

_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it). Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index d1ab0d713fa6..b1127e862

[PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3

The CLK_PLL_DE is needed to be referenced in device tree for H3, for both forcing the parent of PLL_DE. So export it to the device tree binding header. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-- include/dt-bindings/clock/sun8i-h3

[PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3

The CLK_PLL_DE is needed to be referenced in device tree for H3, for both forcing the parent of PLL_DE. So export it to the device tree binding header. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +-- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++ 2 files

[PATCH 04/13] drm: sun4i: add compatible for H3 display engine

Add a compatible string for H3 display engine in sun4i_drv code. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index fd99fe

[PATCH 04/13] drm: sun4i: add compatible for H3 display engine

Add a compatible string for H3 display engine in sun4i_drv code. Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index fd99fe8a4df7..02c80bb7b385 100644

[PATCH 03/13] drm: sun4i: add support for H3's TCON

From: Icenowy Zheng <icen...@aosc.xyz> Allwinner H3 has two special TCONs without channel 0. Add support for this kind of TCON. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun4i

[PATCH 03/13] drm: sun4i: add support for H3's TCON

From: Icenowy Zheng Allwinner H3 has two special TCONs without channel 0. Add support for this kind of TCON. Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++--- drivers/gpu/drm/sun4i

[PATCH 00/13] Allwinner H3 DE2 basical support

ty now due to no TVE) The last 6 patches are only used for testing this patchset, and they're going to be sent by Jernej Skrabec after this patchset is applied. Icenowy Zheng (9): dt-bindings: update the binding for Allwinner H3 DE2 support drm: sun4i: add support for H3 mixers drm: sun4i: a

[PATCH 00/13] Allwinner H3 DE2 basical support

ty now due to no TVE) The last 6 patches are only used for testing this patchset, and they're going to be sent by Jernej Skrabec after this patchset is applied. Icenowy Zheng (9): dt-bindings: update the binding for Allwinner H3 DE2 support drm: sun4i: add support for H3 mixers drm: sun4i: a

[PATCH] pinctrl: sunxi: rename R_PIO i2c pin function name

in mainline kernel so I think it's safe to change the name. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 4 ++-- 3 files changed, 6 ins

[PATCH] pinctrl: sunxi: rename R_PIO i2c pin function name

in mainline kernel so I think it's safe to change the name. Signed-off-by: Icenowy Zheng --- drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deleti

Re: [PATCH 2/3] ARM: sunxi: h3/h5: Add sun8i-h3-ephy compatible

于 2017年7月28日 GMT+08:00 下午5:44:51, Chen-Yu Tsai 写到: >On Fri, Jul 28, 2017 at 5:28 PM, Corentin Labbe > wrote: >> This patch adds the sun8i-h3-ephy compatible to the internal PHY. >> >> Signed-off-by: Corentin Labbe >> --- >>

Re: [PATCH 2/3] ARM: sunxi: h3/h5: Add sun8i-h3-ephy compatible

于 2017年7月28日 GMT+08:00 下午5:44:51, Chen-Yu Tsai 写到: >On Fri, Jul 28, 2017 at 5:28 PM, Corentin Labbe > wrote: >> This patch adds the sun8i-h3-ephy compatible to the internal PHY. >> >> Signed-off-by: Corentin Labbe >> --- >> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 ++- > >To avoid repeating the

Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

于 2017年7月26日 GMT+08:00 下午3:08:06, Chen-Yu Tsai <w...@csie.org> 写到: >On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icen...@aosc.io> wrote: >> From: Ondrej Jirman <meg...@megous.com> >> >> Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on >

Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

于 2017年7月26日 GMT+08:00 下午3:08:06, Chen-Yu Tsai 写到: >On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote: >> From: Ondrej Jirman >> >> Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on >> Orange Pi PC, then set the power supply of the ARM cores to

Re: [PATCH 0/3] Add ethernet0 alias for several A64 boards

> > On Sat, Jul 22, 2017 at 10:28:49AM +0800, Icenowy Zheng wrote: >> > > > Allwinner A64 SoC has an EMAC which is used to provide Ethernet >> > > > function on several boards. >> > > > >> > > > The EMAC itself doesn't have a

Re: [PATCH 0/3] Add ethernet0 alias for several A64 boards

于 2017年7月25日 GMT+08:00 下午10:31:27, Maxime Ripard 写到: >On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote: >> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io wrote: >> > 在 2017-07-24 15:58，Maxime Ripard 写道： >> > > On Sat, Jul 22, 2017 at 1

[PATCH v2 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m

[PATCH v2 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64

. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index ec72ca8c8b30

[PATCH v2 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

Banana Pi M64 board uses an AXP803 PMIC. Enable the PMIC and its regulators. As we have now proper regulators support, missing or dummy regulators are changed to the correct ones. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Changed vdd-cpux constraints. - Added v

[PATCH v2 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

Banana Pi M64 board uses an AXP803 PMIC. Enable the PMIC and its regulators. As we have now proper regulators support, missing or dummy regulators are changed to the correct ones. Signed-off-by: Icenowy Zheng --- Changes in v2: - Changed vdd-cpux constraints. - Added vcc-1v2-hsic regulator

[PATCH v2 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v2: - Added Chen-Yu's review tag. arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinne

[PATCH v2 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64

. Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- Changes in v2: - Added Chen-Yu's review tag. arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64

Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

于 2017年7月23日 GMT+08:00 下午11:15:04, Chen-Yu Tsai <w...@csie.org> 写到: >On Fri, Jul 21, 2017 at 7:38 PM, <icen...@aosc.io> wrote: >> 在 2017-07-21 15:49，Chen-Yu Tsai 写道： >>> >>> On Fri, Jul 21, 2017 at 3:44 PM, Icenowy Zheng <icen...@aosc.io> >wrote

Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

于 2017年7月23日 GMT+08:00 下午11:15:04, Chen-Yu Tsai 写到: >On Fri, Jul 21, 2017 at 7:38 PM, wrote: >> 在 2017-07-21 15:49，Chen-Yu Tsai 写道： >>> >>> On Fri, Jul 21, 2017 at 3:44 PM, Icenowy Zheng >wrote: >>>> >>>> >>>> >>>&g

[PATCH] thermal: core: fix some format issues on critical shutdown string

The critical shutdown notice string used to have some spaces missing, which makes it not so pretty. Add the spaces to satisfy usual English space rules. Reported-by: Mingcong Bai <jeff...@aosc.io> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/thermal/thermal_core.c |

[PATCH] thermal: core: fix some format issues on critical shutdown string

The critical shutdown notice string used to have some spaces missing, which makes it not so pretty. Add the spaces to satisfy usual English space rules. Reported-by: Mingcong Bai Signed-off-by: Icenowy Zheng --- drivers/thermal/thermal_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH v3 5/5] ARM: sun8i: h3: add partial CPU thermal zone

are also not added yet. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index efe3a8e4f2af..551efecaab5d 100644 --- a/arch/arm/boot/dts

[PATCH v3 5/5] ARM: sun8i: h3: add partial CPU thermal zone

are also not added yet. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index efe3a8e4f2af..551efecaab5d 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b

[PATCH v3 0/5] IIO-based thermal sensor driver for Allwinner H3 SoC

ady merged. Icenowy Zheng (5): dt-bindings: update the Allwinner GPADC device tree binding for H3 iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23 iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor ARM: sun8i: h3: add support for the thermal sensor i

[PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

Allwinner H3 features a thermal sensor like the one in A33, but has its register re-arranged, the clock divider moved to CCU (originally the clock divider is in ADC) and added a pair of bus clock and reset. Update the binding document to cover H3. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v3 0/5] IIO-based thermal sensor driver for Allwinner H3 SoC

ady merged. Icenowy Zheng (5): dt-bindings: update the Allwinner GPADC device tree binding for H3 iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23 iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor ARM: sun8i: h3: add support for the thermal sensor i

[PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

Allwinner H3 features a thermal sensor like the one in A33, but has its register re-arranged, the clock divider moved to CCU (originally the clock divider is in ADC) and added a pair of bus clock and reset. Update the binding document to cover H3. Signed-off-by: Icenowy Zheng --- Changes in v3

[PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Clock name changes. - Fixed some small issues pointed out by Quentin. drivers/iio/adc/sun4i-gpadc-iio.c | 228 +++--- include/linux/mfd/sun4i-gpadc.h | 27 + 2 files changed, 215 insertions(

[PATCH v3 4/5] ARM: sun8i: h3: add support for the thermal sensor in H3

As we have gained the support for the thermal sensor in H3, we can now add its device nodes to the device tree. Add them to the H3 device tree. The H5 thermal sensor has some differences, and will be added furtherly. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Cloc

[PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

SUN8I", not "SUN8I_A23". Add "_A23" after "SUN8I" on the register names. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/iio/adc/sun4i-gpadc-iio.c | 2 +- include/linux/mfd/sun4i-gpadc.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletion

[PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

-off-by: Icenowy Zheng --- Changes in v3: - Clock name changes. - Fixed some small issues pointed out by Quentin. drivers/iio/adc/sun4i-gpadc-iio.c | 228 +++--- include/linux/mfd/sun4i-gpadc.h | 27 + 2 files changed, 215 insertions(+), 40 deletions

[PATCH v3 4/5] ARM: sun8i: h3: add support for the thermal sensor in H3

As we have gained the support for the thermal sensor in H3, we can now add its device nodes to the device tree. Add them to the H3 device tree. The H5 thermal sensor has some differences, and will be added furtherly. Signed-off-by: Icenowy Zheng --- Changes in v3: - Clock name changes

[PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

SUN8I", not "SUN8I_A23". Add "_A23" after "SUN8I" on the register names. Signed-off-by: Icenowy Zheng --- drivers/iio/adc/sun4i-gpadc-iio.c | 2 +- include/linux/mfd/sun4i-gpadc.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/driv

[PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

atch, slight changes and change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 19 +++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-ora

[PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

] Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 19 +++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index 998b60f8d295..d855f8b6254e 100644 --- a/arch/arm/boot

[PATCH 09/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/bo

[PATCH 09/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus

[PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

n-Yu Tsai <w...@csie.org> Tested-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 62e4f0d2b2fc..406d0aac9fd6 100644

[PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

Some new Allwinner SoCs get supported in the kernel after the compatibles are added to cpufreq-dt-platdev driver. Add their compatible strings in the cpufreq-dt-platdev driver. Cc: "Rafael J. Wysocki" <r...@rjwysocki.net> Cc: Viresh Kumar <viresh.ku...@linaro.org> Signed

[PATCH 08/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 38 +- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..a0cee17fe44b

[PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

From: Chen-Yu Tsai This patch utilizes the new PLL clk notifier to gate then ungate the PLL CPU clock after rate changes. This should prevent any system hangs resulting from cpufreq changes to the clk. Reported-by: Ondrej Jirman Signed-off-by: Chen-Yu Tsai Tested-by: Icenowy Zheng

[PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

Some new Allwinner SoCs get supported in the kernel after the compatibles are added to cpufreq-dt-platdev driver. Add their compatible strings in the cpufreq-dt-platdev driver. Cc: "Rafael J. Wysocki" Cc: Viresh Kumar Signed-off-by: Icenowy Zheng --- drivers/cpufreq/cpufreq-dt-pla

[PATCH 08/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-h3.dtsi | 38 +- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..a0cee17fe44b 100644 --- a/arch/arm/boot/dts

[PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

The CPUX clock, which is the main clock of the ARM core on Allwinner H3, can be adjusted by changing the frequency of the PLL_CPUX clock. Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX clock can be adjusted when adjusting the CPUX clock. Signed-off-by: Icenowy Zheng <i

[PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

The CPUX clock, which is the main clock of the ARM core on Allwinner H3, can be adjusted by changing the frequency of the PLL_CPUX clock. Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX clock can be adjusted when adjusting the CPUX clock. Signed-off-by: Icenowy Zheng

[PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

From: Ondrej Jirman <meg...@megous.com> Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng <

[PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 6f2162608006..b240099bc865 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +

[PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

From: Ondrej Jirman Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank. Add support for it in the device tree. Signed-off-by: Ondrej Jirman [Icenowy: Change to use r_ccu and change pinmux node name] Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14

[PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

From: Ondrej Jirman H3/H5 SoCs contain an I2C controller optionally available on the PL0 and PL1 pins. This patch adds pinmux configuration for this controller. Signed-off-by: Ondrej Jirman [Icenowy: change commit message and node name] Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts

[PATCH 02/10] regulator: add support for SY8106A regulator

nowy: Change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/regulator/Kconfig | 8 +- drivers/regulator/Makefile| 2 +- drivers/regulator/sy8106a-regulator.c | 163 ++ 3 files changed, 171 insertions(+), 2 de

[PATCH 02/10] regulator: add support for SY8106A regulator

From: Ondrej Jirman SY8106A is an I2C attached single output regulator made by Silergy Corp, which is used on several Allwinner H3/H5 SBCs to control the power supply of the ARM cores. Add a driver for it. Signed-off-by: Ondrej Jirman [Icenowy: Change commit message] Signed-off-by: Icenowy

[PATCH 01/10] dt-bindings: add binding for the SY8160A voltage regulator

From: Ondrej Jirman <meg...@megous.com> SY8106A is an I2C-controlled adjustable voltage regulator made by Silergy Corp. Add its device tree binding. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Change commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io>

[PATCH 00/10] A trial to Allwinner H3 DVFS support

mentioned. Chen-Yu Tsai (1): clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change Icenowy Zheng (4): clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 cpufreq: dt: Add support for some new Allwinner SoCs ARM: sun8i: h3: add operating-points-v2 table for CPU ARM

[PATCH 01/10] dt-bindings: add binding for the SY8160A voltage regulator

From: Ondrej Jirman SY8106A is an I2C-controlled adjustable voltage regulator made by Silergy Corp. Add its device tree binding. Signed-off-by: Ondrej Jirman [Icenowy: Change commit message] Signed-off-by: Icenowy Zheng --- .../bindings/regulator/sy8106a-regulator.txt| 21

[PATCH 00/10] A trial to Allwinner H3 DVFS support

mentioned. Chen-Yu Tsai (1): clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change Icenowy Zheng (4): clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 cpufreq: dt: Add support for some new Allwinner SoCs ARM: sun8i: h3: add operating-points-v2 table for CPU ARM

[PATCH v3 0/2] Last step to working Allwinner R40 pinctrl

, with fixes suggested by Chen-Yu and Maxime. Icenowy Zheng (2): pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: sunxi: add support of R40 to A10 pinctrl driver drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274

[PATCH v3 0/2] Last step to working Allwinner R40 pinctrl

, with fixes suggested by Chen-Yu and Maxime. Icenowy Zheng (2): pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: sunxi: add support of R40 to A10 pinctrl driver drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274

[PATCH v3 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v3: - Fixed a m

[PATCH v3 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- Changes in v3: - Fixed a missing comma in v2. - Added Chen-Yu's review tag

[PATCH v3 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

iver of its own") Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v3: - Added Chen-Yu's review tag. - Added fix tag suggested by Chen-Yu. Changes in v2: - Commit message changes. (mentioning the datasheet versions which are us

[PATCH v3 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

iver of its own") Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- Changes in v3: - Added Chen-Yu's review tag. - Added fix tag suggested by Chen-Yu. Changes in v2: - Commit message changes. (mentioning the datasheet versions which are used to discover this pin function.) drivers/p

[PATCH 3/3] arm64: allwinner: a64: add ethernet0 alias for SoPine EMAC node

The SoPine official baseboard uses the A64 chip's EMAC to provide an Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-

[PATCH 3/3] arm64: allwinner: a64: add ethernet0 alias for SoPine EMAC node

The SoPine official baseboard uses the A64 chip's EMAC to provide an Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 1

[PATCH 0/3] Add ethernet0 alias for several A64 boards

t0 aliases to these boards. I hope this patchset can be queued in 4.13, otherwise 4.13 kernels won't get non-volatile MAC addresses, and will use random ones instead, which is annoying to many users. Icenowy Zheng (3): arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node arm64: allw

[PATCH 2/3] arm64: allwinner: a64: add ethernet0 alias for Pine64 EMAC node

The Pine64 (including the Plus models) board uses the A64 chip's EMAC to provide Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/

[PATCH 0/3] Add ethernet0 alias for several A64 boards

t0 aliases to these boards. I hope this patchset can be queued in 4.13, otherwise 4.13 kernels won't get non-volatile MAC addresses, and will use random ones instead, which is annoying to many users. Icenowy Zheng (3): arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node arm64: allw

[PATCH 2/3] arm64: allwinner: a64: add ethernet0 alias for Pine64 EMAC node

The Pine64 (including the Plus models) board uses the A64 chip's EMAC to provide Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts

[PATCH 1/3] arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node

The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m

[PATCH 1/3] arm64: allwinner: a64: add ethernet0 alias for BPi M64 EMAC node

The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet link. Add the ethernet0 alias in the device tree, in order to let U-Boot generate a MAC address from the chip's SID. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 + 1 file

[PATCH v2 2/2] arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the baseboard

The SoPine SoM has an AXP803 PMIC connected to the RSB bus of the A64 SoC, and the regulators of the PMIC are used both on the SoM itself and on the official baseboard Add related device tree parts to the SoPine SoM DTSI file and the baseboard DT. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v2 1/2] arm64: allwinner: a64: enable AXP803 regulators for Pine64

Add support of AXP803 regulators in the Pine64 device tree. The phy-supply regulator is also set in EMAC device node, in order to prevent Ethernet regression by regulator get disabled by regulator framework. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Change t

[PATCH v2 2/2] arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the baseboard

The SoPine SoM has an AXP803 PMIC connected to the RSB bus of the A64 SoC, and the regulators of the PMIC are used both on the SoM itself and on the official baseboard Add related device tree parts to the SoPine SoM DTSI file and the baseboard DT. Signed-off-by: Icenowy Zheng --- Changes in v2

[PATCH v2 1/2] arm64: allwinner: a64: enable AXP803 regulators for Pine64

Add support of AXP803 regulators in the Pine64 device tree. The phy-supply regulator is also set in EMAC device node, in order to prevent Ethernet regression by regulator get disabled by regulator framework. Signed-off-by: Icenowy Zheng --- Changes in v2: - Change the min voltage of vdd-cpux

[PATCH v2 0/2] AXP803 regulators support for Pine64 and SoPine

regulators in v1 are removed. Icenowy Zheng (2): arm64: allwinner: a64: enable AXP803 regulators for Pine64 arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the baseboard .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 102 + .../dts/allwinner/sun50i-a64

[PATCH v2 0/2] AXP803 regulators support for Pine64 and SoPine

regulators in v1 are removed. Icenowy Zheng (2): arm64: allwinner: a64: enable AXP803 regulators for Pine64 arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the baseboard .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 102 + .../dts/allwinner/sun50i-a64

Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

于 2017年7月21日 GMT+08:00 下午3:42:07, Chen-Yu Tsai <w...@csie.org> 写到: >On Fri, Jul 21, 2017 at 7:07 AM, Icenowy Zheng <icen...@aosc.io> wrote: >> Banana Pi M64 board uses an AXP803 PMIC. >> >> Enable the PMIC and its regulators. >> >> As we have no

Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

于 2017年7月21日 GMT+08:00 下午3:42:07, Chen-Yu Tsai 写到: >On Fri, Jul 21, 2017 at 7:07 AM, Icenowy Zheng wrote: >> Banana Pi M64 board uses an AXP803 PMIC. >> >> Enable the PMIC and its regulators. >> >> As we have now proper regulators support, missing o

[PATCH 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m

[PATCH 3/3] arm64: allwinner: a64: add proper support for the Wi-Fi on BPi M64

. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 51d67c0a0edf

[PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

Banana Pi M64 board uses an AXP803 PMIC. Enable the PMIC and its regulators. As we have now proper regulators support, missing or dummy regulators are changed to the correct ones. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts

[PATCH 2/3] arm64: allwinner: a64: enable AXP803 for Banana Pi M64

Banana Pi M64 board uses an AXP803 PMIC. Enable the PMIC and its regulators. As we have now proper regulators support, missing or dummy regulators are changed to the correct ones. Signed-off-by: Icenowy Zheng --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 116

[PATCH 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts

[PATCH 1/3] arm64: allwinner: a64: enable USB host controller for BPi M64

. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 0d1f026d831a

[PATCH v2 0/2] Last step to working Allwinner R40 pinctrl

, with fixes suggested by Chen-Yu and Maxime. Icenowy Zheng (2): pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: sunxi: add support of R40 to A10 pinctrl driver drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274

[PATCH v2 0/2] Last step to working Allwinner R40 pinctrl

, with fixes suggested by Chen-Yu and Maxime. Icenowy Zheng (2): pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver pinctrl: sunxi: add support of R40 to A10 pinctrl driver drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274

[PATCH v2 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Fixed some lines' format. drivers/pinctrl/sunxi/K

[PATCH v2 2/2] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng --- Changes in v2: - Fixed some lines' format. drivers/pinctrl/sunxi/Kconfig | 2

[PATCH v2 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

heet V1.41 contain this pin function, and it's discovered during implementing R40 pinctrl driver. Add it to the driver. As we now merged A20 pinctrl driver to the A10 one, we need to only fix the A10 driver now. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Commit

[PATCH v2 1/2] pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

heet V1.41 contain this pin function, and it's discovered during implementing R40 pinctrl driver. Add it to the driver. As we now merged A20 pinctrl driver to the A10 one, we need to only fix the A10 driver now. Signed-off-by: Icenowy Zheng --- Changes in v2: - Commit message changes. (mentioning the

[PATCH] dt-bindings: add compatible string of Allwinner H5 Mali-450 MP4 GPU

Allwinner H5 has a Mali-450 MP4 GPU, which has a reset line like other Allwinner SoCs with Mali Utgard, but it's a Mali-450, so it needs a new compatible. Add the new compatible to Mali Utgard binding document. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bi

[PATCH] dt-bindings: add compatible string of Allwinner H5 Mali-450 MP4 GPU

Allwinner H5 has a Mali-450 MP4 GPU, which has a reset line like other Allwinner SoCs with Mali Utgard, but it's a Mali-450, so it needs a new compatible. Add the new compatible to Mali Utgard binding document. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/gpu/arm,mali

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