tegra210_usb3_phy_power_on() if the lane
is assigned for XUSB super-speed.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
no change
v6:
no change
v5:
no change
v4:
mutex_lock()/mutex_unlock() fix
update copyright string
v3:
new, was a part of "phy: tegra: xusb: Rear
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
no change
v6
and restore XUSB PADCTL context during system suspend and
resume.
- tegra_xusb_padctl_suspend_noirq()
- tegra_xusb_padctl_resume_noirq()
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
add 'Acked-by: Thierry Reding '
v6:
no change
v5:
no change
v4:
move sleepwalk/wake stubs
This commit implements a register map which grants USB (UTMI and HSIC)
sleepwalk registers access to USB PHY drivers. The USB sleepwalk logic
is in PMC hardware block but USB PHY drivers have the best knowledge
of proper programming sequence.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
host driver invokes
.phy_exit() which indicates disabling a USB port.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
no change
v6:
no change
v5:
no change
v4:
no change
v3:
new, was a part of "phy: tegra: xusb: Add wake/sleepwalk for Tegra210"
drivers/phy/
This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
sleepwalk operations.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
add 'Acked-by: Thierry Reding '
v6:
no change
v5:
no change
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct
, it invokes pm_runtime_put_sync() to request power
driver to power down partitions; If power domain devices are not
available, tegra_powergate_power_off() will be used to power down
partitions.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
add 'Acked-by: Thierry
whether PLLE hardware sequencer has been enabled or not.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
no change
v6:
no change
v5:
no change
v4:
update copyright strings
v3:
rename 'val' with 'value
drivers/clk/tegra/clk-tegra210.c | 53
event. At runtime resume, xhci-tegra driver
brings XUSB host controller out of ELPG to handle the wake events.
The same ELPG enter/exit procedure will be performed for system
suspend/resume path so USB devices can remain connected across SC7.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7
This commit implements Tegra210 XUSB PADCTL wake and sleepwalk
routines. Sleepwalk logic is in PMC (always-on) hardware block.
PMC driver provides managed access to the sleepwalk registers
via regmap framework.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
add 'Acked-by: Thierry
This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb
PHY driver. It is a phandle and specifier referring to the Tegra210
pmc@7000e400 node.
Signed-off-by: JC Kuo
Acked-by: Rob Herring
---
v7:
no change
v6:
no change
v5:
replace "pmc@7000e400 node&quo
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo
---
v7:
no change
v6:
no change
v5:
no change
v4:
no change
v3:
no change
arch/
ng lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
3. Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
Signed-off-by: JC Kuo
Acked-by: Thierry Re
.
JC Kuo (14):
clk: tegra: Add PLLE HW power sequencer control
clk: tegra: Don't enable PLLE HW sequencer at init
phy: tegra: xusb: Move usb3 port init for Tegra210
phy: tegra: xusb: Rearrange UPHY init on Tegra210
phy: tegra: xusb: Add Tegra210 lane_iddq operation
phy: tegra: xusb: Add
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v7:
no change
v6
On 1/19/21 9:52 PM, Thierry Reding wrote:
> On Tue, Jan 19, 2021 at 04:55:35PM +0800, JC Kuo wrote:
>> Once UPHY PLL hardware power sequencer is enabled, do not assert
>> reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
>> This commit removes reset_con
This commit implements Tegra210 XUSB PADCTL wake and sleepwalk
routines. Sleepwalk logic is in PMC (always-on) hardware block.
PMC driver provides managed access to the sleepwalk registers
via regmap framework.
Signed-off-by: JC Kuo
---
v6:
no change
v5:
no change
v4:
move sleepwalk
This commit implements a register map which grants USB (UTMI and HSIC)
sleepwalk registers access to USB PHY drivers. The USB sleepwalk logic
is in PMC hardware block but USB PHY drivers have the best knowledge
of proper programming sequence.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo
---
v6:
no change
v5:
no change
v4:
no change
v3:
no change
arch/arm64/boot/
This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb
PHY driver. It is a phandle and specifier referring to the Tegra210
pmc@7000e400 node.
Signed-off-by: JC Kuo
Acked-by: Rob Herring
---
v6:
no change
v5:
replace "pmc@7000e400 node" -> with "
tegra210_usb3_phy_power_on() if the lane
is assigned for XUSB super-speed.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v6:
no change
v5:
no change
v4:
mutex_lock()/mutex_unlock() fix
update copyright string
v3:
new, was a part of "phy: tegra: xusb: Rearrange UPHY
ng lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v6:
no change
v5:
no change
v4:
no change
v3:
make separate changes
use "unsigned int" instead "int"
whether PLLE hardware sequencer has been enabled or not.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v6:
no change
v5: no change
v4:
update copyright strings
v3:
rename 'val' with 'value
drivers/clk/tegra/clk-tegra210.c | 53 +++-
include/linux/clk/tegra.h
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v6:
no change
v5
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v6:
no change
v5
and restore XUSB PADCTL context during system suspend and
resume.
- tegra_xusb_padctl_suspend_noirq()
- tegra_xusb_padctl_resume_noirq()
Signed-off-by: JC Kuo
---
v6:
no change
v5:
no change
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct
This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
sleepwalk operations.
Signed-off-by: JC Kuo
---
v6:
no change
v5:
no change
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct tegra_xusb_lane_ops'
v3:
move 'ao_regs' to the top of 'struct
, it invokes pm_runtime_put_sync() to request power
driver to power down partitions; If power domain devices are not
available, tegra_powergate_power_off() will be used to power down
partitions.
Signed-off-by: JC Kuo
---
v6:
no change
v5:
no change
v4:
commit message improveme
event. At runtime resume, xhci-tegra driver
brings XUSB host controller out of ELPG to handle the wake events.
The same ELPG enter/exit procedure will be performed for system
suspend/resume path so USB devices can remain connected across SC7.
Signed-off-by: JC Kuo
---
v6:
fix compiling warning
.
JC Kuo (15):
clk: tegra: Add PLLE HW power sequencer control
clk: tegra: Don't enable PLLE HW sequencer at init
phy: tegra: xusb: Move usb3 port init for Tegra210
phy: tegra: xusb: tegra210: Do not reset UPHY PLL
phy: tegra: xusb: Rearrange UPHY init on Tegra210
phy: tegra: xusb: Add
host driver invokes
.phy_exit() which indicates disabling a USB port.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v6:
no change
v5:
no change
v4:
no change
v3:
new, was a part of "phy: tegra: xusb: Add wake/sleepwalk for Tegra210"
drivers/phy/tegra/xusb-tegra
Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
This commit removes reset_control_assert(pcie->rst) and
reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure.
Signed-off-by: JC Kuo
This commit enables USB host mode at J512 type-C port of Jetson-Xavier.
Signed-off-by: JC Kuo
---
.../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 8 +++
.../boot/dts/nvidia/tegra194-p2972-.dts | 24 +--
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git
tegra210_usb3_phy_power_on() if the lane
is assigned for XUSB super-speed.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v5:
no change
v4:
mutex_lock()/mutex_unlock() fix
update copyright string
v3:
new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210"
d
event. At runtime resume, xhci-tegra driver
brings XUSB host controller out of ELPG to handle the wake events.
The same ELPG enter/exit procedure will be performed for system
suspend/resume path so USB devices can remain connected across SC7.
Signed-off-by: JC Kuo
---
v5:
avoid using
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happens. This is required for supporting XUSB host controller
ELPG.
Signed-off-by: JC Kuo
---
v5:
no change
v4:
no change
v3:
no cha
This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
sleepwalk operations.
Signed-off-by: JC Kuo
---
v5:
no change
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct tegra_xusb_lane_ops'
v3:
move 'ao_regs' to the top of 'struct
, it invokes pm_runtime_put_sync() to request power
driver to power down partitions; If power domain devices are not
available, tegra_powergate_power_off() will be used to power down
partitions.
Signed-off-by: JC Kuo
---
v5:
no change
v4:
commit message improvement
update copy
host driver invokes
.phy_exit() which indicates disabling a USB port.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v5:
no change
v4:
no change
v3:
new, was a part of "phy: tegra: xusb: Add wake/sleepwalk for Tegra210"
drivers/phy/tegra/xusb-tegra
This commit implements Tegra210 XUSB PADCTL wake and sleepwalk
routines. Sleepwalk logic is in PMC (always-on) hardware block.
PMC driver provides managed access to the sleepwalk registers
via regmap framework.
Signed-off-by: JC Kuo
---
v5:
no change
v4:
move sleepwalk/wake stubs from
This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb
PHY driver. It is a phandle and specifier referring to the Tegra210
pmc@7000e400 node.
Signed-off-by: JC Kuo
---
v5:
replace "pmc@7000e400 node" -> with "PMC node"
v4:
new cha
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo
---
v5:
no change
v4:
no change
v3:
no change
arch/arm64/boot/dts/nvidia/tegra210.dts
This commit implements a register map which grants USB (UTMI and HSIC)
sleepwalk registers access to USB PHY drivers. The USB sleepwalk logic
is in PMC hardware block but USB PHY drivers have the best knowledge
of proper programming sequence.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
and restore XUSB PADCTL context during system suspend and
resume.
- tegra_xusb_padctl_suspend_noirq()
- tegra_xusb_padctl_resume_noirq()
Signed-off-by: JC Kuo
---
v5:
no change
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct tegra_xusb_lane_ops'
v3:
commit
ng lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v5:
no change
v4:
no change
v3:
make separate changes
use "unsigned int" instead "int" type for PHY in
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v5:
no change
v4
Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
This commit removes reset_control_assert(pcie->rst) and
reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure.
Signed-off-by: JC Kuo
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v5:
no change
v4
whether PLLE hardware sequencer has been enabled or not.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v5: no change
v4:
update copyright strings
v3:
rename 'val' with 'value
drivers/clk/tegra/clk-tegra210.c | 53 +++-
include/linux/clk/tegra.h| 4 ++-
2
.
JC Kuo (16):
clk: tegra: Add PLLE HW power sequencer control
clk: tegra: Don't enable PLLE HW sequencer at init
phy: tegra: xusb: Move usb3 port init for Tegra210
phy: tegra: xusb: tegra210: Do not reset UPHY PLL
phy: tegra: xusb: Rearrange UPHY init on Tegra210
phy: tegra: xusb: Add
;)
Cc: sta...@vger.kernel.org
Signed-off-by: JC Kuo
Reviewed-by: Jon Hunter
---
v3:
add 'Cc: sta...@vger.kernel.org' tag
v2:
add 'Fixes:' tag
add Reviewed-by: Jon Hunter
.../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 20 +--
1 file changed, 10 insertions(+), 10 deletions(-)
On 11/14/20 12:20 AM, Thierry Reding wrote:
> On Mon, Oct 19, 2020 at 04:40:46PM -0500, Rob Herring wrote:
>> On Fri, Oct 16, 2020 at 09:07:20PM +0800, JC Kuo wrote:
>>> This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb
>>> PHY driver. It
USB_VBUS_EN0 regulator (regulator@11) is being overwritten by vdd-cam-1v2
regulator. This commit rearrange USB_VBUS_EN0 to be regulator@14.
Fixes: 257c8047be44 ("arm64: tegra: jetson-tx1: Add camera supplies")
Signed-off-by: JC Kuo
Reviewed-by: Jon Hunter
---
v2:
add 'Fixes:' t
On 11/18/20 7:24 PM, Jon Hunter wrote:
>
> On 18/11/2020 03:46, JC Kuo wrote:
>> USB_VBUS_EN0 regulator (regulator@11) is being overwritten by vdd-cam-1v2
>> regulator. This commit rearrange USB_VBUS_EN0 to be regulator@14.
>>
>> Signed-off-by: JC Kuo
>&g
USB_VBUS_EN0 regulator (regulator@11) is being overwritten by vdd-cam-1v2
regulator. This commit rearrange USB_VBUS_EN0 to be regulator@14.
Signed-off-by: JC Kuo
---
.../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 20 +--
1 file changed, 10 insertions(+), 10 deletions(-)
diff
74/0x180
[ 153.757663] Code: aa0303e2 94000f64 f9405680 b4e0 (f9402803)
[ 153.763826] ---[ end trace 81543a3394cb409d ]---
Fixes: e8f7d2f409a1 ("phy: tegra: xusb: Add usb-phy support")
Signed-off-by: JC Kuo
---
drivers/phy/tegra/xusb.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 11/14/20 12:44 AM, Thierry Reding wrote:
> On Fri, Oct 16, 2020 at 09:07:10PM +0800, JC Kuo wrote:
>> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
>> state for power saving when all of the connected USB devices are in
>> suspended state. This patc
to get regulators: %d\n", err);
> + dev_err_probe(>dev, err, "failed to get regulators\n");
> goto remove;
> }
>
>
Acked-by: JC Kuo
On 10/20/20 5:40 AM, Rob Herring wrote:
> On Fri, Oct 16, 2020 at 09:07:20PM +0800, JC Kuo wrote:
>> This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb
>> PHY driver. It is a phandle and specifier referring to the Tegra210
>> pmc@7000e400 no
host driver invokes
.phy_exit() which indicates disabling a USB port.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v4:
no change
v3:
new, was a part of "phy: tegra: xusb: Add wake/sleepwalk for Tegra210"
drivers/phy/tegra/xusb-tegra210.c | 52 -
This commit implements Tegra210 XUSB PADCTL wake and sleepwalk
routines. Sleepwalk logic is in PMC (always-on) hardware block.
PMC driver provides managed access to the sleepwalk registers
via regmap framework.
Signed-off-by: JC Kuo
---
v4:
move sleepwalk/wake stubs from 'struct
event. At runtime resume, xhci-tegra driver
brings XUSB host controller out of ELPG to handle the wake events.
The same ELPG enter/exit procedure will be performed for system
suspend/resume path so USB devices can remain connected across SC7.
Signed-off-by: JC Kuo
---
v4:
reshuffle the code
This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
sleepwalk operations.
Signed-off-by: JC Kuo
---
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct tegra_xusb_lane_ops'
v3:
move 'ao_regs' to the top of 'struct tegra186_xusb_padctl'
change
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happens. This is required for supporting XUSB host controller
ELPG.
Signed-off-by: JC Kuo
---
v4:
no change
v3:
no change
arch/arm6
, it invokes pm_runtime_put_sync() to request power
driver to power down partitions; If power domain devices are not
available, tegra_powergate_power_off() will be used to power down
partitions.
Signed-off-by: JC Kuo
---
v4:
commit message improvement
update copyright strin
tegra210_usb3_phy_power_on() if the lane
is assigned for XUSB super-speed.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v4:
mutex_lock()/mutex_unlock() fix
update copyright string
v3:
new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210"
drivers/phy/
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo
---
v4:
no change
v3:
no change
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
1 file
This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb
PHY driver. It is a phandle and specifier referring to the Tegra210
pmc@7000e400 node.
Signed-off-by: JC Kuo
---
v4:
new change to document "nvidia,pmc" prop
.../devicetree/bindings/phy/nvidia,tegr
ng lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
Signed-off-by: JC Kuo
Acked-by: Thierry Re
whether PLLE hardware sequencer has been enabled or not.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v4:
update copyright strings
v3:
rename 'val' with 'value
drivers/clk/tegra/clk-tegra210.c | 53 +++-
include/linux/clk/tegra.h| 4 ++-
2 files
and restore XUSB PADCTL context during system suspend and
resume.
- tegra_xusb_padctl_suspend_noirq()
- tegra_xusb_padctl_resume_noirq()
Signed-off-by: JC Kuo
---
v4:
move sleepwalk/wake stubs from 'struct tegra_xusb_padctl_ops' to
'struct tegra_xusb_lane_ops'
v3:
commit message
This commit implements a register map which grants USB (UTMI and HSIC)
sleepwalk registers access to USB PHY drivers. The USB sleepwalk logic
is in PMC hardware block but USB PHY drivers have the best knowledge
of proper programming sequence.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v4:
no change
v3
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo
Acked-by: Thierry Reding
---
v4:
no change
v3
Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
This commit removes reset_control_assert(pcie->rst) and
reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure.
Signed-off-by: JC Kuo
.
JC Kuo (16):
clk: tegra: Add PLLE HW power sequencer control
clk: tegra: Don't enable PLLE HW sequencer at init
phy: tegra: xusb: Move usb3 port init for Tegra210
phy: tegra: xusb: tegra210: Do not reset UPHY PLL
phy: tegra: xusb: Rearrange UPHY init on Tegra210
phy: tegra: xusb: Add
I will amend accordingly and submit new patch.
Thanks for review.
JC
On 9/28/20 10:06 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:41PM +0800, JC Kuo wrote:
>> This commit implements the complete programming sequence for ELPG
>> entry and exit.
>>
>>
I will modify the commit message accordingly.
Thanks for review.
JC
On 9/28/20 9:53 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:40PM +0800, JC Kuo wrote:
>> This commit unlinks xhci-tegra platform device with ss/host power
>> domain devices. Reasons for this chan
I will amend accordingly and submit new patch.
Thanks for review.
JC
On 9/28/20 9:50 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:38PM +0800, JC Kuo wrote:
>> This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
>> sleepwalk operations.
>>
>
On 9/28/20 9:40 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:36PM +0800, JC Kuo wrote:
> [...]
>> diff --git a/drivers/phy/tegra/xusb-tegra210.c
>> b/drivers/phy/tegra/xusb-tegra210.c
> [...]
>
> Could we add function pointers to struct
I will add a dt-bindings commit for this change.
Thanks for review.
JC
On 9/28/20 9:18 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:35PM +0800, JC Kuo wrote:
>> PMC driver provides USB sleepwalk registers access to XUSB PADCTL
>> driver. This commit adds a "
I will amend commit accordingly and submit a new patch.
Thanks for review.
JC
On 9/28/20 9:17 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:34PM +0800, JC Kuo wrote:
>> This commit implements a register map which grants USB (UTMI and HSIC)
>> sleepwalk registers ac
Asserting reset to a PLL when it's managed by hardware power sequencer would
break sequencer's state machine. Putting PLL in reset doesn't save some extra
power.
Thanks for review.
JC
On 9/28/20 9:06 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:30PM +0800, JC Kuo wrote:
>
ll clients are in low power state,
i.e., software has to explicitly power off PLLE.
Thanks for review.
JC
On 9/28/20 8:54 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote:
>> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
>> state
Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
This commit removes reset_control_assert(pcie->rst) and
reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure.
Signed-off-by: JC Kuo
---
v3:
tegra210_usb3_phy_power_on() if the lane
is assigned for XUSB super-speed.
Signed-off-by: JC Kuo
---
v3:
new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210"
drivers/phy/tegra/xusb-tegra210.c | 298 +-
drivers/phy/tegra/xusb.c
ng lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
Signed-off-by: JC Kuo
---
v3:
make separate changes
use "unsigned int" instead "int" type for PHY index
add blank line for better readability
drivers
As per Tegra210 TRM, before changing lane assignments, driver should
keep lanes in IDDQ and sleep state; after changing lane assignments,
driver should bring lanes out of IDDQ.
This commit implements the required operations.
Signed-off-by: JC Kuo
---
v3:
add 'misc_ctl2' data member to UPHY
This commit implements Tegra210 XUSB PADCTL wake and sleepwalk
routines. Sleepwalk logic is in PMC (always-on) hardware block.
PMC driver provides managed access to the sleepwalk registers
via regmap framework.
Signed-off-by: JC Kuo
---
v3:
rename 'pmc_reg" with 'regmap' and move to th
-off-by: JC Kuo
---
v3:
commit message improvement
drop regmap_reg() usage
rename 'reg' with 'offset'
rename 'val' with 'value'
drop '__force' when invokes devm_regmap_init()
print error code of devm_regmap_init()
move devm_regmap_init() a litter bit earlier
explicitly set
This commit implements Tegra186/Tegra194 XUSB PADCTL/AO wake and
sleepwalk operations.
Signed-off-by: JC Kuo
---
v3:
move 'ao_regs' to the top of 'struct tegra186_xusb_padctl'
change return data of .phy_remote_wake_detected() to 'bool'
change input parameter of .phy_remote_wake_detected
, it invokes pm_runtime_put_sync() to request power
driver to power down partitions; If power domain devices are not
available, tegra_powergate_power_off() will be used to power down
partitions.
Signed-off-by: JC Kuo
---
v3:
'use_genpd' base on the results of tegra_xusb_powe
host driver invokes
.phy_exit() which indicates disabling a USB port.
Signed-off-by: JC Kuo
---
v3:
new, was a part of "phy: tegra: xusb: Add wake/sleepwalk for Tegra210"
drivers/phy/tegra/xusb-tegra210.c | 52 ---
1 file changed, 40 insertions(+), 12
event. At runtime resume, xhci-tegra driver
brings XUSB host controller out of ELPG to handle the wake events.
The same ELPG enter/exit procedure will be performed for system
suspend/resume path so USB devices can remain connected across SC7.
Signed-off-by: JC Kuo
---
v3:
use 'unsigned int
This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194
XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake
event happens. This is required for supporting XUSB host controller
ELPG.
Signed-off-by: JC Kuo
---
v3:
no change
arch/arm64/boot/dts/nvidi
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo
---
v3:
no change
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
1 file changed, 1
.
JC Kuo (15):
clk: tegra: Add PLLE HW power sequencer control
clk: tegra: Don't enable PLLE HW sequencer at init
phy: tegra: xusb: Move usb3 port init for Tegra210
phy: tegra: xusb: tegra210: Do not reset UPHY PLL
phy: tegra: xusb: Rearrange UPHY init on Tegra210
phy: tegra: xusb: Add
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo
---
v3:
no change
drivers/clk/tegra/clk-pll.c
and restore XUSB PADCTL context during system suspend and
resume.
- tegra_xusb_padctl_suspend_noirq()
- tegra_xusb_padctl_resume_noirq()
Signed-off-by: JC Kuo
---
v3:
commit message improvement, no change in code
drivers/phy/tegra/xusb.c | 73 ++
drivers
whether PLLE hardware sequencer has been enabled or not.
Signed-off-by: JC Kuo
---
v3:
rename 'val' with 'value
drivers/clk/tegra/clk-tegra210.c | 51
include/linux/clk/tegra.h| 2 ++
2 files changed, 53 insertions(+)
diff --git a/drivers/clk/tegra/clk
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