On Thu, Jun 27, 2013 at 08:50:44PM +0530, Viresh Kumar wrote:
> BTW, your v1 is already applied and sent to Linus. So,
> you need to send only fixup now.
Here is the fixup delta patch, thanks! :
---8<---
>From 133f670aa1dc450fd37ba39081d046bf238c507b Mon Sep 17 00:00:00 2001
From
On Thu, Jun 27, 2013 at 08:39:12PM +0530, Viresh Kumar wrote:
> On 27 June 2013 20:25, Jacob Shin wrote:
> > diff --git a/drivers/cpufreq/cpufreq_ondemand.c
> > b/drivers/cpufreq/cpufreq_ondemand.c
> > index 4b9bb5d..93eb5cb 100644
> > --- a/drivers/cpufreq/cpufreq_o
On Thu, Jun 27, 2013 at 12:32:36PM +0530, Viresh Kumar wrote:
> On 26 June 2013 23:27, Jacob Shin wrote:
> > On Wed, Jun 26, 2013 at 08:02:29PM +0530, Viresh Kumar wrote:
> >> On 26 June 2013 19:58, Jacob Shin wrote:
> >> > On Wed, Jun 26, 2013 at 12:18:
Commit-ID: 9608d33b8210c993af4430d661a6474946480c9b
Gitweb: http://git.kernel.org/tip/9608d33b8210c993af4430d661a6474946480c9b
Author: Jacob Shin
AuthorDate: Thu, 20 Jun 2013 09:52:50 -0500
Committer: H. Peter Anvin
CommitDate: Wed, 26 Jun 2013 14:55:37 -0700
x86, microcode, amd
On Wed, Jun 26, 2013 at 08:02:29PM +0530, Viresh Kumar wrote:
> On 26 June 2013 19:58, Jacob Shin wrote:
> > On Wed, Jun 26, 2013 at 12:18:27PM +0530, Viresh Kumar wrote:
>
> >> I am not sure if this is enough. What if we had ondemand as the
> >> governor in
On Thu, Jun 20, 2013 at 10:24:14AM -0500, Jacob Shin wrote:
> On Thu, Jun 20, 2013 at 10:16:16AM -0500, Jacob Shin wrote:
> > On Thu, Jun 20, 2013 at 12:30:53PM +0200, Ingo Molnar wrote:
> > >
> > > * Jacob Shin wrote:
> > >
> > > > On Fri, Ju
On Wed, Jun 26, 2013 at 08:02:29PM +0530, Viresh Kumar wrote:
> On 26 June 2013 19:58, Jacob Shin wrote:
> > On Wed, Jun 26, 2013 at 12:18:27PM +0530, Viresh Kumar wrote:
>
> >> I am not sure if this is enough. What if we had ondemand as the
> >> governor in
On Wed, Jun 26, 2013 at 12:18:27PM +0530, Viresh Kumar wrote:
> On 25 June 2013 21:49, Jacob Shin wrote:
> > Yes, so sorry about that, it looks like I failed to test with:
>
> No problem, it happens :)
>
> > CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> > CON
_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_X86_AMD_FREQ_SENSITIVITY=m
The following patch fixes this, Tim, could you please test ? :
---8<---
>From 3c727b1f775448599e67c5fb2121d79448e80c90 Mon Sep 17 00:00:00 2001
From: Jacob Shin
Date: Tue, 25 Jun 2013 10:40:5
On Thu, Jun 20, 2013 at 10:16:16AM -0500, Jacob Shin wrote:
> On Thu, Jun 20, 2013 at 12:30:53PM +0200, Ingo Molnar wrote:
> >
> > * Jacob Shin wrote:
> >
> > > On Fri, Jun 07, 2013 at 09:22:18PM -0500, Jacob Shin wrote:
> > > > This patchset addre
On Thu, Jun 20, 2013 at 12:30:53PM +0200, Ingo Molnar wrote:
>
> * Jacob Shin wrote:
>
> > On Fri, Jun 07, 2013 at 09:22:18PM -0500, Jacob Shin wrote:
> > > This patchset addreses two problems with early loading on AMD.
> > >
> > > First, feedb
Commit-ID: 275bbe2e299f1820ec8faa443d689469a9e6ecc5
Gitweb: http://git.kernel.org/tip/275bbe2e299f1820ec8faa443d689469a9e6ecc5
Author: Jacob Shin
AuthorDate: Wed, 5 Jun 2013 15:13:55 -0500
Committer: H. Peter Anvin
CommitDate: Wed, 5 Jun 2013 13:56:47 -0700
x86, microcode, amd: Make
Commit-ID: cd1c32ca969ebfd65e61312c988223bb14f09c2e
Gitweb: http://git.kernel.org/tip/cd1c32ca969ebfd65e61312c988223bb14f09c2e
Author: Jacob Shin
AuthorDate: Wed, 5 Jun 2013 15:13:56 -0500
Committer: H. Peter Anvin
CommitDate: Wed, 5 Jun 2013 13:56:55 -0700
x86, microcode, amd: Allow
On Fri, Jun 07, 2013 at 09:22:18PM -0500, Jacob Shin wrote:
> This patchset addreses two problems with early loading on AMD.
>
> First, feedback from Yinghai that find_ucode_in_initrd() should be
> marked __init:
> https://lkml.org/lkml/2013/6/4/695
>
> And second, feedba
On Wed, Jun 12, 2013 at 01:45:18PM +0530, Viresh Kumar wrote:
> This CPUFreq driver uses APIs from freq_table.c and so must select
> CPU_FREQ_TABLE.
>
Ah, thanks for cathcing this!
> Cc: Jacob Shin
> Signed-off-by: Viresh Kumar
Acked-by: Jacob Shin
> ---
> drivers/cp
and size of the microcode container file
Jacob Shin (2):
x86/microcode/amd: make find_ucode_in_initrd() __init
x86/microcode/amd: allow multiple families' bin files appended
together
arch/x86/kernel/microcode_amd_early.c | 170 -
1 file changed
Add support for parsing through multiple families' microcode patch
container binary files appended together when early loading. This is
already supported on Intel.
Reported-by: Henrique de Moraes Holschuh
Signed-off-by: Jacob Shin
---
arch/x86/kernel/microcode_amd_early.c |
Change find_ucode_in_initrd() to __init and only let BSP call it
during cold boot. This is the right thing to do because only BSP will
see initrd loaded by the boot loader. APs will offset into
initrd_start to find the microcode patch binary.
Reported-by: Yinghai Lu
Signed-off-by: Jacob Shin
On Thu, Jun 06, 2013 at 12:10:42AM +0200, Borislav Petkov wrote:
> On Fri, May 31, 2013 at 08:15:12PM -0500, Jacob Shin wrote:
> > Any thoughts on this Boris?
>
> Looks ok to me - I'm assuming you're testing all this new code on all
> families...?
Thanks, I have sent
Add support for parsing through multiple families' microcode patch
container binary files appended together when early loading. This is
already supported on Intel.
Reported-by: Henrique de Moraes Holschuh
Signed-off-by: Jacob Shin
---
arch/x86/kernel/microcode_amd_early.c |
together, whereas the current
AMD implementation lacks this support:
https://lkml.org/lkml/2013/5/31/4
V2:
* test for !initrd_start before using it
* use __pa() instead of __pa_nodebug() on AP load
* fixed calculation of start offset and size of the microcode container file
Jacob Shin (2):
x86
Change find_ucode_in_initrd() to __init and only let BSP call it
during cold boot. This is the right thing to do because only BSP will
see initrd loaded by the boot loader. APs will offset into
initrd_start to find the microcode patch binary.
Reported-by: Yinghai Lu
Signed-off-by: Jacob Shin
On Thu, Jun 06, 2013 at 12:18:33AM +0200, Borislav Petkov wrote:
> On Wed, Jun 05, 2013 at 03:13:54PM -0500, Jacob Shin wrote:
> > This patchset addreses two problems with early loading on AMD.
>
> It would be nice if, in the future, you put the maintainers of this
> driver t
together, whereas the current
AMD implementation lacks this support:
https://lkml.org/lkml/2013/5/31/4
Jacob Shin (2):
x86/microcode/amd: make find_ucode_in_initrd() __init
x86/microcode/amd: allow multiple families' bin files appended
together
arch/x86/kernel/microcode_amd_early.c |
Change find_ucode_in_initrd() to __init and only let BSP call it
during cold boot. This is the right thing to do because only BSP will
see initrd loaded by the boot loader. APs will offset into
initrd_start to find the microcode patch binary.
Reported-by: Yinghai Lu
Signed-off-by: Jacob Shin
Add support for parsing through multiple families' microcode patch
container binary files appended together when early loading. This is
already supported on Intel.
Reported-by: Henrique de Moraes Holschuh
Signed-off-by: Jacob Shin
---
arch/x86/kernel/microcode_amd_early.c |
On Tue, Jun 04, 2013 at 04:36:00PM -0500, Jacob Shin wrote:
> On Tue, Jun 04, 2013 at 02:02:43PM -0700, Yinghai Lu wrote:
> > On Fri, May 31, 2013 at 2:59 PM, tip-bot for Jacob Shin
> > wrote:
> > > Commit-ID: 6b3389ac21b5e557b957f1497d0ff22bf733e8c3
>
On Tue, Jun 04, 2013 at 02:02:43PM -0700, Yinghai Lu wrote:
> On Fri, May 31, 2013 at 2:59 PM, tip-bot for Jacob Shin
> wrote:
> > Commit-ID: 6b3389ac21b5e557b957f1497d0ff22bf733e8c3
> > Gitweb:
> > http://git.kernel.org/tip/6b3389ac21b5e557b957f1497d0ff22bf733e8
On Fri, May 31, 2013 at 06:30:39PM -0300, Henrique de Moraes Holschuh wrote:
> On Fri, 31 May 2013, Andreas Herrmann wrote:
> > On Fri, May 31, 2013 at 01:26:49AM -0300, Henrique de Moraes Holschuh wrote:
> > > On Thu, 30 May 2013, Jacob Shin wrote:
> > > > m
Commit-ID: 6b3389ac21b5e557b957f1497d0ff22bf733e8c3
Gitweb: http://git.kernel.org/tip/6b3389ac21b5e557b957f1497d0ff22bf733e8c3
Author: Jacob Shin
AuthorDate: Fri, 31 May 2013 01:53:24 -0500
Committer: H. Peter Anvin
CommitDate: Fri, 31 May 2013 13:56:58 -0700
x86, microcode, amd: Fix
On Fri, May 31, 2013 at 01:26:49AM -0300, Henrique de Moraes Holschuh wrote:
> On Thu, 30 May 2013, Jacob Shin wrote:
> > mkdir initrd
> > cd initrd
> > -mkdir kernel
> > -mkdir kernel/x86
> > -mkdir kernel/x86/microcode
> > -cp ../microcode.bin kernel/x
On Fri, May 31, 2013 at 08:13:09AM -0700, H. Peter Anvin wrote:
> If you send a patch with text above the patch, please include a scissor
> line:
>
> ---8<---
>
> ... above the patch so that git tools can process it.
Ah okay, sorry about that, will do so from now on.
Yinghai, Boris, sorry if yo
On Fri, May 31, 2013 at 10:41:33AM +0200, Borislav Petkov wrote:
> On Thu, May 30, 2013 at 08:31:08PM -0700, tip-bot for Jacob Shin wrote:
> > Commit-ID: 757885e94a22bcc82beb9b1445c95218cb20ceab
> > Gitweb:
> > http://git.kernel.org/tip/757885e94a22bcc82beb9b1445c952
On Thu, May 30, 2013 at 11:10:23PM -0700, Yinghai Lu wrote:
> On Thu, May 30, 2013 at 8:31 PM, tip-bot for Jacob Shin
> wrote:
> > Commit-ID: 757885e94a22bcc82beb9b1445c95218cb20ceab
> > Gitweb:
> > http://git.kernel.org/tip/757885e94a22bcc82beb9b1445c95218cb20ce
Commit-ID: 757885e94a22bcc82beb9b1445c95218cb20ceab
Gitweb: http://git.kernel.org/tip/757885e94a22bcc82beb9b1445c95218cb20ceab
Author: Jacob Shin
AuthorDate: Thu, 30 May 2013 14:09:19 -0500
Committer: H. Peter Anvin
CommitDate: Thu, 30 May 2013 20:19:25 -0700
x86, microcode, amd
Commit-ID: a76096a6571d5389376753c2e18b30a9791fa072
Gitweb: http://git.kernel.org/tip/a76096a6571d5389376753c2e18b30a9791fa072
Author: Jacob Shin
AuthorDate: Thu, 30 May 2013 14:09:18 -0500
Committer: H. Peter Anvin
CommitDate: Thu, 30 May 2013 20:19:25 -0700
x86, microcode, amd
Commit-ID: f2b3ee820a9f2368d7f8842ad7da062dfe86e199
Gitweb: http://git.kernel.org/tip/f2b3ee820a9f2368d7f8842ad7da062dfe86e199
Author: Jacob Shin
AuthorDate: Thu, 30 May 2013 14:09:17 -0500
Committer: H. Peter Anvin
CommitDate: Thu, 30 May 2013 20:19:25 -0700
x86, microcode: Vendor
.
* Added AMD blurb to Documentation/x86/early-microcode.txt
V2:
* Fixed warnings when compiling without early loading
* Picked up a typo fix [PATCH 1/4] from Boris
Borislav Petkov (1):
x86, microcode, intel: Correct typo in printk
Jacob Shin (3):
x86/microcode: vendor abstract out
In preparation work for early loading, refactor some common functions
that will be shared, and move some struct defines to a common header file.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/microcode_amd.h | 64
arch/x86/kernel/microcode_amd.c | 111
Add early microcode patch loading support for AMD.
Signed-off-by: Jacob Shin
---
Documentation/x86/early-microcode.txt | 11 +-
arch/x86/Kconfig | 14 +-
arch/x86/include/asm/microcode_amd.h | 14 ++
arch/x86/kernel/Makefile |1 +
arch/x86/kernel
Currently save_microcode_in_initrd() is declared in vendor neutural
microcode.h file, but defined in vendor specific
microcode_intel_early.c file. Vendor abstract it out to
microcode_core_early.c with a wrapper function.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/microcode_intel.h
From: Borislav Petkov
User-visible so correct it.
Signed-off-by: Borislav Petkov
Signed-off-by: Jacob Shin
---
arch/x86/kernel/microcode_intel_early.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/microcode_intel_early.c
b/arch/x86/kernel
On Wed, May 29, 2013 at 12:45:29AM +0200, Borislav Petkov wrote:
> On Thu, May 23, 2013 at 10:40:18AM -0500, Jacob Shin wrote:
> > Add support for early microcode patch loading on AMD.
> >
> > Signed-off-by: Jacob Shin
> > ---
> > arch/x86/Kconfig
On Fri, May 24, 2013 at 03:33:38PM +, Yu, Fenghua wrote:
> > From: Jacob Shin [mailto:jacob.s...@amd.com]
> > Add support for early microcode patch loading on AMD.
> >
> > Signed-off-by: Jacob Shin
> > ---
> > arch/x86/Kconfig
On Fri, May 24, 2013 at 10:29:48AM +0200, Borislav Petkov wrote:
> On Thu, May 23, 2013 at 04:23:01PM -0500, Jacob Shin wrote:
> > On Thu, May 23, 2013 at 09:01:21PM +, Yu, Fenghua wrote:
> > > > From: Jacob Shin [mailto:jacob.s...@amd.com]
> > > > The follow
On Fri, May 24, 2013 at 10:43:50AM +0200, Borislav Petkov wrote:
> On Thu, May 23, 2013 at 10:40:17AM -0500, Jacob Shin wrote:
> > From: Borislav Petkov
> >
> > User-visible so correct it.
> >
> > Signed-off-by: Borislav Petkov
> > Signed-off-by: J
On Thu, May 23, 2013 at 09:01:21PM +, Yu, Fenghua wrote:
> > From: Jacob Shin [mailto:jacob.s...@amd.com]
> > The following patchset adds early microcode patch loading support on
> > AMD systems, on top of the framework introduced by:
> > https://lkml.org/lkml/2012/1
, microcode, intel: Correct typo in printk
Jacob Shin (2):
x86/microcode: vendor abstract out save_microcode_in_initrd()
x86/microcode: early microcode patch loading support on AMD
arch/x86/Kconfig| 16 +-
arch/x86/include/asm/microcode.h|1 -
arch/x86/include
Add support for early microcode patch loading on AMD.
Signed-off-by: Jacob Shin
---
arch/x86/Kconfig | 16 +-
arch/x86/include/asm/microcode.h |1 -
arch/x86/include/asm/microcode_amd.h | 17 ++
arch/x86/include/asm/microcode_intel.h |1 +
arch/x86
Currently save_microcode_in_initrd() is declared in vendor neutural
microcode.h file, but defined in vendor specific
microcode_intel_early.c file. Vendor abstract it out to
microcode_core_early.c with a wrapper function.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/microcode_intel.h
From: Borislav Petkov
User-visible so correct it.
Signed-off-by: Borislav Petkov
Signed-off-by: Jacob Shin
---
arch/x86/kernel/microcode_intel_early.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/microcode_intel_early.c
b/arch/x86/kernel
On Thu, May 23, 2013 at 09:54:23AM +0200, Borislav Petkov wrote:
> On Wed, May 22, 2013 at 08:15:33PM -0500, Jacob Shin wrote:
> > Currently save_microcode_in_initrd() is declared in vendor neutural
> > microcode.h file, but defined in vendor specific
> > microcode_intel
Currently save_microcode_in_initrd() is declared in vendor neutural
microcode.h file, but defined in vendor specific
microcode_intel_early.c file. Vendor abstract it out to
microcode_core_early.c with a wrapper function.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/microcode_intel.h
The following patchset adds early microcode patch loading support on
AMD systems, on top of the framework introduced by:
https://lkml.org/lkml/2012/12/21/193
Jacob Shin (2):
x86/microcode: vendor abstract out save_microcode_in_initrd()
x86/microcode: early microcode patch loading support on
Add support for early microcode patch loading on AMD.
Signed-off-by: Jacob Shin
---
arch/x86/Kconfig | 14 +-
arch/x86/include/asm/microcode_amd.h | 14 ++
arch/x86/kernel/microcode_amd.c| 335
arch/x86/kernel
ntly the code doesn't work for Fam16h afaict, so I didn't wreck
> that did I?
Hi, right, Family 16h does not have perfctr_core, instead it still has
the 4 legacy performance counter registers just like Family 10h, and
so does not have any special constraints as 15h's perfctr_co
of changing userland API and
in kernel turn bp_len into proper AMD hardware breakpoint address
mask.
V2:
Per Oleg's suggestions:
* Moved testing of bp_addr_mask to validate_hw_breakpoint()
* Changed perf tool syntax to mem:[/addr_mask][:access]
Jacob Shin (3):
perf/x86/a
Currently bp_len is given a default value of 4. Allow user to override it:
$ perf stat -e mem:0x1000/8
^
bp_len
If no value is given, it will default to 4 as it did before.
Signed-off-by: Jacob Shin
---
tools/perf/Documentation/perf
from Oleg Nesterov
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h |2 ++
arch/x86/include/asm/debugreg.h |5
arch/x86/include/asm/hw_breakpoint.h |1 +
arch/x86/include/uapi/asm/msr-index.h |4 +++
arch/x86/kernel/cpu/amd.c | 19
On Sat, Apr 27, 2013 at 06:10:28PM +0200, Oleg Nesterov wrote:
> On 04/27, Jacob Shin wrote:
> >
> > On Sat, Apr 27, 2013 at 05:05:10PM +0200, Oleg Nesterov wrote:
> > > ...
> > > > + if (info->mask)
> > > > + set_dr_a
Signed-off-by: Jacob Shin
---
tools/perf/tests/parse-events.c | 55 +++
1 file changed, 55 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 88e2f44..4fd0f96 100644
--- a/tools/perf/tests/parse-events.c
On Sat, Apr 27, 2013 at 07:34:24PM +0200, Oleg Nesterov wrote:
> On 04/27, Oleg Nesterov wrote:
> >
> > On 04/26, Jacob Shin wrote:
> > >
> > > @@ -518,12 +518,10 @@ int parse_events_add_breakpoint(struct list_head
> > > **list, int *idx,
>
On Sat, Apr 27, 2013 at 05:05:10PM +0200, Oleg Nesterov wrote:
> On 04/26, Jacob Shin wrote:
> >
> > Implement hardware breakpoint address mask for AMD Family 16h and
> > above processors. CPUID feature bit indicates hardware support for
> > DRn_ADDR_MASK MSRs. These ma
from Oleg Nesterov
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h |2 ++
arch/x86/include/asm/debugreg.h |5
arch/x86/include/asm/hw_breakpoint.h |1 +
arch/x86/include/uapi/asm/msr-index.h |4 +++
arch/x86/kernel/cpu/amd.c | 19
Per Oleg's suggestions:
* Moved testing of bp_addr_mask to validate_hw_breakpoint()
* Changed perf tool syntax to mem:[/addr_mask][:access]
Jacob Shin (3):
perf/x86/amd: AMD support for bp_len > HW_BREAKPOINT_LEN_8
perf tools: allow user to specify hardware breakpoint bp_len
perf tools: add h
Currently bp_len is given a default value of 4. Allow user to override it:
$ perf stat -e mem:0x1000/8
^
bp_len
If no value is given, it will default to 4 as it did before.
Signed-off-by: Jacob Shin
---
tools/perf/Documentation/perf
Signed-off-by: Jacob Shin
---
tools/perf/tests/parse-events.c | 55 +++
1 file changed, 55 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 88e2f44..4fd0f96 100644
--- a/tools/perf/tests/parse-events.c
On Fri, Apr 26, 2013 at 05:20:44PM +0100, Will Deacon wrote:
> Hi Jacob,
>
> On Fri, Apr 26, 2013 at 12:19:11AM +0100, Jacob Shin wrote:
> > On Thu, Apr 25, 2013 at 10:17:35AM -0700, H. Peter Anvin wrote:
> > > On 04/25/2013 10:06 AM, Oleg Nesterov wrote:
> > > &g
On Thu, Apr 25, 2013 at 10:17:35AM -0700, H. Peter Anvin wrote:
> On 04/25/2013 10:06 AM, Oleg Nesterov wrote:
> >>
> >> The downside is that in userland perf tool we need differing documentation
> >> on what the mask syntax means for each architecture.
> >
> > Personally I think this is acceptabl
On Thu, Apr 25, 2013 at 05:10:35PM +0200, Oleg Nesterov wrote:
> On 04/25, Frederic Weisbecker wrote:
> >
> > 2013/4/23 Jacob Shin :
> > > @@ -286,7 +286,10 @@ struct perf_event_attr {
> > > __u64 config1; /* extension of config */
>
On Wed, Apr 24, 2013 at 10:48:53AM +0100, Will Deacon wrote:
> On Tue, Apr 23, 2013 at 04:18:46PM +0100, Jacob Shin wrote:
> > On Tue, Apr 23, 2013 at 04:02:40PM +0100, Will Deacon wrote:
> > > On Tue, Apr 23, 2013 at 03:40:57PM +0100, Jacob Shin wrote:
> > > > >
On Tue, Apr 23, 2013 at 04:02:40PM +0100, Will Deacon wrote:
> On Tue, Apr 23, 2013 at 03:40:57PM +0100, Jacob Shin wrote:
> > On Tue, Apr 23, 2013 at 09:34:23AM -0500, Jacob Shin wrote:
> > > On Tue, Apr 23, 2013 at 10:54:37AM +0100, Will Deacon wrote:
> > > > Can
On Tue, Apr 23, 2013 at 09:34:23AM -0500, Jacob Shin wrote:
> On Tue, Apr 23, 2013 at 10:54:37AM +0100, Will Deacon wrote:
> > Hi Jacob,
> >
> > On Tue, Apr 23, 2013 at 08:57:02AM +0100, Jacob Shin wrote:
> > > Some architectures (for us, AMD Family 16h) allow for
On Tue, Apr 23, 2013 at 10:54:37AM +0100, Will Deacon wrote:
> Hi Jacob,
>
> On Tue, Apr 23, 2013 at 08:57:02AM +0100, Jacob Shin wrote:
> > Some architectures (for us, AMD Family 16h) allow for "don't care" bit
> > mask to further qualify a hardware breakpo
On Tue, Apr 23, 2013 at 03:18:44PM +0200, Oleg Nesterov wrote:
> On 04/23, Jacob Shin wrote:
> >
> > +__weak int arch_validate_hwbkpt_addr_mask(struct perf_event *bp)
> > +{
> > + return bp->attr.bp_addr_mask == 0;
> > +}
> > +
> > static
Implement hardware breakpoint address mask for AMD Family 16h (and
any other future) processors. CPUID feature bit indicates the hardware
support for DRn_ADDR_MASK MSRs.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h |2 ++
arch/x86/include/asm/debugreg.h |5
* Changed perf tool syntax to mem:[/addr_mask][:access]
Jacob Shin (2):
perf: Add hardware breakpoint address mask
perf/x86/amd: AMD implementation for hardware breakpoint address mask
Suravee Suthikulpanit (2):
perf tools: Add hardware breakpoint address mask event parser
perf tools: Add
Some architectures (for us, AMD Family 16h) allow for "don't care" bit
mask to further qualify a hardware breakpoint address, in order to
trap on range of addresses. Update perf uapi to add bp_addr_mask field.
Signed-off-by: Jacob Shin
---
include/uapi/linux/perf_event.h |
From: Suravee Suthikulpanit
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Jacob Shin
---
tools/perf/tests/parse-events.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index
From: Suravee Suthikulpanit
Allow perf tool to pass in breakpoint address mask to match an address
range, i.e.:
$ perf stat -e mem:0x1000/0xf:w a.out
Will count writes to [0x1000 ~ 0x1010)
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Jacob Shin
---
tools/perf/Documentation/perf
On Sun, Apr 21, 2013 at 07:19:21PM +0200, Oleg Nesterov wrote:
> Not a comment, but the question...
>
> On 04/09, Jacob Shin wrote:
> >
> > --- a/arch/x86/include/asm/hw_breakpoint.h
> > +++ b/arch/x86/include/asm/hw_breakpoint.h
> > @@ -14,6 +14,7 @@ struct arch
On Mon, Apr 22, 2013 at 04:37:15PM -0500, Jacob Shin wrote:
> On Sun, Apr 21, 2013 at 07:02:02PM +0200, Oleg Nesterov wrote:
> > On 04/20, Jacob Shin wrote:
> > >
> > > On Sat, Apr 20, 2013 at 06:53:34PM +0200, Oleg Nesterov wrote:
> > > >
> > >
On Sun, Apr 21, 2013 at 07:02:02PM +0200, Oleg Nesterov wrote:
> On 04/20, Jacob Shin wrote:
> >
> > On Sat, Apr 20, 2013 at 06:53:34PM +0200, Oleg Nesterov wrote:
> > >
> > > And does attr.bp_len "contribute" to the mask?
> > >
> > > I
Commit-ID: 94f4db3590893c600506105b88dab581c7f6f5c8
Gitweb: http://git.kernel.org/tip/94f4db3590893c600506105b88dab581c7f6f5c8
Author: Jacob Shin
AuthorDate: Sun, 21 Apr 2013 13:06:27 -0500
Committer: Ingo Molnar
CommitDate: Mon, 22 Apr 2013 10:10:55 +0200
perf/x86/amd: Fix AMD NB and
Commit-ID: 0cf5f4323b1b51ecca3e952f95110e03ea611882
Gitweb: http://git.kernel.org/tip/0cf5f4323b1b51ecca3e952f95110e03ea611882
Author: Jacob Shin
AuthorDate: Mon, 15 Apr 2013 12:21:22 -0500
Committer: Ingo Molnar
CommitDate: Sun, 21 Apr 2013 17:21:59 +0200
perf/x86/amd: Remove old
On Sun, Apr 21, 2013 at 07:02:32PM +0200, Borislav Petkov wrote:
> On Sun, Apr 21, 2013 at 05:48:36AM -0700, tip-bot for Jacob Shin wrote:
> > Commit-ID: c43ca5091a374c1f6778bd7e4a39a5a10735a917
> > Gitweb:
> > http://git.kernel.org/tip/c43ca5091a374c1f6778bd7e4a39a5
On Sun, Apr 21, 2013 at 07:02:32PM +0200, Borislav Petkov wrote:
> On Sun, Apr 21, 2013 at 05:48:36AM -0700, tip-bot for Jacob Shin wrote:
> > Commit-ID: c43ca5091a374c1f6778bd7e4a39a5a10735a917
> > Gitweb:
> > http://git.kernel.org/tip/c43ca5091a374c1f6778bd7e4a39a5
On Sun, Apr 21, 2013 at 05:48:36AM -0700, tip-bot for Jacob Shin wrote:
> Commit-ID: c43ca5091a374c1f6778bd7e4a39a5a10735a917
> Gitweb: http://git.kernel.org/tip/c43ca5091a374c1f6778bd7e4a39a5a10735a917
> Author: Jacob Shin
> AuthorDate: Fri, 19 Apr 2013 16:34:28 -0500
> C
Commit-ID: c43ca5091a374c1f6778bd7e4a39a5a10735a917
Gitweb: http://git.kernel.org/tip/c43ca5091a374c1f6778bd7e4a39a5a10735a917
Author: Jacob Shin
AuthorDate: Fri, 19 Apr 2013 16:34:28 -0500
Committer: Ingo Molnar
CommitDate: Sun, 21 Apr 2013 11:01:24 +0200
perf/x86/amd: Add support
On Sat, Apr 20, 2013 at 06:53:34PM +0200, Oleg Nesterov wrote:
> On 04/09, Jacob Shin wrote:
> >
> > The following patchset adds address masks to existing perf hardware
> > breakpoint mechanism to allow trapping on an address range (currently
> > only single address)
On Sat, Apr 20, 2013 at 06:22:23PM +0200, Oleg Nesterov wrote:
> On 04/09, Jacob Shin wrote:
> >
> > @@ -612,6 +612,9 @@ static int hw_breakpoint_add(struct perf_event *bp, int
> > flags)
> > if (!(flags & PERF_EF_START))
> > bp->hw.stat
On Fri, Apr 19, 2013 at 08:55:24PM +0200, Peter Zijlstra wrote:
> On Fri, 2013-04-19 at 09:41 -0500, Jacob Shin wrote:
> >
> > Thank you again, for taking the time.
>
> Ah something I just remembered, could you do a patch like the below
> one? That makes things like perf
On Fri, Apr 19, 2013 at 02:27:16PM +0200, Peter Zijlstra wrote:
> On Thu, 2013-04-18 at 11:33 -0500, Jacob Shin wrote:
>
> > Okay, here is V2 which does that. Thanks again in advance for taking
> > the time to look it over.
>
> Awesome, looks good on a first read.. I&
On Tue, Apr 16, 2013 at 11:36:20AM +0200, Ingo Molnar wrote:
>
> * Jacob Shin wrote:
>
> > On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
> > > The following patchset adds address masks to existing perf hardware
> > > breakpoint mechanism to a
On Thu, Apr 18, 2013 at 01:28:54PM +0200, Peter Zijlstra wrote:
> On Mon, 2013-04-15 at 12:21 -0500, Jacob Shin wrote:
> > Add support for AMD Family 15h [and above] northbridge performance
> > counters. MSRs 0xc0010240 ~ 0xc0010247 are shared across all cores
> > that share
On Mon, Apr 15, 2013 at 12:21:21PM -0500, Jacob Shin wrote:
> Per Ingo and Peter Z's request:
> https://lkml.org/lkml/2013/4/10/267
>
> This patchset removes the NB counter support from perf_event_amd.c and
> creates a new PMU instead to add support for both AMD NB and L2I
&
Support for NB counters, MSRs 0xc0010240 ~ 0xc0010247, will be moved
to perf_event_amd_uncore.c in a follow up patch. AMD Family 10h NB
events (events 0xe0 ~ 0xff, on MSRs 0xc001000 ~ 0xc001007) will still
continue to be handled by perf_event_amd.c
Signed-off-by: Jacob Shin
---
arch/x86/kernel
On Tue, Apr 09, 2013 at 12:21:48PM -0500, Jacob Shin wrote:
> The following patchset adds address masks to existing perf hardware
> breakpoint mechanism to allow trapping on an address range (currently
> only single address) on supported architectures.
>
> perf uapi is u
common L2 cache.
We do not enable counter overflow interrupts. Sampling mode and
per-thread events are not supported.
Signed-off-by: Jacob Shin
---
arch/x86/include/asm/cpufeature.h |2 +
arch/x86/include/uapi/asm/msr-index.h |4 +
arch/x86/kernel/cpu/Makefile
Per Ingo and Peter Z's request:
https://lkml.org/lkml/2013/4/10/267
This patchset removes the NB counter support from perf_event_amd.c and
creates a new PMU instead to add support for both AMD NB and L2I
counters.
Jacob Shin (2):
perf, amd: remove NB counter support from perf_event_
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