agree with
Table 9; Error Management Details (PN26G02A pg. 34)
Jeff
On 6/25/19 2:41 AM, Schrempf Frieder wrote:
Hi Jeff,
On 18.06.19 19:08, Jeff Kletsky wrote:
From: Jeff Kletsky
Add initial support for Paragon Technology
PN26G01Ax and PN26G02Ax SPI NAND
Datasheets available at
From: Jeff Kletsky
Add initial support for Paragon Technology
PN26G01Ax and PN26G02Ax SPI NAND
Datasheets available at
http://www.xtxtech.com/upfile/2016082517274590.pdf
http://www.xtxtech.com/upfile/2016082517282329.pdf
Signed-off-by: Jeff Kletsky
---
drivers/mtd/nand/spi/Makefile
From: Jeff Kletsky
These Paragon chips are very similar to other 1Gb/2Gb chips
in terms of their layout and command timings.
One notable difference is that "Minimum number of valid blocks"
(Nvb) is 1003 per Gb, rather than the common 1004. As a result,
the bad-block reservation is
(reduced direct addressees, though still on lists)
On 5/22/19 11:42 PM, Schrempf Frieder wrote:
On 23.05.19 00:05, Jeff Kletsky wrote:
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
and, while it has the same logical layout as the E-series devices
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
Reviewed-by: Frieder Schrempf
---
include/linux/mtd/spinand.h | 30 ++
1
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
Reviewed-by: Frieder Schrempf
---
drivers/mtd/nand/spi/core.c | 2 +-
include/linux/mtd/spinand.h | 4 ++--
2 files changed
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
and, while it has the same logical layout as the E-series devices,
it differs in the SPI interfacing in significant ways.
This support is contingent on previous commits to:
* Add support for two-byte
Addresses changes in macros and related data structures introduced by
commit 377e517b5fa5
mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg
Resolves issue detected by kbuild test robot
Tue, 21 May 2019 17:28:09 +0800
Tue, 21 May 2019 18:17:28 +0800
GD5F1GQ4UFxxG data sheet on
Thanks for the time and suggestions in review.
Commit-message wording revised as suggested.
No changes in patch content.
Supersedes series:
[v2,1/3] mtd: spinand: Add #define-s for page-read ops with three-byte addresses
https://patchwork.ozlabs.org/project/linux-mtd/list/?series=107874
Jeff
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
Reviewed-by: Frieder Schrempf
---
drivers/mtd/nand/spi/core.c | 2 +-
include/linux/mtd/spinand.h | 4 ++--
2 files changed
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
Reviewed-by: Frieder Schrempf
---
include/linux/mtd/spinand.h | 30 ++
1
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
and, while it has the same logical layout as the E-series devices,
it differs in the SPI interfacing in significant ways.
This support is contingent on previous commits to:
* Add support for two-byte
On 5/14/19 11:49 PM, Schrempf Frieder wrote:
On 15.05.19 08:17, Marek Vasut wrote:
On 5/14/19 11:53 PM, Jeff Kletsky wrote:
From: Jeff Kletsky
That #define in $subject is called a macro.
Seems this patch adds a lot of almost duplicate code, can it be somehow
de-duplicated ?
We could add
On 5/14/19 1:01 PM, Miquel Raynal wrote:
Hi Schrempf,
Schrempf Frieder wrote on Tue, 14 May
2019 16:11:28 +:
Hi Jeff,
On 14.05.19 17:42, Jeff Kletsky wrote:
On 5/13/19 6:56 AM, Schrempf Frieder wrote:
Hi Jeff,
[...]
Maybe it would be better to split this patch into three parts
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices
and, while it has the same logical layout as the E-series devices,
it differs in the SPI interfacing in significant ways.
This support is contingent on previous commits to:
* Add support for two-byte
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
---
drivers/mtd/nand/spi/core.c | 2 +-
include/linux/mtd/spinand.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
---
include/linux/mtd/spinand.h | 30 ++
1 file changed, 30 insertions
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
---
include/linux/mtd/spinand.h | 30 ++
1 file changed, 30 insertions
From: Jeff Kletsky
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky
---
include/linux/mtd/spinand.h | 30 ++
1 file changed, 30 insertions
19 matches
Mail list logo
