Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

Hi, On 02/02/16 17:46, Andre Przywara wrote: > Hi Jens, > > thanks for having such an elaborate look! > > On 02/02/16 16:24, Jens Kuske wrote: >> Hi, >> >> On 01/02/16 18:39, Andre Przywara wrote: [..] >>> + >>> + /* dummy clo

Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

4.dtsi > b/arch/arm64/boot/dts/allwinner/a64.dtsi > new file mode 100644 > index 000..8dce10f > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi > @@ -0,0 +1,583 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: > +

Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

arch/arm64/boot/dts/allwinner/a64.dtsi > b/arch/arm64/boot/dts/allwinner/a64.dtsi > new file mode 100644 > index 000..8dce10f > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/a64.dtsi > @@ -0,0 +1,583 @@ > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on th

Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi

Hi, On 02/02/16 17:46, Andre Przywara wrote: > Hi Jens, > > thanks for having such an elaborate look! > > On 02/02/16 16:24, Jens Kuske wrote: >> Hi, >> >> On 01/02/16 18:39, Andre Przywara wrote: [..] >>> + >>> + /* dummy clo

[PATCH] drivers: soc: sunxi: Fix mask generation for SRAM mapping

GENMASK is inclusive on both ends, therefor one has to be subtracted from the width. Also fixes the mask for debug output. Signed-off-by: Jens Kuske --- drivers/soc/sunxi/sunxi_sram.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/sunxi/sunxi_sram.c b

[PATCH] drivers: soc: sunxi: Fix mask generation for SRAM mapping

GENMASK is inclusive on both ends, therefor one has to be subtracted from the width. Also fixes the mask for debug output. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- drivers/soc/sunxi/sunxi_sram.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc

Re: [linux-sunxi] [PATCH resend 2/6] clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i

On 05/12/15 14:16, Chen-Yu Tsai wrote: > The video engine has its own special module clock, consisting of a clock > gate, configurable dividers, and a reset control. > Hi, I've tested these patches on A20, everything works so far. I only read some bits from a random bitstream, so nothing fancy

Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

On 07/12/15 09:12, Jean-Francois Moine wrote: > On Fri, 4 Dec 2015 22:24:42 +0100 > Jens Kuske wrote: > >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> >> Signed-off-by: Jens Kuske >>

Re: [linux-sunxi] [PATCH resend 2/6] clk: sunxi: Add VE (Video Engine) module clock driver for sun[457]i

On 05/12/15 14:16, Chen-Yu Tsai wrote: > The video engine has its own special module clock, consisting of a clock > gate, configurable dividers, and a reset control. > Hi, I've tested these patches on A20, everything works so far. I only read some bits from a random bitstream, so nothing fancy

Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

On 07/12/15 09:12, Jean-Francois Moine wrote: > On Fri, 4 Dec 2015 22:24:42 +0100 > Jens Kuske <jensku...@gmail.com> wrote: > >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> >> Signed-

[PATCH v5 4/4] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot

[PATCH v5 1/4] clk: sunxi: Add H3 clocks support

between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + drivers/clk/sunxi/Makefile

[PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske --- arch/arm/boot/dts/sun8i-h3.dtsi | 497 1 file changed, 497 insertions(+) create mode 100644 arch/arm/boot/dts

[PATCH v5 2/4] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers

[PATCH v5 0/4] ARM: sunxi: Allwinner H3 support

cr" to match user manual - Remove the address paragraph from GPL in dts and dtsi - Some style cleanup and line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Jens Jens Kuske (4): clk: sunxi: Add H3 clocks support pinctr

[PATCH v5 4/4] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske <jensku...@gmail.com> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts

[PATCH v5 1/4] clk: sunxi: Add H3 clocks support

between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + d

[PATCH v5 2/4] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/K

[PATCH v5 0/4] ARM: sunxi: Allwinner H3 support

cr" to match user manual - Remove the address paragraph from GPL in dts and dtsi - Some style cleanup and line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Jens Jens Kuske (4): clk: sunxi: Add H3 clocks support pinctr

[PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 497 1 file changed, 497 insertions(+) create mode

Re: [linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On 23/11/15 11:50, Hans de Goede wrote: > HI, > > On 23-11-15 09:57, Maxime Ripard wrote: >> Hi, >> >> On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote: >>>>> + bus_gates: clk@01c20060 { >&

Re: [linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On 23/11/15 11:50, Hans de Goede wrote: > HI, > > On 23-11-15 09:57, Maxime Ripard wrote: >> Hi, >> >> On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote: >>>>> + bus_gates: clk@01c20060 { >&

Re: [PATCH v4 3/6] pinctrl: sunxi: Add H3 PIO controller support

On 30/10/15 09:08, Chen-Yu Tsai wrote: > Hi, > > On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote: >> The H3 uses the same pin controller as previous SoC's from Allwinner. >> Add support for the pins controlled by the main PIO controller. >> >> Signed-off-by

Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

Hi, On 30/10/15 08:33, Chen-Yu Tsai wrote: > Hi, > > On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote: >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> >> Signed-off-by: Jens Kuske >

Re: [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

On 30/10/15 08:46, Chen-Yu Tsai wrote: > On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske wrote: [..] >> @@ -991,8 +985,30 @@ static void __init sunxi_divs_clk_setup(struct >> device_node *node, >> if (data->ndivs) >> ndivs = data->ndivs; &g

Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

Hi, On 30/10/15 09:27, Arnd Bergmann wrote: > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote: >> >> +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev, >> + const struct of_phandle_args *reset_spec) >> +{ &g

Re: [PATCH v4 2/6] clk: sunxi: Add H3 clocks support

Hi, On 30/10/15 09:28, Arnd Bergmann wrote: > On Tuesday 27 October 2015 17:50:22 Jens Kuske wrote: >> + of_property_read_string_index(node, "clock-output-names", >> + i, _name); >> + >> +

Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

Hi, On 30/10/15 09:27, Arnd Bergmann wrote: > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote: >> >> +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev, >> + const struct of_phandle_args *reset_spec) >> +{ &g

Re: [PATCH v4 2/6] clk: sunxi: Add H3 clocks support

Hi, On 30/10/15 09:28, Arnd Bergmann wrote: > On Tuesday 27 October 2015 17:50:22 Jens Kuske wrote: >> + of_property_read_string_index(node, "clock-output-names", >> + i, _name); >> + >> +

Re: [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

On 30/10/15 08:46, Chen-Yu Tsai wrote: > On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jensku...@gmail.com> wrote: [..] >> @@ -991,8 +985,30 @@ static void __init sunxi_divs_clk_setup(struct >> device_node *node, >> if (data->ndivs) >>

Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

Hi, On 30/10/15 08:33, Chen-Yu Tsai wrote: > Hi, > > On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jensku...@gmail.com> wrote: >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> >> Signed-

Re: [PATCH v4 3/6] pinctrl: sunxi: Add H3 PIO controller support

On 30/10/15 09:08, Chen-Yu Tsai wrote: > Hi, > > On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jensku...@gmail.com> wrote: >> The H3 uses the same pin controller as previous SoC's from Allwinner. >> Add support for the pins controlled by the main PIO controller. >

Re: [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets

On 22/10/15 09:58, Maxime Ripard wrote: > On Wed, Oct 21, 2015 at 06:20:26PM +0200, Jens Kuske wrote: >> Adding a new compatible allows us to define SoC specific behaviour >> if necessary, for example forcing a particular device out of reset >> even if no driver is actually u

[PATCH v4 0/6] ARM: sunxi: Introduce Allwinner H3 support

line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Jens Jens Kuske (6): clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add H3 clocks support pinctrl: sunxi: Add H3 PIO controller s

[PATCH v4 2/6] clk: sunxi: Add H3 clocks support

between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + drivers/clk/sunxi/Makefile

[PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

The H3 bus resets have some holes between the registers, so we add an of_xlate() function to skip them according to the datasheet. Signed-off-by: Jens Kuske --- .../bindings/reset/allwinner,sunxi-clock-reset.txt | 1 + drivers/reset/reset-sunxi.c| 30

[PATCH v4 6/6] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot

[PATCH v4 3/6] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske Acked-by: Maxime Ripard --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig

[PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske --- arch/arm/boot/dts/sun8i-h3.dtsi | 482 1 file changed, 482 insertions(+) create mode 100644 arch/arm/boot/dts

[PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. Signed-off-by: Jens Kuske --- drivers/clk/sunxi/clk-sunxi.c | 38 +++--- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/clk

Re: [PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets

On 22/10/15 09:58, Maxime Ripard wrote: > On Wed, Oct 21, 2015 at 06:20:26PM +0200, Jens Kuske wrote: >> Adding a new compatible allows us to define SoC specific behaviour >> if necessary, for example forcing a particular device out of reset >> even if no driver is actually u

[PATCH v4 6/6] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske <jensku...@gmail.com> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts

[PATCH v4 3/6] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <jensku...@gmail.com> Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> --- .../bindings/pinctrl/allwinner,sunxi

[PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 482 1 file changed, 482 insertions(+) create mode

[PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- drivers/clk/sunxi/clk-sunxi.c | 38 +++--- 1 file changed, 27 insertions(+), 11 deletions(-)

[PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

The H3 bus resets have some holes between the registers, so we add an of_xlate() function to skip them according to the datasheet. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- .../bindings/reset/allwinner,sunxi-clock-reset.txt | 1 + drivers/reset/reset-s

[PATCH v4 2/6] clk: sunxi: Add H3 clocks support

between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + d

[PATCH v4 0/6] ARM: sunxi: Introduce Allwinner H3 support

line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Jens Jens Kuske (6): clk: sunxi: Let divs clocks read the base factor clock name from devicetree clk: sunxi: Add H3 clocks support pinctrl: sunxi: Add H3 PIO controller s

Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On 22/10/15 11:14, Maxime Ripard wrote: > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: >> On Thu, 22 Oct 2015 10:47:35 +0200 >> Maxime Ripard wrote: >> >>> Not really. The uart0 reset is the bit 16, in the reset register 4. >>> >>> 4 * 32 + 16 = 44. >>> >>> Not 112, but

Re: [linux-sunxi] [PATCH 2/6] clk: sunxi: Add H3 clocks support

On 22/10/15 02:15, Julian Calaby wrote: > > This hunk should be in patch 1: Indeed, Thanks. Jens > >> @@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct >> device_node *node, >> >> for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 && >>

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

Hi, On 21/10/15 21:18, Hans de Goede wrote: > > Great to see that you've started working on this again. Last weekend I > ended up working on this too together with Reinder E.N. de Haan > > (added to the Cc). > > We took a slightly different approach for the gates clocks, see: > >

Re: [linux-sunxi] [PATCH 2/6] clk: sunxi: Add H3 clocks support

On 22/10/15 02:15, Julian Calaby wrote: > > This hunk should be in patch 1: Indeed, Thanks. Jens > >> @@ -1000,9 +1005,8 @@ static void __init sunxi_divs_clk_setup(struct >> device_node *node, >> >> for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 && >>

Re: [PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

Hi, On 21/10/15 21:18, Hans de Goede wrote: > > Great to see that you've started working on this again. Last weekend I > ended up working on this too together with Reinder E.N. de Haan > > (added to the Cc). > > We took a slightly different approach for the gates clocks,

Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

On 22/10/15 11:14, Maxime Ripard wrote: > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: >> On Thu, 22 Oct 2015 10:47:35 +0200 >> Maxime Ripard wrote: >> >>> Not really. The uart0 reset is the bit 16, in the reset register 4. >>> >>> 4 * 32

[PATCH 3/6] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers

[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske --- arch/arm/boot/dts/sun8i-h3.dtsi | 499 1 file changed, 499 insertions(+) create mode 100644 arch/arm/boot/dts

[PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets

Adding a new compatible allows us to define SoC specific behaviour if necessary, for example forcing a particular device out of reset even if no driver is actually using it. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt | 1 + drivers

[PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot

[PATCH 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. Signed-off-by: Jens Kuske --- drivers/clk/sunxi/clk-sunxi.c | 39 --- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/clk

[PATCH 2/6] clk: sunxi: Add H3 clocks support

between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + drivers/clk/sunxi/Makefile

[PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

ot;scr" to "sim" and clock "sim" to "scr" to match user manual - Remove the address paragraph from GPL in dts and dtsi - Some style cleanup and line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Je

[PATCH 0/6] ARM: sunxi: Introduce Allwinner H3 support

ot;scr" to "sim" and clock "sim" to "scr" to match user manual - Remove the address paragraph from GPL in dts and dtsi - Some style cleanup and line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Je

[PATCH 2/6] clk: sunxi: Add H3 clocks support

between AHB1 and PLL6/2. The documentation isn't totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- Documentation/devicetree/bindings/clock/sunxi.txt | 2 + d

[PATCH 4/6] reset: sunxi: Add compatible for Allwinner H3 bus resets

Adding a new compatible allows us to define SoC specific behaviour if necessary, for example forcing a particular device out of reset even if no driver is actually using it. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- Documentation/devicetree/bindings/reset/allwinner,sunxi

[PATCH 6/6] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske <jensku...@gmail.com> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts

[PATCH 3/6] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/K

[PATCH 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- drivers/clk/sunxi/clk-sunxi.c | 39 --- 1 file changed, 28 insertions(+), 11 del

[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske <jensku...@gmail.com> --- arch/arm/boot/dts/sun8i-h3.dtsi | 499 1 file changed, 499 insertions(+) create mode

Re: [PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates

Hi, On 05/17/15 14:50, Maxime Ripard wrote: > Hi Jens, > > On Fri, May 15, 2015 at 06:38:52PM +0200, Jens Kuske wrote: >> Some newer sunxi SoCs (A83T, H3) don't have individual registers for >> AHB1, APB1 and APB2 gates anymore, but one big bus gates area where each >>

Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

Hi, On 05/16/15 04:10, Chen-Yu Tsai wrote: > 2015年5月16日 上午12:39於 "Jens Kuske" 寫道： [..] >> @@ -1141,6 +1133,7 @@ static void __init sunxi_divs_clk_setup(struct > device_node *node, >> struct clk_gate *gate = NULL; >> struct clk_fixed_fac

Re: [PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support

Hi, On 05/17/15 16:30, Maxime Ripard wrote: > On Fri, May 15, 2015 at 06:38:57PM +0200, Jens Kuske wrote: >> The H3 uses the same pin controller as previous SoC's from Allwinner. >> Add support for the pins controlled by the main PIO controller. >> >>

Re: [PATCH v2 06/10] clk: sunxi: Add H3 clocks support

Hi, On 05/17/15 16:27, Maxime Ripard wrote: > On Fri, May 15, 2015 at 06:38:56PM +0200, Jens Kuske wrote: >> The H3 clock control unit is similar to the those of other sun8i family >> members like the A23. >> >> It makes use of the new multiple parents option

Re: [PATCH v2 08/10] reset: sunxi: Add compatible for Allwinner H3 bus resets

On 05/17/15 16:31, Maxime Ripard wrote: > On Fri, May 15, 2015 at 06:38:58PM +0200, Jens Kuske wrote: >> Adding a new compatible allows us to define SoC specific behaviour >> if necessary, for example forcing a particular device out of reset >> even if no driver is actually u

Re: [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

Hi, On 05/17/15 16:19, Maxime Ripard wrote: > On Fri, May 15, 2015 at 06:38:54PM +0200, Jens Kuske wrote: >> Add a remove function and export the init and remove function >> to allow us to build the SoC specific drivers as modules. >> >> Signed-off-by: Jens Kuske >&

Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

On 05/17/15 15:06, Maxime Ripard wrote: > On Fri, May 15, 2015 at 06:38:53PM +0200, Jens Kuske wrote: >> Currently, the sunxi clock driver gets the name for the base factor clock >> of divs clocks from the name field in factors_data. This prevents reusing >> of the fa

Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

On 05/17/15 15:06, Maxime Ripard wrote: On Fri, May 15, 2015 at 06:38:53PM +0200, Jens Kuske wrote: Currently, the sunxi clock driver gets the name for the base factor clock of divs clocks from the name field in factors_data. This prevents reusing of the factor clock for clocks with same

Re: [PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support

Hi, On 05/17/15 16:30, Maxime Ripard wrote: On Fri, May 15, 2015 at 06:38:57PM +0200, Jens Kuske wrote: The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske jensku...@gmail.com

Re: [PATCH v2 06/10] clk: sunxi: Add H3 clocks support

Hi, On 05/17/15 16:27, Maxime Ripard wrote: On Fri, May 15, 2015 at 06:38:56PM +0200, Jens Kuske wrote: The H3 clock control unit is similar to the those of other sun8i family members like the A23. It makes use of the new multiple parents option for the bus gates. Some of the gates use

Re: [PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates

Hi, On 05/17/15 14:50, Maxime Ripard wrote: Hi Jens, On Fri, May 15, 2015 at 06:38:52PM +0200, Jens Kuske wrote: Some newer sunxi SoCs (A83T, H3) don't have individual registers for AHB1, APB1 and APB2 gates anymore, but one big bus gates area where each gate can have a different parent

Re: [PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

Hi, On 05/16/15 04:10, Chen-Yu Tsai wrote: 2015年5月16日 上午12:39於 Jens Kuske jensku...@gmail.com寫道： [..] @@ -1141,6 +1133,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, struct clk_gate *gate = NULL; struct clk_fixed_factor *fix_factor; struct

Re: [PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

Hi, On 05/17/15 16:19, Maxime Ripard wrote: On Fri, May 15, 2015 at 06:38:54PM +0200, Jens Kuske wrote: Add a remove function and export the init and remove function to allow us to build the SoC specific drivers as modules. Signed-off-by: Jens Kuske jensku...@gmail.com --- drivers/pinctrl

Re: [PATCH v2 08/10] reset: sunxi: Add compatible for Allwinner H3 bus resets

On 05/17/15 16:31, Maxime Ripard wrote: On Fri, May 15, 2015 at 06:38:58PM +0200, Jens Kuske wrote: Adding a new compatible allows us to define SoC specific behaviour if necessary, for example forcing a particular device out of reset even if no driver is actually using it. Signed-off

[PATCH v2 01/10] Documentation: sunxi: Update Allwinner SoC documentation

There are some new Allwinner SoCs available, namely A33, A83T and H3. Update the documentation to mention those and the related documents. Signed-off-by: Jens Kuske --- Documentation/arm/sunxi/README | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git

[PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. The sun4i PLL5 clock doesn't have a output for the base factor clock, so we still have to use the name field there. Signed-off-by: Jens Kuske --- drivers/clk/sunxi/clk-sunxi.c | 22

[PATCH v2 00/10] ARM: sunxi: Introduce Allwinner H3 support

t; to "sim" and clock "sim" to "scr" to match user manual - Remove the address paragraph from GPL in dts and dtsi - Some style cleanup and line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Jens

[PATCH v2 06/10] clk: sunxi: Add H3 clocks support

totally clear about which devices belong to AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner kernel source code. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/clock/sunxi.txt | 6 +++ drivers/clk/sunxi/clk-sunxi.c | 50

[PATCH v2 04/10] pinctrl: sunxi: Prepare for building SoC specific drivers as modules

Add a remove function and export the init and remove function to allow us to build the SoC specific drivers as modules. Signed-off-by: Jens Kuske --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 25 +++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 ++ 2 files changed, 21

[PATCH v2 05/10] ARM: sunxi: Introduce Allwinner H3 support

The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar to other sun8i family SoCs like the A23. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/sunxi.c

[PATCH v2 08/10] reset: sunxi: Add compatible for Allwinner H3 bus resets

Adding a new compatible allows us to define SoC specific behaviour if necessary, for example forcing a particular device out of reset even if no driver is actually using it. Signed-off-by: Jens Kuske --- Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt | 1 + drivers

[PATCH v2 10/10] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff --git a/arch/arm/boot

[PATCH v2 09/10] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske --- arch/arm/boot/dts/sun8i-h3.dtsi | 446 1 file changed, 446 insertions(+) create mode 100644 arch/arm/boot/dts

[PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 8 + drivers

[PATCH v2 02/10] clk: sunxi: Add support for multiple parents to gates

to the gates_data structure, which allows us to specify an array of parent indices for every single gate. Signed-off-by: Jens Kuske --- drivers/clk/sunxi/clk-sunxi.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c

[PATCH v2 00/10] ARM: sunxi: Introduce Allwinner H3 support

and clock sim to scr to match user manual - Remove the address paragraph from GPL in dts and dtsi - Some style cleanup and line wrapping in dtsi - Add ARM architected timers - dmaengine isn't included anymore, it is merged already Best Regards, Jens Jens Kuske (10): Documentation: sunxi: Update

[PATCH v2 03/10] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

-output-names in the devicetree. It also removes the name field where possible and merges the sun4i PLL5 and PLL6 clocks. The sun4i PLL5 clock doesn't have a output for the base factor clock, so we still have to use the name field there. Signed-off-by: Jens Kuske jensku...@gmail.com --- drivers/clk

[PATCH v2 01/10] Documentation: sunxi: Update Allwinner SoC documentation

There are some new Allwinner SoCs available, namely A33, A83T and H3. Update the documentation to mention those and the related documents. Signed-off-by: Jens Kuske jensku...@gmail.com --- Documentation/arm/sunxi/README | 18 +- 1 file changed, 17 insertions(+), 1 deletion

[PATCH v2 07/10] pinctrl: sunxi: Add H3 PIO controller support

The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske jensku...@gmail.com --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig

[PATCH v2 09/10] ARM: dts: sunxi: Add Allwinner H3 DTSI

The Allwinner H3 is a home entertainment system oriented SoC with four Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Jens Kuske jensku...@gmail.com --- arch/arm/boot/dts/sun8i-h3.dtsi | 446 1 file changed, 446 insertions(+) create mode 100644

[PATCH v2 10/10] ARM: dts: sun8i: Add Orange Pi Plus support

-off-by: Jens Kuske jensku...@gmail.com --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 77 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts diff

[PATCH v2 05/10] ARM: sunxi: Introduce Allwinner H3 support

The Allwinner H3 is a quad-core Cortex-A7-based SoC. It is very similar to other sun8i family SoCs like the A23. Signed-off-by: Jens Kuske jensku...@gmail.com --- Documentation/devicetree/bindings/arm/sunxi.txt | 1 + arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi

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