circumstances (in combination with
another H265 decoding bug) causes driver lock up. With this fix decoding
is still broken (green output) but at least driver doesn't lock up.
Fixes: 86caab29da78 ("media: cedrus: Add HEVC/H.265 decoding support")
Signed-off-by: Jernej Skrabec
---
This is
problems with external
oscillator.
In order to fix RTC and related issues (HDMI-CEC and suspend/resume with
Crust) on all boards, switch to internal oscillator.
Fixes: 32507b868119 ("arm64: dts: allwinner: h6: Move ext. oscillator to board
DTs")
Signed-off-by: Jernej Skrabec
---
arch/arm6
Beelink X2 has power button. Add node for it.
Signed-off-by: Jernej Skrabec
---
Changes from v1:
- renamed node name so it doesn't contain underscores
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink
Beelink X2 has power button. Add node for it.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 62b5280ec093
dependant. See i.MX6
documentation for explanation of those values for similar PHY.
Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 26 +-
1 file
splay Engine support")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/su
on replaced patch 4)
- Added some comments in patch 2
- Replaced patch 4 (see commit log for explanation)
Jernej Skrabec (5):
clk: sunxi-ng: mp: fix parent rate change flag check
drm/sun4i: tcon: set sync polarity for tcon1 channel
drm/sun4i: dw-hdmi: always set clock rate
drm/sun4i: Fix H6 HDMI
("drm/sun4i: Add support for H6 DW HDMI controller")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 -
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git
CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
one. Fix that.
Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu_mp.c
in HW and fix the comment.
Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 ++
1 file changed, 2 insertions(+), 4 deletion
in HW and fix the comment.
Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 ++
1 file changed, 2 insertions(+), 4 deletion
CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
one. Fix that.
Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu_mp.c
splay Engine support")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/su
("drm/sun4i: Add support for H6 DW HDMI controller")
Reviewed-by: Chen-Yu Tsai
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 -
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git
for explanation)
Jernej Skrabec (5):
clk: sunxi-ng: mp: fix parent rate change flag check
drm/sun4i: tcon: set sync polarity for tcon1 channel
drm/sun4i: dw-hdmi: always set clock rate
drm/sun4i: Fix H6 HDMI PHY configuration
drm/sun4i: dw-hdmi: Fix max. frequency for H6
drivers/clk/sunxi-ng
dependant. See i.MX6
documentation for explanation of those values for similar PHY.
Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 26 +-
1 file
cpce value for 594 MHz is set differently in BSP driver. Fix that.
Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
in HW and fix the comment.
Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu
("drm/sun4i: Add support for H6 DW HDMI controller")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 -
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu
splay Engine support")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 24
drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu
CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
one. Fix that.
Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
Tested-by: Andre Heider
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu_mp.c | 2 +-
1 file changed, 1
controller. Patch 4 fixes cpce PHY setting for 594 MHz. Patch 5 fixes
comment and clock rate limit (wrong reasoning).
Please take a look.
Best regards,
Jernej
Jernej Skrabec (5):
clk: sunxi-ng: mp: fix parent rate change flag check
drm/sun4i: tcon: set sync polarity for tcon1 channel
drm
Bluetooth module on BananaPi M2 Plus can also be used for streaming
audio. However, for that case higher UART speed is required.
Add a max-speed property.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
Bluetooth module on BananaPi M2 Zero can also be used for streaming
audio. However, for that case higher UART speed is required.
Add a max-speed property.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 1 +
1 file changed, 1 insertion(+)
diff --git
PineH64 model B has wifi+bt combo module. Wifi is already supported, so
lets add also bluetooth node.
Signed-off-by: Jernej Skrabec
---
.../dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6
DE3 supports 10-bit formats, so it's only naturally to also support
BT2020 encoding.
Add support for it.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 12 +++-
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 2 ++
2 files changed, 13 insertions(+), 1 deletion
YUV to RGB matrices are almost identical to YVU to RGB matrices. They
only have second and third column reversed. Do that reversion in code in
order to lower amount of static data and redundancy.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 99
Rework DE3 CSC macros to take just one coordinate instead of two. This
will make its usage easier in subsequent commit.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 2 +-
drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++
2 files changed, 3 insertions(+), 5 deletions
This short series reworks CSC handling to remove duplicated constants
(patch 1 and 2) and adds BT2020 encoding to DE3 (patch 3).
Please take a look.
Best regards,
Jernej
Jernej Skrabec (3):
drm/sun4i: csc: Rework DE3 CSC macros
drm/sun4i: de2/de3: Remove redundant CSC matrices
drm/sun4i
ement zpos for DE2")
Fixes: d8b3f454dab4 ("drm/sun4i: sun8i: Avoid clearing blending order at each
atomic commit")
Signed-off-by: Roman Stratiienko
[rebased, addressed comments]
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c| 57 +--
Deinterlace core is completely compatible to H3.
Add a node for it.
Signed-off-by: Jernej Skrabec
---
Note: I didn't add H5 fallback, since the only reason why this node
is not in common H3/H5 dtsi is that it's located on different addresses.
If anyone feel fallback compatible is needed, I'll
These two patches add support for deinterlace core found on R40. It's
compatible to H3 one, so only DT node is needed.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (2):
dt-bindings: media: Add Allwinner R40 deinterlace compatible
ARM: dts: sun8i: r40: Add deinterlace node
-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 7907569e7b5c..d5ad3b9efd12 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts
Allwinner R40 SoC also contains deinterlace core, compatible to H3.
Add compatible string for it.
Signed-off-by: Jernej Skrabec
---
.../bindings/media/allwinner,sun8i-h3-deinterlace.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/media
igure reference field")
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
index 781c84a9b1b7.
This short series fixes two issues:
1. conformance to v4l2 request api specifications
2. regression in h264 video decoding introduced during h264 api rework
Please take a look.
Best regards,
Jernej
Jernej Skrabec (2):
media: cedrus: Remove checking for required controls
media: cedrus: Fix
that mechanism.
Note that this mechanism with static required flag isn't very good
anyway because need for control is usually signaled in other controls.
Fixes: 50e761516f2b ("media: platform: Add Cedrus VPU decoder driver")
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/su
nxi-ng: Add A64 clocks")
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 5f66bf
it for all variants
except for V3s.
Signed-off-by: Jernej Skrabec
---
Note: this should be merged after both of these PRs:
https://patchwork.linuxtv.org/project/linux-media/patch/8cf5021f-559c-5ea8-f1f0-250c00bc1...@xs4all.nl/
https://patchwork.linuxtv.org/project/linux-media/patch/5dbd468d-1d10-e0c8-43f0
that bitstream
parsing functions set some internal VPU state, which is later necessary
for proper decoding. Biggest suspect is "VP8 probs update" trigger.
Signed-off-by: Jernej Skrabec
[addressed issues from reviewer]
Signed-off-by: Emmanuel Gil Peyrot
---
Changes in v3:
- addresse
RX/TX delay on OrangePi One Plus board is set on PHY. Reflect that in
ethernet node.
Fixes: 7ee32a17e0d6 ("arm64: dts: allwinner: h6: orangepi-one-plus: Enable
ethernet")
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts | 2 +-
1 file
PineH64 model B contains RTL8723CS wifi+bt combo module.
Since bluetooth support is not yet squared away, only wifi is enabled
for now.
Acked-by: Chen-Yu Tsai
Signed-off-by: Jernej Skrabec
---
Changes from v1:
- added Chen-Yu tag
- added vqmmc-supply
.../dts/allwinner/sun50i-h6-pine-h64
PineH64 model B contains RTL8723CS wifi+bt combo module.
Since bluetooth support is not yet squared away, only wifi is enabled
for now.
Signed-off-by: Jernej Skrabec
---
.../dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch
Ethernet PHY on BananaPi M2 Ultra provides RX and TX delays. Fix
ethernet node to reflect that fact.
Fixes: c36fd5a48bd2 ("ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable GMAC
ethernet controller")
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
e H64")
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index af85b2074867..96
RX and TX delay are provided by ethernet PHY. Reflect that in ethernet
node.
Fixes: 44a94c7ef989 ("arm64: dts: allwinner: H5: Restore EMAC changes")
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +-
1 file changed, 1 insertion(+),
t the fact that PHY provides TX delay.
Fixes: 94f442886711 ("arm64: dts: allwinner: A64: Restore EMAC changes")
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/
RX/TX delay on OrangePi Win board is set on PHY. Reflect that in
ethernet node.
Fixes: 93d6a27cfcc0 ("arm64: dts: allwinner: a64: Orange Pi Win: Add Ethernet
node")
Signed-off-by: Jernej Skrabec
---
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 2 +-
1 file changed, 1
If scaling matrix control is present, VPU should not use default matrix.
Fix that.
Fixes: b3a23db0e2f8 ("media: cedrus: Use H264_SCALING_MATRIX only when
required")
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +-
1 file changed, 1 inser
)
Reported-by: Roman Stratiienko
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 22c8c5375d0d..c0147af6a
Video engine in R40 is very similar to that in A33 but it runs on lower
speed, at least according to OS images released by board designer.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/staging
Allwinner R40 has system controller similar to that in A10.
Add compatibles for system controller and sram c1 region.
Signed-off-by: Jernej Skrabec
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git
a/Documentation
Allwinner R40 SoC contains video engine. Add compatible for it.
Signed-off-by: Jernej Skrabec
---
.../bindings/media/allwinner,sun4i-a10-video-engine.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
Allwinner R40 has system controller and SRAM C1 region similar to that
in A10.
Add nodes for them.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot
Allwinner R40 SoC has a video engine.
Add a node for it.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 0c7526365896..7907569e7b5c
Allwinner R40 SoC contains video engine very similar to that in A33.
First two patches add system controller nodes and the rest of them
add support for Cedrus VPU.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (5):
dt-bindings: sram: allwinner,sun4i-a10-system-control: Add R40
Allwinner R40 has two IR cores, add nodes for them.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d481fe7989b8
Allwinner R40 has very similar IR core to that found in A31.
Add compatible for R40 and while at it, sort compatibles by family.
Signed-off-by: Jernej Skrabec
---
.../bindings/media/allwinner,sun4i-a10-ir.yaml | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
This series first adds nodes to R40 DTSI and then enable IR receiver
for BananaPi M2 Ultra board.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (3):
dt-bindings: media: allwinner,sun4i-a10-ir: Add R40 compatible
ARM: dts: sun8i: r40: Add IR nodes
ARM: dts: sun8i: r40: bananapi
BananaPi M2 Ultra has IR receiver connected to IR0.
Enable it.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi
Audio cores need specific clock rates which can't be simply obtained by
adjusting integer multipliers and dividers. HW for such cases supports
delta-sigma modulation which enables fractional multipliers.
Port H3 delta-sigma table to R40. They have identical audio PLLs.
Signed-off-by: Jernej
Allwinner R40 contains DMA engine similar to that in A64.
Following two patches enable it so DMA users can be added later.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (2):
dt-bindings: dma: allwinner,sun50i-a64-dma: Add R40 compatible
ARM: dts: sun8i: r40: Add DMA node
Allwinner R40 SoC has DMA with 16 channels and 31 request sources.
Add a node for it.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index
R40 has DMA engine which is basically the same as that in A64, with only
known difference being number of request sources and number of channels.
Add compatible for it.
Signed-off-by: Jernej Skrabec
---
.../bindings/dma/allwinner,sun50i-a64-dma.yaml | 9 ++---
1 file changed, 6
to 3.3 V in order to fix this.
Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2
Ultra")
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Following two patches enable Mali400 GPU on Allwinner R40 SoC. At this
point I didn't add table for frequency switching because it would
require far more testing and defaults work stable and reasonably well.
Please take a look.
Best regards,
Jernej
Jernej Skrabec (2):
dt-bindings: gpu: mali
Allwinner R40 SoC contains Mali400, so add its specific compatible to
bindings.
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
b
R40 has Mali400 GP2 GPU. Add a node for it.
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-r40.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index b782041e0e04..b82031b19893 100644
caching support in regmap which is also
used here. Such fix is also easier to backport in stable kernels.
Fixes: 9d75b8c0b999 ("drm/sun4i: add support for Allwinner DE2 mixers")
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 12
1 file changed, 12
that bitstream
parsing functions set some internal VPU state, which is later necessary
for proper decoding. Biggest suspect is "VP8 probs update" trigger.
Signed-off-by: Jernej Skrabec
---
Changes in v2:
- rebased on top of current linux-media master branch
drivers/staging/media/su
tested using Kodi on LibreELEC with A64,
H3, H5 and H6 SoCs in slightly different form (flags were transmitted
in MSB bits in index).
Note: I'm not 100% sure if flags for both, top and bottom fields are
needed. Any input here would be welcome.
Please take a look.
Best regards,
Jernej
Jernej
. Flags will tell if reference is meant for top or
bottom field.
Currently the only user of these lists is Cedrus which is just compile
fixed here. Actual usage of newly introduced flags will come in
following commit.
Signed-off-by: Jernej Skrabec
---
.../media/v4l/ext-ctrls-codec.rst
lists.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
index cce527bbdf86..c87717d17ec5
it.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
index c87717d17ec5
that bitstream
parsing functions set some internal VPU state, which is later necessary
for proper decoding. Biggest suspect is "VP8 probs update" trigger.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/Makefile | 3 +-
drivers/staging/media/sunxi/cedrus/cedrus
If VPU supports untiled output, it actually supports several different
YUV 4:2:0 layouts, namely NV12, NV21, YUV420 and YVU420.
Add support for all of them.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 18 +-
.../staging/media/sunxi/cedrus
Allwinner H3 SoC also contains MBUS controller.
Add compatible for it.
Acked-by: Maxime Ripard
Acked-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Allwinner H3 SoC contains deinterlace unit, which can be used in
combination with VPU unit to decode and process interlaced videos.
Add a node for it.
Acked-by: Maxime Ripard
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-h3.dtsi | 13 +
1 file changed, 13 insertions
to process 1920x1080@60i video
smoothly in real time.
Acked-by: Maxime Ripard
Signed-off-by: Jernej Skrabec
---
MAINTAINERS |7 +
drivers/media/platform/Kconfig| 12 +
drivers/media/platform/sunxi/Makefile |1 +
.../media/plat
DT binding
- implemented power management
- replaced regmap with direct io access
- set exclusive clock rate
- renamed DEINTERLACE_FRM_CTRL_COEF_CTRL to DEINTERLACE_FRM_CTRL_COEF_ACCESS
Jernej Skrabec (6):
dt-bindings: bus: sunxi: Add H3 MBUS compatible
clk: sunxi-ng: h3: Export MBUS clock
MBUS clock will be referenced in MBUS controller node.
Export it.
Acked-by: Maxime Ripard
Acked-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 4
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
2 files changed, 1 insertion(+), 5 deletions
CPU.
Acked-by: Maxime Ripard
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 107eeafad20a..66bee3bea633 100644
--- a/arch/arm/boot/dts
Allwinner H3 Deinterlace core is used for deinterlacing interlaced video
content. Core can also be found on some later SoCs, like H5 and R40.
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
.../media/allwinner,sun8i-h3-deinterlace.yaml | 75
MBUS clock will be referenced in MBUS controller node.
Export it.
Acked-by: Maxime Ripard
Acked-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 4
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
2 files changed, 1 insertion(+), 5 deletions
Allwinner H3 SoC contains deinterlace unit, which can be used in
combination with VPU unit to decode and process interlaced videos.
Add a node for it.
Acked-by: Maxime Ripard
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sun8i-h3.dtsi | 13 +
1 file changed, 13 insertions
CPU.
Acked-by: Maxime Ripard
Signed-off-by: Jernej Skrabec
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 107eeafad20a..66bee3bea633 100644
--- a/arch/arm/boot/dts
Allwinner H3 Deinterlace core is used for deinterlacing interlaced video
content. Core can also be found on some later SoCs, like H5 and R40.
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
.../media/allwinner,sun8i-h3-deinterlace.yaml | 75
Allwinner H3 SoC also contains MBUS controller.
Add compatible for it.
Acked-by: Maxime Ripard
Acked-by: Rob Herring
Signed-off-by: Jernej Skrabec
---
Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
to process 1920x1080@60i video
smoothly in real time.
Signed-off-by: Jernej Skrabec
---
MAINTAINERS |7 +
drivers/media/platform/sunxi/Kconfig |1 +
drivers/media/platform/sunxi/Makefile |1 +
drivers/media/platform/sunxi/sun8i-di/Kcon
_COEF_CTRL to DEINTERLACE_FRM_CTRL_COEF_ACCESS
Jernej Skrabec (6):
dt-bindings: bus: sunxi: Add H3 MBUS compatible
clk: sunxi-ng: h3: Export MBUS clock
ARM: dts: sunxi: h3/h5: Add MBUS controller node
dt-bindings: media: Add Allwinner H3 Deinterlace binding
media: sun4i: Add H3 deinterlace dr
This patch enables internal audio codec on OrangePi Win board by
enabling all relevant nodes and adding appropriate routing. Board has
on-board microphone (MIC1) and 3.5 mm jack with stereo audio and
microphone (MIC2).
Signed-off-by: Jernej Skrabec
---
.../dts/allwinner/sun50i-a64-orangepi
Accessing capture queue structue directly is not safe. Use helpers for
that.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus.h | 8 ++--
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff
Reference index count in VE_H264_PPS should come from PPS control.
However, this is not really important, because reference index count is
in our case always overridden by that from slice header.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 8 ++--
1
-by: Jernej Skrabec
---
.../staging/media/sunxi/cedrus/cedrus_h264.c | 30 +--
.../staging/media/sunxi/cedrus/cedrus_regs.h | 3 ++
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c
b/drivers/staging/media/sunxi
it was set to values from slice control.
Patch 3 replaces direct accesses to capture queue from m2m contex with
helpers which was designed exactly for that. It's also safer since
helpers do some checks.
Best regards,
Jernej
Jernej Skrabec (3):
media: cedrus: Fix decoding for some H264 videos
media
GPU PLL was designed with dynamic frequency switching in mind so driver
can adjust rate based on the GPU load.
Allow GPU clock to change parent rate (GPU PLL is the only possible
parent of GPU clock).
Signed-off-by: Jernej Skrabec
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
1 file changed
. If timestamps are different,
it's first slice and viceversa.
Signed-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus.h | 1 +
drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h
b
These helpers are used by stateless codecs when they support multiple
slices per frame and hold capture buffer flag is set. It's expected that
all such codecs will use this code.
Signed-off-by: Jernej Skrabec
---
drivers/media/v4l2-core/v4l2-mem2mem.c | 35 ++
include
-off-by: Jernej Skrabec
---
drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 9 +
drivers/staging/media/sunxi/cedrus/cedrus_hw.c| 8 +---
drivers/staging/media/sunxi/cedrus/cedrus_video.c | 14 ++
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git
From: Hans Verkuil
Add this new V4L2_DEC_CMD_FLUSH decoder command and document it.
Reviewed-by: Boris Brezillon
Reviewed-by: Alexandre Courbot
Signed-off-by: Hans Verkuil
[Adjusted description]
Signed-off-by: Jernej Skrabec
---
Documentation/media/uapi/v4l/vidioc-decoder-cmd.rst | 10
1 - 100 of 597 matches
Mail list logo
