ble
> sys_pll_params_table[] = {
> PLL_PARAMS(62, 1),
> PLL_PARAMS(63, 1),
> PLL_PARAMS(64, 1),
> + PLL_PARAMS(65, 1),
> + PLL_PARAMS(66, 1),
> + PLL_PARAMS(67, 1),
> + PLL_PARAMS(68, 1),
> + PLL_PARAMS(84, 1),
> { /* sentinel */ },
> };
>
Acked-by: Jerome Brunet
ble
> sys_pll_params_table[] = {
> PLL_PARAMS(62, 1),
> PLL_PARAMS(63, 1),
> PLL_PARAMS(64, 1),
> + PLL_PARAMS(65, 1),
> + PLL_PARAMS(66, 1),
> + PLL_PARAMS(67, 1),
> + PLL_PARAMS(68, 1),
> + PLL_PARAMS(84, 1),
> { /* sentinel */ },
> };
>
Acked-by: Jerome Brunet
On Wed, 2018-11-14 at 23:57 +0100, Martin Blumenstingl wrote:
> Now that we have a utility function to check whether the PLL is enabled
> we can also pass that to our clk_ops to let the common clock framework
> know about the status of the hardware clock.
> For now this is of limited use since the
On Wed, 2018-11-14 at 23:57 +0100, Martin Blumenstingl wrote:
> Now that we have a utility function to check whether the PLL is enabled
> we can also pass that to our clk_ops to let the common clock framework
> know about the status of the hardware clock.
> For now this is of limited use since the
e the pll is in reset */
> meson_parm_write(clk->map, >rst, 1);
>
>
With the small comment above taken care of, it makes perfect sense
and it will be valuable to other PLLs, Thx Martin !
Reviewed-by: Jerome Brunet
e the pll is in reset */
> meson_parm_write(clk->map, >rst, 1);
>
>
With the small comment above taken care of, it makes perfect sense
and it will be valuable to other PLLs, Thx Martin !
Reviewed-by: Jerome Brunet
From: Neil Armstrong
Add Libretech aml-s805x-ac board (aka 'La Frite') support
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
Hi Kevin,
Sorry for this resend, I forgot to align to align Neil's recent
patch regarding lines names [0]
This is fixed here.
Cheers
Jerome
[0
From: Neil Armstrong
Add Libretech aml-s805x-ac board (aka 'La Frite') support
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
Hi Kevin,
Sorry for this resend, I forgot to align to align Neil's recent
patch regarding lines names [0]
This is fixed here.
Cheers
Jerome
[0
Add bindings for the Libretech aml-s805x-ac board, aka 'La Frite'.
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/arm/amlogic.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt
b
This patchset adds support for the libretech aml-s805x-ac, aka 'La Frite'
Jerome Brunet (1):
dt-bindings: arm: amlogic: add libretech aml-s805x-ac bindings
Neil Armstrong (1):
arm64: dts: meson: add libretech aml-s805x-ac board
.../devicetree/bindings/arm/amlogic.txt | 1 +
arch
From: Neil Armstrong
Add Libretech aml-s805x-ac board (aka 'La Frite') support
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 249 ++
2 files changed, 250
Add bindings for the Libretech aml-s805x-ac board, aka 'La Frite'.
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/arm/amlogic.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt
b
This patchset adds support for the libretech aml-s805x-ac, aka 'La Frite'
Jerome Brunet (1):
dt-bindings: arm: amlogic: add libretech aml-s805x-ac bindings
Neil Armstrong (1):
arm64: dts: meson: add libretech aml-s805x-ac board
.../devicetree/bindings/arm/amlogic.txt | 1 +
arch
From: Neil Armstrong
Add Libretech aml-s805x-ac board (aka 'La Frite') support
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../amlogic/meson-gxl-s805x-libretech-ac.dts | 249 ++
2 files changed, 250
REG_PULL and REG_PULLEN for a given pin the EE controller. This
is not true for the AO controller.
Fixes: e39f9dd8206a ("pinctrl: meson: fix pinconf bias disable")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
REG_PULL and REG_PULLEN for a given pin the EE controller. This
is not true for the AO controller.
Fixes: e39f9dd8206a ("pinctrl: meson: fix pinconf bias disable")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm/boot
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm/boot
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot
/r/20181029151340.9087-1-jbru...@baylibre.com
[2]: https://lkml.kernel.org/r/20181108104426.1877-1-jbru...@baylibre.com
Jerome Brunet (4):
arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
arm64: dts: meson: disable pad bias for mmc pinmuxes
arm64: dts: meson: consistently
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
/r/20181029151340.9087-1-jbru...@baylibre.com
[2]: https://lkml.kernel.org/r/20181108104426.1877-1-jbru...@baylibre.com
Jerome Brunet (4):
arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux
arm64: dts: meson: disable pad bias for mmc pinmuxes
arm64: dts: meson: consistently
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
Add broadcom bluetooth device on the s400
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 29ccb8ad0de6
Add broadcom bluetooth device on the s400
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 29ccb8ad0de6
The goal of this patchset is to enable SCPI (dvfs and hwmon) the axg
platform. The first patches in this series fix a few issues to acheive
this.
Jerome Brunet (4):
arm64: dts: meson-axg: fix mailbox address
arm64: dts: meson-axg: correct sram shared mem unit-address
Documentation: bindings
Correct the unit-address in the node name of the SRAM shared memory
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson
Enable SCPI on the axg platform, with cpu clock and hwmon
(core temperature) support
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64
The goal of this patchset is to enable SCPI (dvfs and hwmon) the axg
platform. The first patches in this series fix a few issues to acheive
this.
Jerome Brunet (4):
arm64: dts: meson-axg: fix mailbox address
arm64: dts: meson-axg: correct sram shared mem unit-address
Documentation: bindings
Correct the unit-address in the node name of the SRAM shared memory
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson
Enable SCPI on the axg platform, with cpu clock and hwmon
(core temperature) support
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64
MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113.
These mailboxes are needed for SCPI
Fixes: 9d59b708500f ("arm64: dts: meson-axg: add initial A113D SoC DT support")
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file
amlogic,meson-gxbb-scpi-sensors is both the driver and DT but is not
documented. Just add it to amlogic's scpi documentation
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/arm/amlogic,scpi.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
amlogic,meson-gxbb-scpi-sensors is both the driver and DT but is not
documented. Just add it to amlogic's scpi documentation
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/arm/amlogic,scpi.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation
MHU mailbox address is wrong. Fixing it enables the mailboxes on the A113.
These mailboxes are needed for SCPI
Fixes: 9d59b708500f ("arm64: dts: meson-axg: add initial A113D SoC DT support")
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file
Add the secure monitor device to the axg platform.
With this, we can read the SoC serial number.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts
Add the secure monitor device to the axg platform.
With this, we can read the SoC serial number.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm/boot
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot
function, however leaving it undefined is not an option.
This change consistently disable the pad bias for every pinmux functions.
It seems to work well, we can only assume that the necessary bias (if any)
is already provided by the pin function itself.
Signed-off-by: Jerome Brunet
---
arch/arm/boot
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
In some cases (such as a boot from SPI) the bootloader or the ROM code may
leave a bias pull-down on the mmc pins. If so the MMC will fail during the
initialisation.
Explicitly disabling the pinmux solves the problem.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
]. These must be applied before applying this
series, otherwise when requesting 'bias-disable' you'll probably get a
pull-down instead.
[0]: https://lkml.kernel.org/r/20181023160319.27003-1-jbru...@baylibre.com
[1]: https://lkml.kernel.org/r/20181029151340.9087-1-jbru...@baylibre.com
Jerome Brunet (4
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6
]. These must be applied before applying this
series, otherwise when requesting 'bias-disable' you'll probably get a
pull-down instead.
[0]: https://lkml.kernel.org/r/20181023160319.27003-1-jbru...@baylibre.com
[1]: https://lkml.kernel.org/r/20181029151340.9087-1-jbru...@baylibre.com
Jerome Brunet (4
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for
the function definition, the other for the bias. This is not necessary
since we can define the function and the bias in the same subnode.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6
The uart used with bluetooth chipset on the s400 has flow control
available. Let's enable it.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b
The uart used with bluetooth chipset on the s400 has flow control
available. Let's enable it.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b
Cc: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
Hi Kevin,
I'm resending this change because I noticed the previous patch I sent had
references to spdif input which has not been merged yet. This would have
triggered a conflict in your tree.
Hopefully, this new version will apply correctly
Che
Cc: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
Hi Kevin,
I'm resending this change because I noticed the previous patch I sent had
references to spdif input which has not been merged yet. This would have
triggered a conflict in your tree.
Hopefully, this new version will apply correctly
Che
they are never disabled when needed by the
co-processor.
Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Jerome Brunet
---
Hi Stephen,
If you can put this one in clk-fixes as well, it would be awesome.
It is basically the same thing as the change you took th
they are never disabled when needed by the
co-processor.
Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Jerome Brunet
---
Hi Stephen,
If you can put this one in clk-fixes as well, it would be awesome.
It is basically the same thing as the change you took th
hese clocks. We also depends on some clock hand-off mechanism
making its way to CCF, to make sure the clock stays on between its
registration and the SCPI driver probe.
Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Christian Hewitt
Signed-off-by: Jerome Brunet
hese clocks. We also depends on some clock hand-off mechanism
making its way to CCF, to make sure the clock stays on between its
registration and the SCPI driver probe.
Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates")
Signed-off-by: Christian Hewitt
Signed-off-by: Jerome Brunet
Cc: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 30 +--
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 6 ++--
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/
Cc: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 30 +--
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 6 ++--
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/
The efuse found in gx SoC requires a peripheral clock to properly operate.
We have been able to work without it until now because the clock was on by
default, and left on by the CCF. Soon, it will not be the case anymore, so
the device needs to claim the clock it needs
Signed-off-by: Jerome
Jerome
Jerome Brunet (4):
nvmem: meson-efuse: add error message on user_max failure.
nvmem: meson-efuse: bindings: add peripheral clock
arm64: dts: meson-gx: add efuse pclk
nvmem: meson-efuse: add peripheral clock
.../bindings/nvmem/amlogic-efuse.txt | 3 ++
arch/arm64/boot/dts
Add an explicit error message when SM_EFUSE_USER_MAX command fails
Signed-off-by: Jerome Brunet
---
drivers/nvmem/meson-efuse.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c
index d769840d1e18..40b9df1d030d
Get and enable the peripheral clock required by the efuse device.
The driver has been handle to work without it so far because the
clock was left enabled by default but it won't be the case soon.
Signed-off-by: Jerome Brunet
---
drivers/nvmem/meson-efuse.c | 25 +
1 file
Jerome
Jerome Brunet (4):
nvmem: meson-efuse: add error message on user_max failure.
nvmem: meson-efuse: bindings: add peripheral clock
arm64: dts: meson-gx: add efuse pclk
nvmem: meson-efuse: add peripheral clock
.../bindings/nvmem/amlogic-efuse.txt | 3 ++
arch/arm64/boot/dts
Add an explicit error message when SM_EFUSE_USER_MAX command fails
Signed-off-by: Jerome Brunet
---
drivers/nvmem/meson-efuse.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c
index d769840d1e18..40b9df1d030d
Get and enable the peripheral clock required by the efuse device.
The driver has been handle to work without it so far because the
clock was left enabled by default but it won't be the case soon.
Signed-off-by: Jerome Brunet
---
drivers/nvmem/meson-efuse.c | 25 +
1 file
The efuse found in gx SoC requires a peripheral clock to properly operate.
We have been able to work without it until now because the clock was on by
default, and left on by the CCF. Soon, it will not be the case anymore, so
the device needs to claim the clock it needs
Signed-off-by: Jerome
Add the required peripheral clock for the efuse device.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch
Add the required peripheral clock for the efuse device.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pin
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pin
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson8.c
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson8b.c | 2
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson8b.c | 2
AO pull register definition is inverted between pull (up/down) and
pull enable. Fixing this allows to properly apply bias setting
through pinconf
Fixes: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson8.c
preferred to make a single patch to fix this but the commit
introducing the mistake the is different for each SoC, so a single patch
could be more difficult/annoying to backport.
Jerome Brunet (4):
pinctrl: meson: fix gxbb ao pull register bits
pinctrl: meson: fix gxl ao pull register bits
pinctrl
preferred to make a single patch to fix this but the commit
introducing the mistake the is different for each SoC, so a single patch
could be more difficult/annoying to backport.
Jerome Brunet (4):
pinctrl: meson: fix gxbb ao pull register bits
pinctrl: meson: fix gxl ao pull register bits
pinctrl
On Thu, 2018-10-25 at 22:58 +0200, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Thu, Oct 25, 2018 at 2:54 PM Jerome Brunet wrote:
> [snip]
> > > > > +static void clk_regmap_div_init(struct clk_hw *hw)
> > > > > +{
> > > > > + struc
On Thu, 2018-10-25 at 22:58 +0200, Martin Blumenstingl wrote:
> Hi Jerome,
>
> On Thu, Oct 25, 2018 at 2:54 PM Jerome Brunet wrote:
> [snip]
> > > > > +static void clk_regmap_div_init(struct clk_hw *hw)
> > > > > +{
> > > > > + struc
On Thu, 2018-10-25 at 19:48 +0800, Jianxin Pan wrote:
> Hi Jerome,
>
> On 2018/10/24 17:01, Jerome Brunet wrote:
> > On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> > > From: Yixun Lan
> > >
> > > The patch will add a MMC clock controll
On Thu, 2018-10-25 at 19:48 +0800, Jianxin Pan wrote:
> Hi Jerome,
>
> On 2018/10/24 17:01, Jerome Brunet wrote:
> > On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> > > From: Yixun Lan
> > >
> > > The patch will add a MMC clock controll
regmap_divider_with_init_ops;
... and this as well.
There is no reason to to init the divider to something other than what it is
already when we register the clock controller.
If your consumer needs the clocks to be initialised, it should call
clk_set_rate()
>
> #endif /* __CLK_RE
regmap_divider_with_init_ops;
... and this as well.
There is no reason to to init the divider to something other than what it is
already when we register the clock controller.
If your consumer needs the clocks to be initialised, it should call
clk_set_rate()
>
> #endif /* __CLK_RE
On Fri, 2018-10-19 at 11:03 -0700, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-10-19 09:12:53)
> > On 2018/10/19 1:13, Stephen Boyd wrote:
> > > Quoting Jianxin Pan (2018-10-17 22:07:25)
> > > > diff --git a/drivers/clk/meson/clk-regmap.c
> > > > b/drivers/clk/meson/clk-regmap.c
> > > > index
On Fri, 2018-10-19 at 11:03 -0700, Stephen Boyd wrote:
> Quoting Jianxin Pan (2018-10-19 09:12:53)
> > On 2018/10/19 1:13, Stephen Boyd wrote:
> > > Quoting Jianxin Pan (2018-10-17 22:07:25)
> > > > diff --git a/drivers/clk/meson/clk-regmap.c
> > > > b/drivers/clk/meson/clk-regmap.c
> > > > index
On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> From: Yixun Lan
>
> Document the MMC sub clock controller driver, the potential consumer
> of this driver is MMC or NAND. Also add four clock bindings IDs which
> provided by this driver.
>
> Reviewed-by: Rob Herring
> Signed-off-by:
+ OR MIT)
> +/*
> + * Amlogic Meson MMC Sub Clock Controller Driver
> + *
> + * Copyright (c) 2017 Baylibre SAS.
> + * Author: Jerome Brunet
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yixun Lan
> + */
> +
> +#include
> +#include &q
On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> From: Yixun Lan
>
> Document the MMC sub clock controller driver, the potential consumer
> of this driver is MMC or NAND. Also add four clock bindings IDs which
> provided by this driver.
>
> Reviewed-by: Rob Herring
> Signed-off-by:
+ OR MIT)
> +/*
> + * Amlogic Meson MMC Sub Clock Controller Driver
> + *
> + * Copyright (c) 2017 Baylibre SAS.
> + * Author: Jerome Brunet
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yixun Lan
> + */
> +
> +#include
> +#include &q
: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 29
: 6ac730951104 ("pinctrl: add driver for Amlogic Meson SoCs")
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 29
On Sat, 2018-10-13 at 18:08 +0200, Michael Turquette wrote:
> Quoting Christian Hewitt (2018-10-13 12:04:46)
> > On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
> > with reboot; e.g. a ~60 second delay between issuing reboot and the
> > board power cycling (and in some OS
On Sat, 2018-10-13 at 18:08 +0200, Michael Turquette wrote:
> Quoting Christian Hewitt (2018-10-13 12:04:46)
> > On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems
> > with reboot; e.g. a ~60 second delay between issuing reboot and the
> > board power cycling (and in some OS
This patcheset provide updates regarding reserved memory on
Amlogic platforms.
Jerome Brunet (2):
arm64: dts: meson: fix reserve memory regions
arm64: dts: meson-axg: drop FW reserved memory
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 21 +++--
arch/arm64/boot/dts/amlogic/meson
This patcheset provide updates regarding reserved memory on
Amlogic platforms.
Jerome Brunet (2):
arm64: dts: meson: fix reserve memory regions
arm64: dts: meson-axg: drop FW reserved memory
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 21 +++--
arch/arm64/boot/dts/amlogic/meson
while our
dts declares reserved memory on the same region with no-map.
The conflict produce the warning. This is fixed by using /reservedmem/
in our dts as well, which is probably something we should have done from
the beginning.
Cc: sta...@vger.kernel.org
Cc: Neil Armstrong
Signed-off-by: Jer
while our
dts declares reserved memory on the same region with no-map.
The conflict produce the warning. This is fixed by using /reservedmem/
in our dts as well, which is probably something we should have done from
the beginning.
Cc: sta...@vger.kernel.org
Cc: Neil Armstrong
Signed-off-by: Jer
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