On 2015/11/12 17:00, Paolo Bonzini wrote:
On 12/11/2015 08:06, Jian Zhou wrote:
I think you can just do this in kvm_x86_ops->set_msr. The old
implementation for DEBUGCTL MSR can be moved to svm.c.
I think you mean "moved to vmx.c"?
No, the old implementation is mov
On 2015/11/11 23:23, Paolo Bonzini wrote:
On 23/10/2015 11:15, Jian Zhou wrote:
Changelog in v2:
(1) move the implementation into vmx.c
(2) migraton is supported
(3) add arrays in kvm_vcpu_arch struct to save/restore
LBR MSRs at vm exit/entry time.
(4) add a parameter
On 2015/11/11 23:23, Paolo Bonzini wrote:
On 23/10/2015 11:15, Jian Zhou wrote:
Changelog in v2:
(1) move the implementation into vmx.c
(2) migraton is supported
(3) add arrays in kvm_vcpu_arch struct to save/restore
LBR MSRs at vm exit/entry time.
(4) add a parameter
On 2015/11/12 17:00, Paolo Bonzini wrote:
On 12/11/2015 08:06, Jian Zhou wrote:
I think you can just do this in kvm_x86_ops->set_msr. The old
implementation for DEBUGCTL MSR can be moved to svm.c.
I think you mean "moved to vmx.c"?
No, the old implementation is mov
On 2015/11/11 23:15, Paolo Bonzini wrote:
On 23/10/2015 11:15, Jian Zhou wrote:
data *msr_info)
}
break;
case MSR_IA32_DEBUGCTLMSR:
- if (!data) {
- /* We support the non-activated case already
On 2015/11/11 23:15, Paolo Bonzini wrote:
On 23/10/2015 11:15, Jian Zhou wrote:
data *msr_info)
}
break;
case MSR_IA32_DEBUGCTLMSR:
- if (!data) {
- /* We support the non-activated case already
Supported bits of MSR_IA32_DEBUGCTLMSR are DEBUGCTLMSR_LBR(bit 0),
DEBUGCTLMSR_BTF(bit 1) and DEBUGCTLMSR_FREEZE_LBRS_ON_PMI(bit 11).
Qemu can get/set contents of LBR MSRs and LBR status in order to
support migration.
Signed-off-by: Jian Zhou
Signed-off-by: Stephen He
---
arch/x86/kvm/x86.c
Using msr intercept bitmap and arrays(save/restore LBR MSRs)
in kvm_vcpu_arch struct to support LBR virtualization.
Add a parameter of kvm_intel module to permanently disable
LBRV.
Reorgnized the table of supported CPUs, LBRV can be enabled
or not according to the guest CPUID.
Signed-off-by: Jian
is reorgnized, LBRV
can be enabled or not according to the guest CPUID
Jian Zhou (4):
KVM: X86: Add arrays to save/restore LBR MSRs
KVM: X86: LBR MSRs of supported CPU types
KVM: X86: Migration is supported
KVM: VMX: details of LBR virtualization implementation
arch/x86/include/asm/kvm_host.h
Add arrays in kvm_vcpu_arch struct to save/restore
LBR MSRs at vm exit/entry time.
Add new hooks to set/get DEBUGCTLMSR and LBR MSRs.
Signed-off-by: Jian Zhou
Signed-off-by: Stephen He
---
arch/x86/include/asm/kvm_host.h | 26 --
1 file changed, 20 insertions(+), 6
Macros about LBR MSRs.
Signed-off-by: Jian Zhou
Signed-off-by: Stephen He
---
arch/x86/include/asm/msr-index.h | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b98b471
Using msr intercept bitmap and arrays(save/restore LBR MSRs)
in kvm_vcpu_arch struct to support LBR virtualization.
Add a parameter of kvm_intel module to permanently disable
LBRV.
Reorgnized the table of supported CPUs, LBRV can be enabled
or not according to the guest CPUID.
Signed-off-by: Jian
is reorgnized, LBRV
can be enabled or not according to the guest CPUID
Jian Zhou (4):
KVM: X86: Add arrays to save/restore LBR MSRs
KVM: X86: LBR MSRs of supported CPU types
KVM: X86: Migration is supported
KVM: VMX: details of LBR virtualization implementation
arch/x86/include/asm/kvm_host.h
Supported bits of MSR_IA32_DEBUGCTLMSR are DEBUGCTLMSR_LBR(bit 0),
DEBUGCTLMSR_BTF(bit 1) and DEBUGCTLMSR_FREEZE_LBRS_ON_PMI(bit 11).
Qemu can get/set contents of LBR MSRs and LBR status in order to
support migration.
Signed-off-by: Jian Zhou
Signed-off-by: Stephen He
---
arch/x86/kvm/x86.c
Macros about LBR MSRs.
Signed-off-by: Jian Zhou
Signed-off-by: Stephen He
---
arch/x86/include/asm/msr-index.h | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b98b471
Add arrays in kvm_vcpu_arch struct to save/restore
LBR MSRs at vm exit/entry time.
Add new hooks to set/get DEBUGCTLMSR and LBR MSRs.
Signed-off-by: Jian Zhou
Signed-off-by: Stephen He
---
arch/x86/include/asm/kvm_host.h | 26 --
1 file changed, 20 insertions(+), 6
Add arrays in kvm_vcpu_arch struct to save/restore
LBR MSRs at vm exit/entry time.
Add new hooks to set/get DEBUGCTLMSR and LBR MSRs.
Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
Signed-off-by: Stephen He <herongguang...@huawei.com>
---
arch/x86/include/asm/kvm
is reorgnized, LBRV
can be enabled or not according to the guest CPUID
Jian Zhou (4):
KVM: X86: Add arrays to save/restore LBR MSRs
KVM: X86: LBR MSRs of supported CPU types
KVM: X86: Migration is supported
KVM: VMX: details of LBR virtualization implementation
arch/x86/include/asm/kvm_host.h
Supported bits of MSR_IA32_DEBUGCTLMSR are DEBUGCTLMSR_LBR(bit 0),
DEBUGCTLMSR_BTF(bit 1) and DEBUGCTLMSR_FREEZE_LBRS_ON_PMI(bit 11).
Qemu can get/set contents of LBR MSRs and LBR status in order to
support migration.
Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
Signed-off-by: Step
Macros about LBR MSRs.
Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
Signed-off-by: Stephen He <herongguang...@huawei.com>
---
arch/x86/include/asm/msr-index.h | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/m
Using msr intercept bitmap and arrays(save/restore LBR MSRs)
in kvm_vcpu_arch struct to support LBR virtualization.
Add a parameter of kvm_intel module to permanently disable
LBRV.
Reorgnized the table of supported CPUs, LBRV can be enabled
or not according to the guest CPUID.
Signed-off-by: Jian
Macros about LBR MSRs.
Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
Signed-off-by: Stephen He <herongguang...@huawei.com>
---
arch/x86/include/asm/msr-index.h | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/m
Using msr intercept bitmap and arrays(save/restore LBR MSRs)
in kvm_vcpu_arch struct to support LBR virtualization.
Add a parameter of kvm_intel module to permanently disable
LBRV.
Reorgnized the table of supported CPUs, LBRV can be enabled
or not according to the guest CPUID.
Signed-off-by: Jian
Add arrays in kvm_vcpu_arch struct to save/restore
LBR MSRs at vm exit/entry time.
Add new hooks to set/get DEBUGCTLMSR and LBR MSRs.
Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
Signed-off-by: Stephen He <herongguang...@huawei.com>
---
arch/x86/include/asm/kvm
is reorgnized, LBRV
can be enabled or not according to the guest CPUID
Jian Zhou (4):
KVM: X86: Add arrays to save/restore LBR MSRs
KVM: X86: LBR MSRs of supported CPU types
KVM: X86: Migration is supported
KVM: VMX: details of LBR virtualization implementation
arch/x86/include/asm/kvm_host.h
Supported bits of MSR_IA32_DEBUGCTLMSR are DEBUGCTLMSR_LBR(bit 0),
DEBUGCTLMSR_BTF(bit 1) and DEBUGCTLMSR_FREEZE_LBRS_ON_PMI(bit 11).
Qemu can get/set contents of LBR MSRs and LBR status in order to
support migration.
Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
Signed-off-by: Step
Does it depend on vPMU _for Linux guests_ or in general? My impression
is that LBR can be used by the guest independent of the PMU.
I think only for Linux guests.
I googled how to enable LBR on other guests(except Linux guests),
e.g. Windows, and got no developer manuals about it.
On 2015/10/14 19:30, Paolo Bonzini wrote:
On 14/10/2015 13:26, Jian Zhou wrote:
On 12/10/2015 20:44, Paolo Bonzini wrote:
In addition, the MSR numbers may differ between the guest and the host,
because it is possible to emulate e.g. a Core CPU on a Core 2 CPU. So I
recommend against using
On 2015/10/14 19:30, Paolo Bonzini wrote:
On 14/10/2015 13:26, Jian Zhou wrote:
On 12/10/2015 20:44, Paolo Bonzini wrote:
In addition, the MSR numbers may differ between the guest and the host,
because it is possible to emulate e.g. a Core CPU on a Core 2 CPU. So I
recommend against using
Does it depend on vPMU _for Linux guests_ or in general? My impression
is that LBR can be used by the guest independent of the PMU.
I think only for Linux guests.
I googled how to enable LBR on other guests(except Linux guests),
e.g. Windows, and got no developer manuals about it.
On 12/10/2015 20:44, Paolo Bonzini wrote:
On 12/10/2015 14:10, Jian Zhou wrote:
ping...
I think your expectations for review RTT are a bit too optimistic.
I have only worked 4 hours since you posted the patch... But it was on
my list anyway, so let's do it.
Thank for Paolo's time
On 12/10/2015 20:44, Paolo Bonzini wrote:
On 12/10/2015 14:10, Jian Zhou wrote:
ping...
I think your expectations for review RTT are a bit too optimistic.
I have only worked 4 hours since you posted the patch... But it was on
my list anyway, so let's do it.
Thank for Paolo's time
ping...
> Using vmx msr store/load mechanism and msr intercept bitmap
> to implement LBR virtualization.
>
> Signed-off-by: Jian Zhou
> Signed-off-by: Stephen He
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 2beee03..244
ping...
> Using vmx msr store/load mechanism and msr intercept bitmap
> to implement LBR virtualization.
>
> Signed-off-by: Jian Zhou <jianjay.z...@huawei.com>
> Signed-off-by: Stephen He <herongguang...@huawei.com>
>
> diff --git a/arch/x86/include/asm/
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